JP3019746B2 - LCD panel drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel driving apparatus suitable for driving a matrix type liquid crystal panel having various liquid crystals such as a smectic liquid crystal and a nematic liquid crystal.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal panel driving apparatus of this type includes, for example, a liquid crystal having n scanning electrodes and m signal electrodes constituting a matrix electrode and having an antiferroelectric liquid crystal as a liquid crystal. There is one for driving the panel. This liquid crystal drive device includes a scan electrode drive circuit that drives n scan electrodes and a signal electrode drive circuit that drives m signal electrodes.

The scan electrode drive circuit sequentially selects these scan electrodes in a line-sequential manner by applying a voltage of a predetermined waveform to the n scan electrodes. Further, the signal drive circuit applies a voltage having a waveform corresponding to image data to be displayed on a pixel on the selected scan electrode to the m signal electrodes in synchronization with the sequential selection of scan electrodes of the scan electrode drive circuit. Then, the liquid crystal panel is driven.

[0004]

Incidentally, there is a conventional scan electrode drive circuit having the structure shown in FIG. This scan electrode drive circuit has an n-shaped scan electrode (hereinafter, referred to as an n-shaped scan electrode).
Corresponding to the scan electrodes Y ₁ , Y ₂ ,..., Y _n−1 , Y _n ), the data latch 1 of 3n bits, n level shifters 2 and n analog switches And the analog switch circuit 3 of FIG.

Here, the number of analog switches of each analog switch circuit 3 is determined by the power supply voltages Vhn, Ve, Vwn, Vwp
And Vhp. Each analog switch circuit 3 outputs a power supply voltage as a voltage having the predetermined waveform by selectively turning on each analog switch. Therefore, the total number of analog switches in each analog switch circuit 3 needs to be n times the number of voltages required for driving the scan electrodes. For this reason, there is a problem that the circuit scale of the scan electrode driving circuit increases and the cost increases.

On the other hand, a detailed study of the case where the scan electrode drive circuit drives line-sequentially shows that the scan electrode drive circuit outputs different voltages at different times without outputting the same voltage at the same time. Usually, it is output. Therefore, if such a feature of the line sequential driving is effectively used, it is possible to output a plurality of voltages at different times by driving the same analog switch of each analog switch circuit 3.

Therefore, in order to cope with such a problem, the present invention reduces the number of switches in a scan electrode driving circuit in a liquid crystal panel driving device by effectively utilizing a characteristic inherent in a line sequential scanning system. The purpose is to:

[0008]

In order to achieve the above object, according to the first aspect of the present invention, an n-shaped scanning electrode (Y ₁ , Y ₂ ... Y _n-1 , Y _n ) and m Applied to a liquid crystal panel (10) forming a matrix pixel by the signal electrodes (X ₁ , X ₂ ... X _m-1 , X _m ) based on a line-sequential driving voltage having a plurality of levels. Scan electrode driving means (2) for sequentially selecting and driving n scan electrodes
0, 30, 50) and in synchronization with the selection of the scanning electrode by the scanning electrode driving means, the m signal electrodes are driven based on the signal voltage specifying the image data signal corresponding to the pixel on the selected scanning electrode. Signal electrode driving means (20, 40,
60), the scanning electrode driving means is provided corresponding to each of the n-shaped scanning electrodes, and switches the level of the line-sequential driving voltage to change the level of the n-shaped scanning electrodes. N switching means (A _{y1 to} A _yn ) for sequentially applying at least two of the line-sequential driving voltages which are output at different times in synchronization with the selection of the scanning electrodes. A switching means (SW) for performing the operation is provided in common for each of the switch means.

According to a second aspect of the present invention, in the liquid crystal panel driving device according to the first aspect, each of the switch means has a smaller number of analog switches (51 to 51) than the number of levels of the line-sequential drive voltage. 54), wherein the switching means comprises a single analog switch (SW) for switching at least two of a plurality of levels of the line-sequential driving voltage. According to the third aspect of the present invention,
2. The liquid crystal panel driving device according to claim 1,
Means for positive and negative selection when the scanning electrode is in a selected state.
Depending on the selection period, a plurality of levels of the line-sequential driving voltage
Switching between two different polarities
You. According to the fourth aspect of the present invention, the third aspect of the present invention is provided.
In the liquid crystal panel driving device of the
Are at positive and negative write voltages.
There is a feature.

[0010] The symbols in parentheses of the above means indicate the correspondence with the concrete means described in the embodiments described later.

[0011]

According to the invention as set forth in any one of the first to fourth aspects , the scan electrode driving means is adapted to apply the scan electrode driving means to the n-shaped scan electrodes by utilizing the fact that each scan electrode is scanned line-sequentially. N switch means for switching the level of the line-sequential drive voltage and sequentially applying the line-sequential drive voltage to the n-shaped scan electrodes are provided, and a plurality of levels of the line-sequential drive voltage are provided at different times. Switching means for performing at least two switching operations output in synchronism with the selection of the scanning electrode is provided in common for each switching means.

Thus, each switch means conventionally requires two analog switches for outputting the two levels of drive voltage, but each switch means becomes one analog switch. In addition, the function similar to that of the conventional scan electrode driving means can be exhibited only by adding one analog switch as a switching means common to each switching means. This allows
The reduction in the number of analog switches in the scan electrode driving means can be ensured, and the cost can be reduced by reducing the circuit scale.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a matrix type liquid crystal display device to which the present invention is applied.
It comprises a liquid crystal panel 10 and a liquid crystal panel driving device E for driving the liquid crystal panel 10 in a matrix.

The liquid crystal panel 10 has a matrix of pixels.
Scan electrodes Y constituting₁, Y _Two... Y_n-1, Y
_nAnd m signal electrodes X₁, X_Two... X_m-1, X_mTo
To have an antiferroelectric liquid crystal as the liquid crystal
It is configured. The liquid crystal panel drive E is controlled by
Circuit 20, dual power supply circuits 30, 40, and scan electrode drive
A circuit 50 and a signal electrode drive circuit 60 are provided.
The liquid crystal panel driving device E of the
Under the control of the power supply circuit 20 and an external circuit.
Each scan electrode from the path 30 via the scan electrode drive circuit 50
Y₁, Y_Two... Y_n-1, Y_nDrive voltage of predetermined waveform
(See FIG. 6) to sequentially select the scanning electrodes,
In synchronization with this, the image to be displayed on the pixel on the selected scan electrode
A drive voltage having a predetermined waveform corresponding to image data is applied to each signal electrode X
₁, X_Two... X_m-1, X _mTo the liquid crystal panel 1
0 is displayed.

The control circuit 20 controls a scan electrode drive circuit control signal and a signal electrode drive signal for driving the scan electrode drive circuit 50 based on a vertical synchronizing signal VSYC and a horizontal synchronizing signal HSYC for displaying an image from an external circuit. A signal electrode drive circuit control signal for driving the circuit 60 is generated. In this case, the scan electrode drive circuit control signals include the S101 signal, the S102 signal, the SCC signal, and the DP signal.
_{Consists of the y} signal. Here, S101 signal and S102 signal is a signal for specifying one of the states of the scan electrodes _{Y 1, Y 2 ··· Y n} -1, Y n. In this embodiment, both S10
1 signal and S102 signal are both low level (that is, L)
At this time, the state of erasure is specified. When the S101 signal is L and the S102 signal is at a high level (that is, H), the selected state is specified. When the S101 signal is H and the S102 signal is L, the holding state is specified.

The SCC signal has a rising edge.
And a data latch L_yBoth S101 signals to
The timing for taking in the S102 signal is specified. DP_y
The signal is applied to each scan electrode Y₁, Y_Two... Y_n-1, Y_nOne
To determine the polarity of the selected voltage. example
For example, when the scanning electrode is in the selected state, during the positive selection period, D
P _yThe signal switches from L to H. On the other hand, the signal electrode
The drive circuit control signals are RCK signal, SIC signal, STD
Signal and DP_xConsists of signals.

The scan electrode driving circuit 50 includes a power supply circuit 30
n-shaped scanning electrode Y₁, Y_Two... Y _n-1, Y_nBetween
Connected, the power supply circuit 30 has five levels Vhn,
Ve, Vwn, Vwp and Vhp (see Fig. 4)
Live. The scan electrode drive circuit 50 has 3n bits of data.
Latch L_yAnd (n + 1) level shifters S_y0Or S
_ynAnd n analog switch circuits A_y1Or A_ynAnd
And a analog switch SW.
Switch L_yNumber of bits, level shifter S_y1Or S_ynNumber of
And analog switch circuit A_y1Or A_ynThe number of scanning electrodes
Y₁, Y_Two... Y_n-1, Y_nCorresponds to the number of

The data latch _Ly is connected to the control circuit 2
0 to the scan electrode drive circuit control signal (S101 signal, S1
02 signal, SCC signal and DP _y signal).
Thus, the data latch L _y takes to sync S101 signal and S102 signal to the SCC signal, the scan electrodes Y ₁ specified by these S101 signal and S102 _{signal, Y 2 ··· Y n-1} , Based on the state of Y _n , data is created and stored using the power supply voltage from the power supply circuit 30.

[0019] In this case, in preparing the data in the data latch L _y, DP _y signal determines the polarity of the voltage applied to the selected scanning electrodes. Further, the level shifter S _y0 generates a switching signal for switching the analog switch SW based on the DP _y signals from the control circuit 20. Each level shifter S _y1 to S _yn outputs a switching signal for switching the analog switches in each corresponding data decoded by the analog switch circuit A _y1 through A _yn of the data latch L _y, respectively.

The analog switch SW includes a level shifter S
_When the switching signal from _y0 is H, each analog switch 51 is connected to a terminal of the power supply circuit (corresponding to the power supply voltage Vwp). On the other hand, when the switching signal from the level shifter S _y0 is L, the analog switch SW connects each analog switch 51 to a terminal of the power supply circuit (corresponding to the power supply voltage Vwn).

The analog switches 51 of the analog switch circuits A _{y1 to} A _yn are turned on / off by switching signals from the level shifters S _{y1 to} S _yn . The remaining analog switches 52, 53, 54 of the analog switch circuits A _{y1 to} A _yn are connected to respective output terminals (corresponding to respective power supply voltages Vhp, Vhn, Ve) of the power supply circuit 30.

Thus, the voltage output from the scan electrode drive circuit 50 to each scan electrode is switched by turning on / off an analog switch provided for each output. In each of the erasing and holding periods, the analog switches of the respective outputs connected to the respective electrodes to which the erasing voltage V _e , the positive holding voltage V _hp or the negative holding voltage V _hn are applied are turned on, so that a predetermined A voltage waveform is output.

[0023] The selection period, and the analog switch is turned on for each output connected to the electrode the write voltage is applied, with the analog switches a write voltage write voltage is applied to the electrodes applied by the polarity control signal DP _y The voltage is switched to the positive write voltage Vwp or the negative write voltage Vwn to output a voltage with a predetermined waveform. Here, the operation of the scan electrode driving circuit 50 will be described with reference to FIG.

The scan electrode driving circuit 50 controls each of the scan electrodes Y ₁ , Y _2, ... Based on each power supply voltage from the power supply circuit 30.
An erase voltage, a select voltage, and a hold voltage corresponding to the erase, select, and hold states are sequentially output to Y _n-1 and Y _n . Further, in order to perform AC driving, the scan electrode driving circuit 50 is used.
Reverses the positive and negative polarities of the selection voltage for each selection period.

[0025] Incidentally, the case of driving the scan electrodes Y ₁ by the scan electrode driving circuit 50 will be described as an example. Scan electrode driving circuit 50, the erase time, and outputs an erase voltage V _e to erase all the pixels display on the scanning electrodes.
Then, the scan electrode driving circuit 50 operates during the positive selection period.
A negative write voltage V _wn is output once, and then a positive write voltage V _WP is output. Also, the scan electrode driving circuit 50
Outputs the holding voltage V _hp during the positive holding period, and holds this holding voltage V _hp until the next erase time. As a result, the display contents are held until the next erasing time.

After the erasing time, the scan electrode driving circuit 50 performs AC driving. Therefore, the scan electrode drive circuit 50 enters a negative selection period having a polarity opposite to that of the previous selection period, and once outputs the positive write voltage V _wp and then outputs the negative write voltage V _wn . Further, scan electrode driving circuit 50 outputs holding voltage V _hn during the negative holding period, and holds this holding voltage V _hn until the next erasing period.
As a result, the display contents are held until the next erasing time.
Thereafter, such an operation is repeated by the scan electrode drive circuit 50.

[0027] In this case, since the scan electrodes Y ₁ to line sequential scanning in the order, the waveform of the output of the scan electrode driving circuit 50, to the scanning electrodes Y ₂ after the scanning electrodes, a waveform shifted by selection period minutes . At that time, in order to prevent the flicker of the display, for example, scan electrodes Y ₁ is positive, the scan electrode Y ₂ is negative, so that the scanning electrode Y ₃ is positive, the voltage polarity is made to differ for each scanning electrode .

When each scanning electrode is in the selected state,
For example, in the positive selection period, as described above, since the DP _y signal switches from L to H, the scan electrode driving circuit 50
_Changes from V _wn to V _wp . in this way,
Decoding result of the DP _y signal inputted to the data latch L _y is, directly determines the polarity of the selection voltage. Incidentally, Turning to the holding period, the polarity maintains the state of the decoding result of a previous selection period entered the DP _y signal, DP _y
It does not depend on the signal.

The scan electrode driving circuit 50 controls each of the scan electrodes Y ₁ , Y ₂ ... Y _n-1 , Y _n based on each power supply voltage from the power supply circuit 30 as shown in FIG. , A drive voltage having a predetermined line-sequential scanning waveform corresponding to the erase, select and hold states is sequentially applied. Signal electrode drive circuit 60
Is connected between the power supply circuit 40 and the liquid crystal panel 10, the power supply circuit 40 generates a power supply voltage of the eight levels V ₁ to V ₈ (see FIG. 6).

The signal electrode drive circuit 60 includes m data latches L _{xf1 to} L _xfm , m data latches L _{xs1 to} L _xsm , m level shifters S _{x1 to} S _xm , and m analog switches is constituted by a circuit A _x1 to A _xm, these data latches L _xf1 to L _xfm, data latch L _xs1 to L _xsm, level shifter S _x1 to S _xm and the analog switch circuits A _x1 to A _xm, respectively, each X _m-1 , X _m are provided corresponding to the signal electrodes X ₁ , X ₂ .

Here, each data latch L _{xf1 to} L _{xfm
Each of the} data latches L _{xs1 to} L _xsm comprises a 3-bit data latch. Each of the analog switch circuits A _{x1 to} A _xm includes eight analog switches. Each of the data latches L _{xf1 to} L _xfm receives an image data signal DAP signal for displaying an image from an external circuit, and receives an SIC signal and an STD signal from the control circuit 20.
In the present embodiment, an eight-gradation display for performing eight-stage brightness control is employed. Therefore, the image data signal DAP
The signal is a 3-bit data signal indicating eight levels of brightness for each pixel.

Therefore, each of the data latches L _{xf1 to} L _xfm
Creates a data signal based on the image data signal DAP signal as follows. For each data latch L _{xf1 to} L _xfm , a 3-bit image data signal DAP is
With each of the signal electrodes X ₁ to the signal electrode X _m is inputted as the corresponding serial data, SIC signal and STD signal is input from the control circuit 20.

[0033] Here, the image data signals DAP is in accordance with the scanning of the scanning electrodes, from the image data signals of pixels arranged on the scanning electrode Y ₁ to the image data signals of pixels arranged on the scan electrodes Y _n , Each data latch L _xf1 through L
Input to _xfm in order. In FIG. 5, the symbols D _{1, i} are
Shows a set of image data signals of pixels arranged on the scanning electrode Y _1. Each of the symbols D _{1,1 to} D _{1, m} indicates an image data signal corresponding to each of the signal electrodes X _{1 to} X _m therein.

Thus, the image data signal DAP is
When D signal is H, it is input as a data signal corresponding to the signal electrodes X _1, is taken into the data latch L _xf1 in synchronization with the rise of the SIC signal. Thereafter, the image data signal DAP is taken into these data latches L _{xf2 to} L _xfm as data signals corresponding to the signal electrodes X _{2 to} X _m in synchronization with the rise of the SIC signal.

Thus, each of the data latches L _{xf1 to} L _{xf1 to} L
Image data signals are stored in _xfm for the pixels arranged on one scanning electrode. Each such data latch L
_xf1 to operation of the L _xfm is repeated for each scan electrode. The image data signals DAP stored in the data latches L _{xf1 to} L _xfm in this manner are sequentially transferred to and stored in the data latches L _{xs1 to} L _xsm in synchronization with each rise of the RCK signal. Also, DP _x from the external circuit
When the signal is in accordance with the RCK signal, each data latch L _{xs1 to} L _{xs1 to} L
Input to _xsm .

Each of the level shifters S _{x1 to} S _xm decodes the data signal transferred to each of the data latches L _{xs1 to} L _xsm and _applies it to each of the analog switch circuits A _{x1 to} A _xm as a switching signal. Each of the analog switch circuits A _{x1 to} A _xm switches the voltage to be applied to the signal electrodes X _{1 to} X _m from the power supply circuit 40. The switching timing of each analog switch of these analog switch circuits A _{x1 to} A _xm is , Each data latch L _xs1 through L
It is determined by the image data signal and DP signal stored in _xsm .

[0037] For example, when DP _x signal is L, the image data signal of 3 bits corresponding to the output to the signal electrodes (0,0,0), (0,0,1) (1, 1,
0) and (1, 1, 1), while the power supply circuit 40
, The analog switches of the analog switch circuits A _{x1 to} A _xm connected to the respective output terminals (terminals corresponding to the power supply voltages V ₈ , V ₇ ... V ₁ ) are turned on.

DP_xWhen the signal is H, output to each signal electrode
The 3-bit image data signal corresponding to the force is (0, 0,
0), (0, 0, 1) ... (1, 1, 0), (1,
1, 1), whereas each output terminal of the power supply circuit 40
(Each power supply voltage V₁... V₇, V ₈To the corresponding terminal)
Each connected analog switch circuit A_x1Or A_xm
Is turned on.

As described above, the scan electrode driving circuit 50
Signal and DP _y signal to the signal electrode driving circuit 60
In synchronization with the RCK signal and DP _x signals to and entering one selection period before the image data signals of pixels arranged on the scanning electrodes in a selected period to the signal electrode driving circuit 60, in FIG. 6 The liquid crystal drive voltage waveform shown is realized. As described above, each of the scan electrodes Y ₁ to Y _n sequentially scanning of the line
Re leverage Rukoto, in the scanning electrode driving circuit 50,
An analog switch SW is connected between both output terminals of the power supply circuit 30 (corresponding to both power supply voltages V _wp and V _wn ) and each analog switch 51, and the switching operation of the analog switch SW is performed by the level shifter S _y0. did.

Thus, the single analog switch SW
By each analog switch circuit A _y1Or A_ynThe analog
Power supply voltage V to switch 51_wp, V_wnSelective grant of
Can be controlled. Therefore, conventionally, each analog switch circuit
A_y1Or A_ynAt both power supply voltages V_wp, V
_wnRequires two analog switches for the output of
What was the analog switch circuit A_y1Or A_ynTo
And one analog switch 51
Log switch circuit A_y1Or A_ynSwitch common to all
Only one analog switch SW is added as a switch.
The same function as the conventional scan electrode drive circuit can be exhibited. This
As a result, the analog switch in the scan electrode driving circuit 50 is
Switch count can be ensured, and
Cost reduction can be realized.

Each of the analog switch circuits A _{y1 to} A _{y1 to} A
The number of total analog switches required in _yn is n-2 reduction compared to the conventional configuration, but the analog switches that supply the write voltage have a higher voltage than the erase voltage and the hold voltage. In order to switch at high speed, a transistor having a low on-resistance is required as a component of the analog switch. Therefore, since the transistor size increases, the effect of reducing the circuit space exceeds the effect of reducing the total number of analog switches. For example, when the scan electrode drive circuit is formed as a monolithic IC, the chip size can be reduced by about 30% as compared with the conventional one.

In this embodiment, an example is described in which the invention is applied to a liquid crystal panel driving device for a liquid crystal panel 10 in which antiferroelectric liquid crystal is sealed. However, the present invention is not limited to this. The present invention may be applied to a liquid crystal panel driving device for a liquid crystal panel in which each liquid crystal such as a smectic liquid crystal or a nematic liquid crystal is sealed. Also,
The present invention is not limited to the liquid crystal panel for a liquid crystal display device, and may be applied to, for example, a liquid crystal panel driving device for a liquid crystal panel for a liquid crystal switch.

In practicing the present invention, the driving waveform of each scanning electrode of the liquid crystal panel 10 is not limited to that of the above embodiment, and the scanning electrode driving circuit outputs a driving voltage by a line sequential driving method. The drive voltage may have any waveform as long as it exists. Accordingly, the analog switch SW only needs to switch between the two drive voltages output at different times, and is not limited to the two voltages described in the above embodiment. Further, the number of the analog switches SW may be plural.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a detailed circuit diagram of the scan electrode driving circuit of FIG.

FIG. 3 is a detailed circuit diagram of the signal electrode driving circuit of FIG. 1;

FIG. 4 is a timing chart showing an operation of the scan electrode driving circuit of FIG. 2;

FIG. 5 is a timing chart showing the operation of the signal electrode drive circuit of FIG. 2;

FIG. 6 is a timing chart showing output waveforms of the liquid crystal panel driving device of FIG.

FIG. 7 is a timing chart showing the operation of a conventional scan electrode drive circuit.

[Explanation of symbols]

10: liquid crystal panel, 20: control circuit,
30, 40: power supply circuit, 50: scan electrode drive circuit, 60: signal electrode drive circuit, _{Ay1 to Ayn} ...
Analog switch circuit, 51 to 54 ... analog switch, L _y ... data latch, SW ... analog switches, S _y0 to S _yn ... level shifter.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 545 G02F 1/133 560

Claims (4)

(57) [Claims] The present invention is applied to a liquid crystal panel forming a matrix pixel by n-shaped scanning electrodes and m-shaped signal electrodes, and sequentially selects the n-shaped scanning electrodes based on a line-sequential driving voltage having a plurality of levels. Scanning electrode driving means for driving the scan electrodes in synchronization with the selection of the scanning electrodes by the scanning electrode driving means, based on a signal voltage for specifying an image data signal corresponding to a pixel on the selected scanning electrode. And a signal electrode driving means for driving the scan electrode driving means, wherein the scanning electrode driving means is provided corresponding to each of the n-shaped scanning electrodes, and switches the level of the line-sequential driving voltage to change the level thereof. It includes n switching means for sequentially imparting the n-shaped scanning electrodes, and different from the time out of a plurality of levels of the line sequential driving voltage
A liquid crystal panel driving device, wherein switching means for switching at least two outputted signals in synchronization with the selection of the scanning electrode is provided in common for each of the switching means. 2. The method according to claim 1, wherein each of the switch units includes a smaller number of analog switches than the number of levels of the line-sequential drive voltage, and the switch unit includes at least two of a plurality of levels of the line-sequential drive voltage. 2. The liquid crystal panel driving device according to claim 1, comprising a single analog switch for switching. 3. The switching means, wherein the scanning electrode is selected.
In the selected state, the line order is determined according to the positive and negative selection periods.
Of the multiple levels of the next drive voltage, two with different polarities
2. The liquid crystal panel according to claim 1, wherein the liquid crystal panel is switched.
Drive. 4. The two levels having different polarities are positive
A write voltage and a negative write voltage.
The liquid crystal panel driving device according to claim 3.