JPH08327977A - Liquid crystal panel driving device - Google Patents

Abstract

PURPOSE: To reduce the number of switches in an operation electrode drive circuit by effectively utilizing a characteristic peculiar to a line sequential scan system. CONSTITUTION: The level shifter Sy0 of the operation electrode drive circuit 50 generates a switch signal for switching an analog switch SW based on a DP, signal. The level shifters Sy1 to Syn output the switch signal for decoding respective answering data from a data latch Ly and switching; respective analog switches of respective analog switch circuits Ay1 to Ayn . The analog switch SW connects respective analog switches 51 to a terminal answer to a source voltage Vwp of a power source circuit or the terminal corresponding to the source voltage Vwn of the power source circuit by the switch signal from the level shifter Sy0 . Respective analog switches 51 are turned on/off by the switch signals from the level shifters Sy1 to Syn .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel driving device suitable for driving a matrix type liquid crystal panel having various liquid crystals such as smectic liquid crystals and nematic liquid crystals.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal panel driving device of this type, for example, a liquid crystal having n-row scanning electrodes and m-row signal electrodes forming a matrix-like electrode, and an antiferroelectric liquid crystal as a liquid crystal. There is one for driving the panel. This liquid crystal drive device includes a scan electrode drive circuit that drives n scan electrodes and a signal electrode drive circuit that drives m signal electrodes.

Then, the scan electrode drive circuit applies a voltage having a predetermined waveform to the n scan electrodes to sequentially select the scan electrodes by a line sequential method. In addition, the signal drive circuit applies a voltage having a waveform corresponding to image data to be displayed on the pixel on the selected scan electrode to the m signal electrodes in synchronization with the sequential selection of the scan electrodes of the scan electrode drive circuit. Drive the liquid crystal panel.

[0004]

By the way, there is a conventional scan electrode driving circuit having a structure shown in FIG. This scan electrode drive circuit is composed of n-shaped scan electrodes (hereinafter,
(Corresponding to the scanning electrodes Y ₁ , Y ₂ , ..., Y _n-1 , Y _n ) corresponding to the scanning electrodes Y ₁ , Y ₂ , ... The analog switch circuit 3 of FIG.

Here, the number of analog switches in each analog switch circuit 3 is the power supply voltage Vhn, Ve, Vwn, Vwp.
And a value equal to the number of Vhp. Then, each analog switch circuit 3 outputs the power supply voltage as the voltage of the above-mentioned predetermined waveform by selectively turning on each analog switch. Therefore, the total number of analog switches in each analog switch circuit 3 needs to be n times the number of analog switches required to drive the scan electrodes. Therefore, there is a problem in that the circuit scale of the scan electrode drive circuit increases and the cost increases.

On the other hand, when the scan electrode drive circuit is line-sequentially driven, the scan electrode drive circuit outputs different voltages at different times without outputting the same voltage at the same time. It is usually designed to output. Therefore, by effectively utilizing such a characteristic of line-sequential driving, it is possible to output a plurality of voltages at different times by driving the same analog switch of each analog switch circuit 3.

Therefore, in order to cope with such a situation, the present invention effectively utilizes the characteristics peculiar to the line-sequential scanning method in the liquid crystal panel driving device to reduce the number of switches in the scanning electrode driving circuit. The purpose is to

[0008]

[Means for Solving the Problems]
Therefore, in the invention according to claim 1, in the n-shaped scanning electrode
(Y₁, Y₂... Y_n-1, Y_n) And m signal electrodes
(X₁, X₂... X_m-1, X_m) By matrix
Applied to a liquid crystal panel (10) that forms a pixel.
Based on the line-sequential driving voltage having several levels,
Scan electrode driving means (2) for sequentially selecting and driving the scan electrodes
0, 30, 50) and scanning by this scanning electrode driving means
Corresponds to the pixel on the selected scan electrode in synchronization with electrode selection.
Based on the signal voltage that specifies the image data signal
Signal electrode driving means (20, 40,
60) and a liquid crystal panel driving device comprising:
The scanning electrode driving means corresponds to each of the n-shaped scanning electrodes.
The line-sequential drive voltage is cut off at that level.
Instead, n switches that are sequentially applied to the n-shaped scan electrodes are provided.
Chi means (A _y1Through A_yn) Of the line-sequential drive voltage
Switching at least two of a plurality of levels
The switching means (SW) that operates in synchronization with the selection of the scan electrodes is
It is provided in common to each of the switch means
A liquid crystal panel drive device is provided.

According to a second aspect of the present invention, in the liquid crystal panel drive device according to the first aspect, each of the switch means has a smaller number of analog switches than the level number of the line sequential drive voltage. 54), and the switching means is configured by a single analog switch (SW) that switches at least two of the plurality of levels of the line-sequential drive voltage.

The reference numerals in parentheses of the above means indicate the correspondence with the concrete means described in the embodiments described later.

[0011]

According to the invention described in claim 1 or 2, the scanning electrode driving means corresponds to the n-shaped scanning electrodes by utilizing the fact that the scanning electrodes are line-sequentially scanned. Is provided for switching the level of the line-sequential drive voltage and sequentially applying it to the n-shaped scan electrodes, and scans at least two of a plurality of levels of the line-sequential drive voltage. Switching means for synchronizing with the selection of the electrodes is provided in common for each switch means.

As a result, each switch means conventionally required two analog switches for outputting the above-mentioned two levels of drive voltage, but now each switch means becomes one analog switch. Moreover, the same function as that of the conventional scan electrode driving means can be exhibited by only adding one analog switch as a switching means common to each switch means. This allows
A reduction in the number of analog switches in the scan electrode driving means can be ensured, and cost reduction can be realized by reducing the circuit scale.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a matrix type liquid crystal display device to which the present invention is applied.
The liquid crystal panel 10 and a liquid crystal panel driving device E for driving the liquid crystal panel 10 in a matrix are configured.

The liquid crystal panel 10 has pixels arranged in a matrix.
N scanning electrodes Y forming the₁, Y ₂... Y_n-1, Y
_nAnd signal electrodes X on m lines₁, X₂... X_m-1, X_mTo
And have an antiferroelectric liquid crystal as the liquid crystal.
It is configured. The liquid crystal panel drive device E is a controller.
Drive circuit 20, both power supply circuits 30, 40, and scan electrode drive
A circuit 50 and a signal electrode drive circuit 60 are provided.
The liquid crystal panel drive device E of FIG.
Controlled by the control circuit 20 and an external circuit,
Each scanning electrode from the path 30 through the scanning electrode driving circuit 50
Y₁, Y₂... Y_n-1, Y_nDrive voltage of a predetermined waveform
(See FIG. 6) to sequentially select the scanning electrodes,
In synchronization with this, the image to be displayed on the pixel on the selected scan electrode
A drive voltage having a predetermined waveform corresponding to image data is applied to each signal electrode X.
₁, X₂... X_m-1, X _mApplied to the liquid crystal panel 1
Display at 0.

The control circuit 20 drives the scan electrode drive circuit 50 based on the vertical sync signal VSYC and the horizontal sync signal HSYC for displaying an image from an external circuit, and a scan electrode drive circuit control signal and a signal electrode drive. A signal electrode drive circuit control signal for driving the circuit 60 is generated. In this case, the scan electrode drive circuit control signals are S101 signal, S102 signal, SCC signal and DP.
_It consists of the _y signal. Here, the S101 signal and the S102 signal are signals that specify one state of each of the scan electrodes Y ₁ , Y _2, ..., Y _n-1 , Y _n . In this embodiment, both S10
1 signal and S102 signal are both low level (that is, L)
When, the erased state is specified. When the S101 signal is L and the S102 signal is high level (that is, H), the selected state is specified. When the S101 signal is H and the S102 signal is L, the holding state is specified.

Further, the SCC signal has a rising edge.
Data latch L described later._yBoth S101 signals to and
The acquisition timing of the S102 signal is specified. DP_y
The signal is for each scan electrode Y.₁, Y₂... Y_n-1, Y_nOne
It serves to determine the polarity of the select voltage to the two. example
For example, when the scan electrode is in the selected state, D
P _yThe signal switches from L to H. On the other hand, the signal electrode
Drive circuit control signals are RCK signal, SIC signal, STD
Signal and DP_xComposed of signals.

The scan electrode drive circuit 50 is connected to the power supply circuit 30.
n-shaped scan electrode Y₁, Y₂... Y _n-1, Y_nBetween
The power supply circuit 30 is connected to the five levels Vhn,
Generates power supply voltages of Ve, Vwn, Vwp and Vhp (see Fig. 4)
To live. The scan electrode drive circuit 50 uses 3n-bit data.
Latch L_yAnd (n + 1) level shifters S_y0Through S
_ynAnd n analog switch circuits A_y1Through A_ynAnd
It consists of the analog switch SW and data
Touch L_yNumber of bits, level shifter S_y1Through S_ynNumber of
And analog switch circuit A_y1Through A_ynNumber of scan electrodes
Y₁, Y₂... Y_n-1, Y_nIt corresponds to the number of.

The data latch L _y is provided in the control circuit 2
0 to scan electrode drive circuit control signal (S101 signal, S1
02 signal, SCC signal and DP _y signal).
Then, the data latch L _y takes in the S101 signal and the S102 signal in synchronization with the SCC signal, and scan electrodes Y ₁ , Y ₂ ... Y _n-1 , specified by the S101 signal and the S102 signal, Based on the state of Y _n , the power supply voltage from the power supply circuit 30 is used to create and store as data.

At this time, in creating the data in the data latch L _y , the DP _y signal determines the polarity of the voltage applied to the selective scan electrode. The level shifter S _y0 also generates a switching signal for switching the analog switch SW based on the DP _y signal from the control circuit 20. Further, the level shifters S _{y1 to} S _yn decode the corresponding data from the data latch L _y and output switching signals for switching the analog switches of the analog switch circuits A _{y1 to} A _yn , respectively.

The analog switch SW is a level shifter S.
_When the switching signal from _y0 is H, each analog switch 51 is connected to the terminal of the power supply circuit (corresponding to the power supply voltage Vwp). On the other hand, when the switching signal from the level shifter S _y0 is L, the analog switch SW connects each analog switch 51 to the terminal of the power supply circuit (corresponding to the power supply voltage Vwn).

The analog switch 51 of each of the analog switch circuits A _{y1 to} A _yn is turned on / off by a switching signal from each of the level shifters S _{y1 to} S _yn . The remaining analog switches 52, 53, 54 of the analog switch circuits A _{y1 to} A _yn are connected to the output terminals of the power supply circuit 30 (corresponding to the power supply voltages Vhp, Vhn, Ve).

As a result, the voltage output from the scan electrode drive circuit 50 to each scan electrode is switched by turning on / off the analog switch provided for each output. During each period of erasing and holding, the analog switch of each output connected to each electrode to which the erasing voltage V _e , the positive holding voltage V _hp or the negative holding voltage V _hn is turned on is turned on, so that a predetermined value is obtained. The voltage waveform is output.

During the selection period, each output analog switch connected to the electrode to which the write voltage is applied is turned on, and the write voltage to be applied to the electrode to which the write voltage is applied is changed by the polarity control signal DP _y by the analog switch. By switching to the positive write voltage Vwp or the negative write voltage Vwn, the voltage is output in a predetermined waveform. Here, the operation of the scan electrode driving circuit 50 will be described with reference to FIG.

The scan electrode drive circuit 50 is responsive to the power supply voltages from the power supply circuit 30 to scan electrodes Y ₁ , Y _2, ...
An erase voltage, a selection voltage and a holding voltage corresponding to the erased, selected and held states are sequentially output to Y _n-1 and Y _n . Further, since the AC driving is performed, the scan electrode driving circuit 50
Reverses the positive and negative polarities of the selection voltage for each selection period.

Incidentally, the case where the scan electrode driving circuit 50 drives the scan electrode Y ₁ will be described as an example. The scan electrode drive circuit 50 outputs an erase voltage V _{e in} order to erase the display of all pixels on the scan electrodes during the erase time.
Then, the scan electrode driving circuit 50, during the positive selection period,
The negative write voltage V _wn is output once, and then the positive write voltage V _WP is output. In addition, the scan electrode drive circuit 50
Outputs the holding voltage V _hp during the positive holding period and holds this holding voltage V _hp until the next erasing time. As a result, the display content is held until the next erasing time.

After this erasing time, the scan electrode driving circuit 50 then performs AC driving. Therefore, the scan electrode driving circuit 50 becomes a negative selection period having a polarity opposite to that of the previous selection period, once outputs the positive write voltage V _wp , and then outputs the negative write voltage V _wn . The scanning electrode driving circuit 50, at negative holding period, and outputs the held voltage V _hn, holds the holding voltage V _hn until the next erase period.
As a result, the display content is held until the next erasing time.
After that, such an operation is repeated by the scan electrode driving circuit 50.

In this case, since the line-sequential scanning is performed in order from the scan electrode Y _1, the waveform of the output of the scan electrode driving circuit 50 becomes a waveform shifted by the selection period with respect to each scan electrode after the scan electrode Y _2. . At this time, in order to prevent display flicker, the voltage polarity is different for each scan electrode, for example, the scan electrode Y ₁ is positive, the scan electrode Y ₂ is negative, and the scan electrode Y ₃ is positive. .

When each scan electrode is in the selected state,
For example, in the positive selection period, since the DP _y signal switches from L to H as described above, the scan electrode drive circuit 50
The output voltage of V _wn switches from V _wn to V _wp . in this way,
The decoding result of the DP _y signal input to the data latch L _y directly determines the polarity of the selection voltage. Note that, when the period shifts to the holding period, the polarity holds the state of the decoding result of the DP _y signal input in the immediately preceding selection period, and DP _y
It does not depend on the signal.

The scan electrode drive circuit 50, based on each power supply voltage from the power supply circuit 30, as shown in FIG. 4, for each scan electrode Y ₁ , Y ₂ ... Y _n-1 , Y _n . , A predetermined line-sequential scanning waveform drive voltage corresponding to the erased, selected, and held states is sequentially applied. Signal electrode drive circuit 60
Are connected between the power supply circuit 40 and the liquid crystal panel 10, and the power supply circuit 40 generates power supply voltages of _eight levels V _{1 to} V ₈ (see FIG. 6).

The signal electrode drive circuit 60 includes m data latches L _{xf1 to} L _xfm , m data latches L _{xs1 to} L _xsm , m level shifters S _{x1 to} S _xm , and m analog switches. is constituted by a circuit A _x1 to A _xm, these data latches L _xf1 to L _xfm, data latch L _xs1 to L _xsm, level shifter S _x1 to S _xm and the analog switch circuits A _x1 to A _xm, respectively, each It is provided corresponding to the signal electrodes X ₁ , X _2, ... X _m-1 , X _m .

Here, each data latch L _{xf1 to} L _{xfm
Each of the} data latches L _{xs1 to} L _xsm is a 3-bit data latch. Each of the analog switch circuits A _{x1 to} A _xm is composed of eight analog switches. An image data signal DAP signal for displaying an image is input from an external circuit to each of the data latches L _{xf1 to} L _xfm , and a SIC signal and an STD signal are input from the control circuit 20.
In this embodiment, 8-gradation display in which brightness is controlled in 8 steps is adopted. Therefore, the image data signal DAP
The signal is a 3-bit data signal indicating brightness of 8 levels for each pixel.

Therefore, each data latch L _{xf1 to} L _xfm
Creates a data signal based on the image data signal DAP signal as follows. For each of the data latches L _{xf1 to} L _xfm , the 3-bit image data signal DAP is
The signal electrodes X ₁ to X _m are input as serial data corresponding to each, and the SIC signal and the STD signal are input from the control circuit 20.

Here, the image data signal DAP is from the image data signal of the pixel arranged on the scan electrode Y ₁ to the image data signal of the pixel arranged on the scan electrode Y _{n in} synchronization with the scanning of the scan electrode. , Each data latch L _{xf1 to} L
Input to _xfm in order. In FIG. 5, reference numeral D _{1, i} is
7 shows a set of image data signals of pixels arranged on the scan electrode Y ₁ . Further, the symbols D _{1,1 to} D _{1, m} indicate image data signals corresponding to the signal electrodes X _{1 to} X _m therein.

Then, the image data signal DAP is ST
When the D signal is H, it is input as a data signal corresponding to the signal electrode X ₁ , and is taken into the data latch L _xf1 in synchronization with the rising _edge of the SIC signal. After that, the image data signal DAP is taken into these data latches L _{xf2 to} L _xfm as data signals corresponding to the signal electrodes X _{2 to} X _m in synchronization with the rising _edge of the SIC signal.

As a result, each data latch L _{xf1 to} L _xf1
Image data signals corresponding to pixels arranged on one scan electrode are stored in _xfm . Each such data latch L
The operation from _{xf1 to} L _xfm is repeated for each scan electrode. The image data signals DAP stored in the data latches L _{xf1 to} L _xfm in this manner are sequentially transferred to and stored in the data latches L _{xs1 to} L _xsm in synchronization with the rising edges of the RCK signal. In addition, DP _x from the external circuit
The signal is the data latch L _{xs1 to} L _according to the RCK signal.
Input to _xsm .

The level shifters S _{x1 to} S _xm respectively decode the data signals transferred to the data latches L _{xs1 to} L _xsm and _{apply the} decoded data signals to the analog switch circuits A _{x1 to} A _xm as switching signals. Each of the analog switch circuits A _{x1 to} A _xm switches the voltage to be applied to the signal electrodes X _{1 to} X _m from the power supply circuit 40. The switching timing of each analog switch of these analog switch circuits A _{x1 to} A _xm is , Each data latch L _{xs1 to} L
It is determined by the image data signal and DP signal stored in _xsm .

For example, when the DP _x signal is L, the 3-bit image data signal corresponding to the output to each signal electrode is (0, 0, 0), (0, 0, 1) ... (1, 1,
0) and (1, 1, 1), the power supply circuit 40
The analog switches of the respective analog switch circuits A _{x1 to} A _xm connected to the respective output terminals (terminals corresponding to the respective power supply voltages V ₈ , V ₇ ... V ₁ ) turn on.

DP_xOutput to each signal electrode when the signal is H
The 3-bit image data signal corresponding to the force is (0, 0,
0), (0, 0, 1) ... (1, 1, 0), (1,
1, 1), whereas each output terminal of the power supply circuit 40
(Each power supply voltage V₁... V₇, V ₈To the corresponding terminal)
Each connected analog switch circuit A_x1Through A_xm
The analog switch of turns on.

As described above, the scan electrode drive circuit 50
SCC signal and DP _y signal to the signal electrode driving circuit 60
6 by inputting the image data signal of the pixel arranged on the scan electrode in the selection period to the signal electrode driving circuit 60 one selection period before in synchronization with the RCK signal and the DP _x signal to The liquid crystal drive voltage waveform shown is realized. As described above, by utilizing the fact that the scan electrodes Y _{1 to} Y _n are line-sequentially scanned, in the scan electrode drive circuit 50,
An analog switch SW is connected between both output terminals (corresponding to both power supply voltages V _wp and V _wn ) of the power supply circuit 30 and each analog switch 51, and the switching operation of this analog switch SW is performed by the level shifter S _y0. did.

As a result, a single analog switch SW
Each analog switch circuit A _y1Through A_ynThe analogo
Dual power supply voltage V to switch 51_wp, V_wnSelective grant of
Can be controlled. Therefore, conventionally, each analog switch circuit
A_y1Through A_ynAt the respective power supply voltage V_wp, V
_wn2 analog switches are needed for the output of
What used to be each analog switch circuit A_y1Through A_ynTo
One analog switch 51 and each analog switch
Log switch circuit A_y1Through A_ynCommon switching switch
Just by adding one analog switch SW,
The function similar to that of the conventional scan electrode driving circuit can be exhibited. This
As a result, the analog switch in the scan electrode drive circuit 50 is
It is possible to secure a reduction in the number of switches and
Cost reduction can be realized.

Further, each analog switch circuit A _{y1 to} A _y
The total number of analog switches required in _yn is n-2 reductions as compared with the conventional configuration, but the analog switches supplying the write voltage have a higher voltage than the erase voltage and the holding voltage. In order to switch at high speed, a transistor with low on-resistance is required as a constituent element of an analog switch. Therefore, since the transistor size becomes large, the effect of reducing the circuit space exceeds the effect of reducing the total number of analog switches. For example, when the scan electrode driving circuit is formed into a monolithic IC, the chip size can be reduced by about 30% as compared with the conventional one.

In this embodiment, an example in which the invention is applied to the liquid crystal panel driving device for the liquid crystal panel 10 in which the antiferroelectric liquid crystal is sealed has been described, but the invention is not limited to this. The present invention may be applied to a liquid crystal panel driving device for a liquid crystal panel in which liquid crystals such as smectic liquid crystals and nematic liquid crystals are sealed. Also,
The present invention is not limited to a liquid crystal panel for a liquid crystal display device, but may be applied to a liquid crystal panel driving device for a liquid crystal panel for a liquid crystal switch, for example.

Further, in carrying out the present invention, the drive waveform of each scan electrode of the liquid crystal panel 10 is not limited to that of the above embodiment, and the scan electrode drive circuit outputs the drive voltage by the line sequential drive system. The drive voltage may have any waveform as long as it has a waveform. Along with this, the analog switch SW has only to switch between two drive voltages output at different times, and is not limited to the two voltages described in the above embodiment. Further, the number of analog switches SW may be plural.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a detailed circuit diagram of the scan electrode driving circuit of FIG.

FIG. 3 is a detailed circuit diagram of the signal electrode drive circuit of FIG.

FIG. 4 is a timing chart showing an operation of the scan electrode driving circuit of FIG.

5 is a timing chart showing an operation of the signal electrode drive circuit of FIG.

6 is a timing chart showing output waveforms of the liquid crystal panel driving device of FIG.

FIG. 7 is a timing chart showing an operation of a conventional scan electrode driving circuit.

[Explanation of symbols]

10 ... Liquid crystal panel, 20 ... Control circuit,
30, 40 ... Power supply circuit, 50 ... Scan electrode drive circuit, 60 ... Signal electrode drive circuit, _{Ay1 to Ayn} ...
Analog switch circuit, 51 to 54 ... Analog switch, L _y ... Data latch, SW ... Analog switch, S _{y0 to Syn} ... Level shifter.

Claims (2)

[Claims] 1. An n-type scanning electrode is applied to a liquid crystal panel that constitutes a matrix pixel by n-type scanning electrodes and m-number of signal electrodes, and the n-number of scanning electrodes are sequentially selected based on a line-sequential driving voltage having a plurality of levels. And a scanning electrode driving unit that is driven by the scanning electrode driving unit, and in synchronization with the selection of the scanning electrode by the scanning electrode driving unit, based on a signal voltage that specifies an image data signal corresponding to a pixel on the selected scanning electrode In the liquid crystal panel driving device, the scanning electrode driving means is provided corresponding to each of the n-shaped scanning electrodes, and the line-sequential driving voltage is switched to change its level. n switch means for sequentially applying to the n-shaped scan electrodes are provided, and at least two of the plurality of levels of the line-sequential drive voltage are switched to select the scan electrodes. The liquid crystal panel driving apparatus characterized by switching means for performing synchronization is provided in common to the respective switching means. 2. Each of the switch means is composed of an analog switch whose number is smaller than the number of levels of the line-sequential drive voltage, and the switching means includes at least two of the plurality of levels of the line-sequential drive voltage. 2. The liquid crystal panel drive device according to claim 1, wherein the liquid crystal panel drive device is configured by a single analog switch that performs switching.