JP2003233358A - Liquid crystal driver and liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce noise when driving a liquid crystal panel. <P>SOLUTION: An amplifier circuit (85) is comprised of a multi-output amplifier circuit (85-1) having many output terminals, and a delay circuit (85-2) for distributing timing for driving a plurality of source lines. The multi-output amplifier circuit is constituted of a plurality of amplifier blocks. The delay circuit (85-2) shifts a plurality of amplifier blocks in the operation timing. Thus, the concentration of the currents for driving the liquid crystal panel can be avoided and large current generation is avoided, and consequently, noise is reduce when driving the liquid crystal panel. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technique for a liquid crystal panel, for example, a technique effectively applied to a source driver of a TFT type color liquid crystal panel.

[0002]

2. Description of the Related Art A liquid crystal panel includes a plurality of source lines and gate lines arranged so as to intersect the source lines, and liquid crystal cells are arranged at intersections of the source lines and the gate lines. A driving device for driving such a liquid crystal panel is provided with a source driver for driving a source line and a gate driver for driving a gate line. The source driver outputs drive information on a line-by-line basis.
At this time, the gate driver drives the plurality of source lines in a time division manner.

An example of the document describing the liquid crystal display is "Electronic Communication Handbook (page 472)" issued by Ohm Co., Ltd. in 1983.

[0004]

A multi-output liquid crystal driver having a plurality of output terminals is used as a source driver for driving a large-screen TFT liquid crystal panel. The multi-output liquid crystal driver outputs a drive signal for the liquid crystal panel in synchronization with the input line output signal. At this time, since the drive signals output from all the output terminals in the conventional multi-output liquid crystal driver are output at the same timing, the current for driving the liquid crystal panel is concentrated and a large current instantaneously flows. The inventors of the present application have found that this large current causes spike-like noise to be generated in the power supply line and the signal line.

In general, as electronic equipments and radio wave environments become more complicated, EMI (electromagnetic interfering) not only in the equipments but also in the constructed system.
(fence): Electromagnetic disturbance) should be taken into consideration. Particularly in the liquid crystal display device, since the signal output timing from the multi-output liquid crystal driver is synchronized with the data transfer clock signal (32.5 MHz),
When spike-like noise occurs in the power supply line or the signal line due to a large amount of current instantaneously flowing to drive the liquid crystal panel, the harmonics of the data transfer clock signal (7 Next, 9th)
EMI needs to be considered. In order to reduce this EMI as well, it is necessary to reduce spike-like noise generated due to the concentration of the current for driving the liquid crystal panel.

An object of the present invention is to reduce noise when driving a liquid crystal panel.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a timing control circuit for distributing the timing of driving the plurality of source lines is provided. Further, a plurality of multi-output amplifier circuits for driving a plurality of source lines, respectively, and a timing control circuit for dispersing the signal output timing from the multi-output amplifier circuits are provided. Here, when the signal output timing is determined based on the line output signal, the timing control circuit may be formed by a delay circuit for delaying the line output signal.

According to the above means, the timing control circuit disperses the timing for driving the plurality of source lines. Thereby, concentration of current for driving the liquid crystal panel is avoided, and generation of large current is avoided. This achieves noise reduction when driving the liquid crystal panel.

Further, a plurality of multi-output amplifier circuits for respectively driving a plurality of source lines, an output terminal group capable of externally outputting output signals from the plurality of multi-output amplifier circuits, and the output terminal group. Of the plurality of output terminals, the signal output timing from the multi-output amplifier circuit is the same as that of the multi-output amplifier circuit corresponding to the output terminals located at both ends. And a timing control circuit for distributing from the center of the group to both sides.

According to the above means, in the timing control circuit, the signal output timings from the multi-output amplifier circuits corresponding to the output terminals located at both ends of the plurality of output terminals forming the output terminal group are equal to each other. Under the above condition, the signal output timing from the multi-output amplifier circuit is dispersed from the center of the output terminal group to both sides. At this time, since the signal output timings from the multi-output amplifier circuits corresponding to the output terminals located at both ends of the plurality of output terminals forming the output terminal group become equal to each other, such a liquid crystal panel is driven when the liquid crystal panel is driven. When a plurality of drivers are used, it is possible to prevent streaks from occurring due to driving timing between liquid crystal drivers adjacent to each other.
The signals from the multi-output amplifier circuit are provided under the condition that the signal output timings from the multi-output amplifier circuits corresponding to the output terminals located at both ends of the plurality of output terminals forming the output terminal group are equal to each other. The output timing may be dispersed from both sides of the output terminal group toward the center.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows an example of the structure of a liquid crystal display device according to the present invention.

The liquid crystal display device 36 is not particularly limited, but the color liquid crystal panel 12, a plurality of gate drivers 10-1 to 10-3 for driving the gate lines of the color liquid crystal panel 12, and the color liquid crystal panel described above. 12
Source drivers 11 for driving the data lines of
-1 to 11-n, a controller 14 that controls the operation of the entire liquid crystal display device 36, and a liquid crystal drive power supply circuit 13 that supplies power for driving the color liquid crystal panel 12.

Although not particularly limited, the color liquid crystal panel 12 is a TFT type, and its size is 1600 × 120.
An n-channel MO having a number of 0 dots, a plurality of gate lines, a plurality of data lines arranged so as to intersect the gate lines, and an n-channel MO arranged at the intersections of the gate lines and the data lines.
It includes an S transistor and a liquid crystal element. For example, as shown in FIG. 4, the gate electrodes of the plurality of n-channel type MOS transistors 221 have corresponding gate lines g1.
To g4, the drain electrode of the transistor 221 is coupled to the corresponding data lines d1 to d3, and the liquid crystal element 222 is coupled between the source electrode of the transistor 221 and the ground GND. To enable color display, the three adjacent data lines d1, d2, d3 are
It supports RGB (red, green, blue),
One pixel is formed by these three elements corresponding to RGB. According to the configuration example shown in FIG. 4, the gate driver 10 selectively drives the gate lines g1 to g4 to a high level, and the source driver 11-1 drives the data lines d1, d2, d3 at a voltage level corresponding to the concentration. Driving the corresponding n-channel type MOS transistor 221 turns on the corresponding liquid crystal element 222.
Is charged up. After that, the output signal of the gate driver 10-1 is set to low level, the n-channel MOS transistor 221 is turned off, and the voltage of the liquid crystal element 222 is held.

Next, the source drivers 11-1 to 11-n
Will be described in detail. In addition, the plurality of source drivers 1
1-1 to 11-n have the same configuration. Therefore, in the following description, only the source driver 11-1 will be described in detail.

FIG. 5 shows a configuration example of the source driver.

As shown in FIG. 5, the source driver 11
-1 is a clock control circuit 80, latch circuits 92, 9
3, decoder 84, amplifier circuit 85, data inversion circuit 8
6 and a gradation voltage generating circuit 87, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The data output horizontal clock signal CL1 and the data transfer clock signal CL2 from the controller 14 are input to the clock control circuit 80. The enable signals EIO0 to 2R * (* indicates low active or signal inversion) and EIO0 to 2L * are used as the enable signals of the source driver. Data acquisition is performed. M is an alternating signal.
In order to prevent the liquid crystal from being damaged, the alternating drive of the liquid crystal controls the alternating drive of the liquid crystal. The alternating signal M is taken in at the timing of the rising edge of the data output horizontal clock signal CL1, and depending on the polarity of the alternating signal M, the positive polarity side (V0 to V8) and the negative polarity side (V9 to V17) side. Output voltage is selectively generated. Although not particularly limited,
When the AC signal M has a logical value of "0", the odd output terminal (Y
1, Y3, ..., Yn-1) outputs the liquid crystal applied voltage of positive polarity, and the even output terminals (Y2, Y4, ..., Yn) output the liquid crystal applied voltage of negative polarity. When the alternating signal M has a logical value "1", odd output terminals (Y1, Y
, ..., Yn-1) outputs the liquid crystal applied voltage of negative polarity, and the even output terminals (Y2, Y4, ..., Yn) output the liquid crystal applied voltage of positive polarity. SHL is a signal instructing the shift direction of the display data, and the shift direction of the display data written in the first latch circuit is controlled via the latch address selector 81.

Data D transmitted from the controller 14
57-D50, D47-D40, D37-D30, D2
7 to D20, D17 to D10, D07 to D00 are transmitted to the first latch circuit 92 via the data inverting circuit 86. The inversion circuit 86 inverts the logic of the data according to the data inversion signal POL transmitted from the controller 14.

The first latch circuit 92 is a data inverting circuit 8
The data from 6 is held under the control of the latch address selector 81. A second latch circuit 93 capable of holding the output data of the first latch circuit 92 is provided at the subsequent stage of the first latch circuit 92. First latch circuit 92, second
The latch circuit 93 includes eight planes of data latches, each of which corresponds to Yn data lines. Eight planes are provided because 8-bit digital data is required for each terminal in order to output a voltage of 256 gradations from each source line drive terminal.

A decoder 84 for decoding the output data of the latch circuit is provided at the subsequent stage of the latch circuit 93. The output signal of the decoder 84 is buffered by the amplifier circuit 85 in the subsequent stage to drive the source line, and then output to the outside.

The voltages of various levels required for decoding by the decoder 84 are generated by resistance-dividing the input voltages V0 to V17 of various levels in the gradation voltage generation circuit 87. For example, as shown in FIG. 6, by taking in input voltages V0 to V17 of various levels and combining the representatively shown ladder resistances R1 to R6 and R9 to R14, 256 gradations of positive polarity and 256 gradations of negative polarity are obtained. We obtain multiple levels of voltage to indicate

12 to 14 show a color liquid crystal panel 1.
2 drive example is shown.

"+" And "-" indicate that the dot logic is inverted.

FIG. 12 shows a state of dot inversion driving.

As described above, the source drivers 11-1 to 11-1
1-n enables alternating current driving of the liquid crystal by switching the logic of the alternating signal M. For example, by switching the alternating signal M for each data output horizontal clock signal CL1, it is possible to perform dot inversion driving in which gradation voltages having different polarities are applied to adjacent dots.

FIG. 13 shows a state of n-line inversion driving.

When the logic of the alternating signal M is switched every n times of the data output horizontal clock signal CL1, as shown in FIG. 13, n-line inversion driving is performed every horizontal dot and every vertical n line. .

FIG. 14 shows the state of frame inversion driving.

By switching the logic of the alternating signal M for each frame, frame inversion drive can be performed for each dot in the horizontal direction and for each frame in the vertical direction as shown in FIG.

FIG. 15 shows the relationship between the data input at the time of frame inversion in dot-by-dot inversion and the alternating signal M and output level.

In this driver, it is necessary to hold the level of the alternating signal M during the high level period of the data output horizontal clock signal CL1. The high voltage side and the low voltage side of the grayscale voltage generation circuit 87 are operated according to the level of the alternating signal M at the rising edge of the data output horizontal clock signal CL1 to output the respective grayscale voltages. During the high level period of the data output horizontal clock signal CL1, the output signal is in a high impedance state in order to stably operate the output of the buffer amplifier.

FIG. 1 shows a configuration example of the amplifier circuit 85.

The amplifier circuit 85 is not particularly limited,
A multi-output amplifier circuit 85-1 having a large number of output terminals (Y1 to Yn) and a delay circuit 85-2 for delaying the line output signal are included.

The multi-output amplifier circuit 85-1 includes a first amplifier block 61 for outputting signals Y1 to Y (n / 2) for driving the color liquid crystal panel 12 in synchronization with the line output signal, and a delay circuit. A signal Y (n / 2) + for driving the color liquid crystal panel 12 in synchronization with the output signal of 85-2.
A second amplifier block that outputs 1 to Yn. The delay circuit 85-2 gives a predetermined delay time to the line output signal. As a result, the output signals Y (n / 2) +1 to Yn of the second amplifier block 62 are output signals Y1 to Y (n / 2) of the amplifier block 61 as shown in FIG.
More than a predetermined amount of time later, it stands up. In this way, the signal output timing of the multi-output amplifier circuit 85-1 is the first
The shift between the amplifier block 61 and the second amplifier block 62 makes it possible to reduce the concentration of current when driving the color liquid crystal panel 12.

Here, the delay circuit 85-2 is an example of the timing control circuit in the present invention.

According to the above example, the following operational effects can be obtained.

By deviating the signal output timing of the multi-output amplifier circuit 85-1 between the first amplifier block 61 and the second amplifier block 62, it is possible to reduce the concentration of current when driving the color liquid crystal panel 12. it can. In other words, by dispersing the timings at which the plurality of source lines are driven, it is possible to reduce the concentration of current when driving the color liquid crystal panel 12. Thereby,
It is possible to prevent spike-like noise from being generated in the power supply line and the signal line due to the current concentration when driving the color liquid crystal panel 12.

7 to 11 show another configuration example of the amplifier circuit 85.

In the amplifier circuit 85 shown in FIG. 7, the delay circuit 85-2 is composed of a flip-flop circuit (F / F) 70. The line output signal is transmitted to the data terminal D of the flip-flop circuit 70. The data transfer clock signal CL2 is transmitted to the clock terminal CP of the flip-flop circuit 70. The line output signal is output from the output terminal Q in synchronism with the data transfer clock signal CL2 to be delayed, and then the second amplifier block 62
Transmitted to. Even if the delay circuit 85-2 is configured by the flip-flop circuit 70 as described above, the line output signal can be delayed and then supplied to the second amplifier block 62. Therefore, the same effect as the above example can be obtained. Can be obtained.

In the amplifier circuit 85 shown in FIG. 8, the multi-output amplifier circuit 85-1 includes m (m is a positive integer) amplifier blocks 63-1, 63-2, 63-3, ..., 63-.
The delay circuit 85-2 includes m−1 flip-flop circuits (F / F) 70-1, 70-2, 70-3,
..., 70-m-1 is included. Flip-flop circuit 70-
, 70-2, 70-3, ..., 70-m-1 are connected in series, and the line output signal is the data transfer clock signal C.
The shift is performed in synchronization with L2. Flip-flop circuits 70-1, 70-2, 70-3, ..., 70
The line output signals delayed by −m−1 correspond to the corresponding amplifier blocks 63-2, 63-3, ..., 6
By being transmitted to 3-m, the output timings of the m amplifier blocks 63-1, 63-2, 63-3, ..., 63-m are dispersed by m. Even in this case, it is possible to obtain the same effects as the above example.

In the amplifier circuit 85 shown in FIG. 9, the multi-output amplifier circuit 85-1 is composed of m amplifier blocks 63-.
1-63-m, the delay circuit 85-2 is (m / 2)
-1 flip-flop circuits 70-1 to 70- (m /
2) -1 is included. Flip-flop circuits Flip-flop circuits 70-1 to 70- (m / 2) -1 are connected in series, and the line output signal is the data transfer clock signal CL2.
It is designed to be shifted in synchronism with. The line output signal is sent to the amplifier block 63- (m /
2) and 63- (m / 2) +1 directly. The output signal of the flip-flop circuit 70- (m / 2) -2 is supplied to the amplifier blocks 63-2 and 63- (m-1). The output signal of the flip-flop circuit 70- (m / 2) -1 is supplied to the amplifier blocks 63-1 and 63-m. As a result, m amplifier blocks 63-1 to 6-3 are provided.
Since the signal output timing from 3-m can be dispersed from the center to both sides of the output terminal group of the multi-output amplifier circuit 85-1, the concentration of current when driving the color liquid crystal panel 12 is relaxed. be able to. Thereby,
It is possible to prevent spike-like noise from being generated in the power supply line and the signal line due to the current concentration when driving the color liquid crystal panel 12. Then, by performing such distribution, the signal output timings from the amplifier blocks 63-1 and 63-m located at both ends of the multi-output amplifier circuit 85-1 become equal to each other. For this reason,
As shown in FIG. 3, the source drivers 11-1 to 11-
When n are arranged, the signal output timings from the adjacent amplifier blocks are the same between the source drivers adjacent to each other. Here, since the resistances of the ladder resistors R1 to R6 and R9 to R14 (see FIG. 6) of the gradation voltage generating circuit 87 are different in different chips,
When the source drivers 11-1 to 11-n are arranged, a streak is likely to occur on a display image due to a difference in signal output timing between adjacent source drivers. Therefore, when the signal output timings from the adjacent amplifier blocks greatly differ between the adjacent source drivers, the signal between the adjacent source drivers is generated in the streaks caused by the errors of the ladder resistors R1 to R6 and R9 to R14. Streaks due to the difference in output timing will be superimposed, and streaks cannot be ignored. On the other hand, when the configuration shown in FIG. 9 is adopted, the signal output timings from the adjacent amplifier blocks are made equal to each other between the source drivers adjacent to each other, so that at least the signal output between the source drivers adjacent to each other is performed. Streaks due to the difference in timing do not occur. Therefore, it is possible to reduce the concentration of current when driving the color liquid crystal panel 12 without increasing streaks.

In the amplifier circuit 85 shown in FIG. 10, the multi-output amplifier circuit 85-1 has m amplifier blocks 63.
-1 to 63-m, the delay circuit 85-2 includes (m /
2) -1 flip-flop circuits 70-1 to 70-
Including (m / 2) -1. Flip-flop circuits Flip-flop circuits 70-1 to 70- (m / 2) -1 are connected in series, and the line output signal is shifted in synchronization with the data transfer clock signal CL2. The line output signal is sent to the amplifier blocks 63-
1 and 63-m are fed directly. The output signal of the flip-flop circuit 70-1 is supplied to the amplifier blocks 63-2 and 63- (m-1). The output signal of the flip-flop circuit 70- (m / 2) -1 is the amplifier block 63.
-(M / 2) and 63- (m / 2) +1.
As a result, m amplifier blocks 63-1 to 63-m
Signal output timing from the multi-output amplifier circuit 85-
Since it is possible to disperse the output terminal group 1 from both sides toward the center, it is possible to reduce the concentration of current when driving the color liquid crystal panel 12. As a result, it is possible to suppress the generation of spike-like noise on the power supply line and the signal line due to the current concentration when driving the color liquid crystal panel 12. Further, by performing such distribution, the signal output timings from the amplifier blocks 63-1 and 63-m located at both ends of the multi-output amplifier circuit 85-1 become equal to each other. Therefore, when the source drivers 11-1 to 11-n are arranged as shown in FIG. 3, the signal output timings from the amplifier blocks adjacent to each other between the adjacent source drivers are equal to each other. Therefore, the same operational effect as when the configuration shown in FIG. 9 is adopted.

In the amplifier circuit 85 shown in FIG. 11, the multi-output amplifier circuit 85-1 has m amplifier blocks 63.
Delay circuit 85-2 includes inverter groups 90-1, 90-2, 90-3, ..., 90-.
m-1. The line output signal is directly transmitted to the amplifier block 63-1. Amplifier block 63-2
To 63-m, corresponding inverter groups 90-1, 90
Output signals of -2, 90-3, ..., 90-m-1 are transmitted. Even if the delay circuit 85-2 is configured by the inverter group as described above, the line output signal can be delayed and then supplied to the second amplifier block 62, so that the timing for driving the plurality of source lines is dispersed. As a result, it is possible to reduce the concentration of current when driving the color liquid crystal panel 12, and thus the color liquid crystal panel 1
It is possible to suppress the generation of spike-like noise in the power supply line and the signal line due to the current concentration when driving 2.

Although the invention made by the present inventor has been specifically described above, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

In the above description, the invention which was mainly made by the present inventor is the field of application which is the background of the invention.
Although it has been described that the invention is applied to the source driver of the color LCD panel, the invention is not limited thereto and can be widely applied to drivers of various liquid crystal panels.

The present invention can be applied under the condition that at least the liquid crystal panel is driven.

[0049]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the timing control circuit disperses the timing for driving the plurality of source lines, the concentration of the current for driving the liquid crystal panel can be avoided and the generation of a large current can be avoided. It is possible to reduce noise when driving the liquid crystal panel.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of a main part in a source driver which is an example of a liquid crystal driver according to the present invention.

FIG. 2 is an operation timing chart of a main part of the source driver.

FIG. 3 is a block diagram of a configuration example of a liquid crystal display device including the source driver.

FIG. 4 is a circuit diagram of a configuration example of a color liquid crystal panel in the liquid crystal display device.

FIG. 5 is a block diagram of a configuration example of the source driver.

FIG. 6 is an explanatory diagram of an output voltage of a grayscale voltage generation circuit included in the source driver.

FIG. 7 is a block diagram of another configuration example of a main part of the source driver.

FIG. 8 is a block diagram of another configuration example of a main part of the source driver.

FIG. 9 is a block diagram of another configuration example of a main part of the source driver.

FIG. 10 is a block diagram of another configuration example of a main part of the source driver.

FIG. 11 is a block diagram of another configuration example of a main part of the source driver.

FIG. 12 is an explanatory diagram of an example of dot inversion driving of the color liquid crystal panel.

FIG. 13 is an explanatory diagram of an example of n-line inversion driving of the color liquid crystal panel.

FIG. 14 is an explanatory diagram of a frame inversion driving example of the color liquid crystal panel.

FIG. 15 is a diagram for explaining the relationship between data input, alternating signal, and output level at the time of dot inversion of the color liquid crystal panel.

FIG. 16 is a block diagram of a configuration example of a computer system that is an application example of the liquid crystal display device.

[Explanation of symbols]

10 Gate driver 11-1 to 11-n Source driver 12 color LCD panel 13 LCD drive power supply circuit 61, 62, 63-1 to 63-m amplifier block 70,70-1 to 70-m-1 flip-flop circuit 85 amplifier circuit 85-1 Multi-output amplifier circuit 85-2 Delay circuit

Continued front page    F term (reference) 2H093 NC16 ND10 ND40 ND43                 5C006 AA21 AC21 AF43 AF71 BB16                       BC12 BC24 BF06 BF07 BF25                       FA16 FA32                 5C080 AA10 BB05 CC03 DD12 FF11                       JJ02 JJ04

Claims (5)

[Claims] 1. A liquid crystal driver for driving a liquid crystal panel including a plurality of gate lines and a plurality of source lines arranged so as to intersect the plurality of gate lines, wherein timings for driving the plurality of source lines are dispersed. A liquid crystal driver including a timing control circuit for 2. A liquid crystal driver for driving a liquid crystal panel including a plurality of gate lines and a plurality of source lines arranged so as to intersect therewith, each of which is for driving a plurality of source lines. A liquid crystal driver, comprising: a plurality of multi-output amplifier circuits; and a timing control circuit for dispersing signal output timings from the multi-output amplifier circuits. 3. A liquid crystal driver for driving a liquid crystal panel including a plurality of gate lines and a plurality of source lines arranged so as to cross the plurality of gate lines, each driving a plurality of source lines. Corresponding to a plurality of multi-output amplifier circuits, an output terminal group capable of outputting output signals from the plurality of multi-output amplifier circuits to the outside, and output terminals located at both ends of the plurality of output terminals forming the output terminal group A timing control circuit for dispersing the signal output timing from the multi-output amplifier circuit from the center of the output terminal group to both sides, provided that the signal output timings from the multi-output amplifier circuit are equal to each other, A liquid crystal driver including: 4. A liquid crystal driver for driving a liquid crystal panel including a plurality of gate lines and a plurality of source lines arranged so as to cross the plurality of gate lines, each driving a plurality of source lines. Corresponding to a plurality of multi-output amplifier circuits, an output terminal group capable of outputting output signals from the plurality of multi-output amplifier circuits to the outside, and output terminals located at both ends of the plurality of output terminals forming the output terminal group A timing control circuit for dispersing the signal output timing from the multi-output amplifier circuit from both sides of the output terminal group toward the center, provided that the signal output timings from the multi-output amplifier circuit are equal to each other, A liquid crystal driver including: 5. A liquid crystal display device comprising the liquid crystal driver according to claim 1 and a liquid crystal panel driven by the liquid crystal driver.