KR100214836B1 - Device for showing a still-picture of pip-tv - Google Patents

Abstract

Disclosed is a PDP-TV image freezing apparatus capable of temporarily stopping an operation of a video signal displayed on a screen in a PDP-TV to provide a viewer with a still image. Each data corresponding to the RGB signal is applied to the PISO unit in parallel from the memory unit in which the image data is stored, and the PISO unit alternately converts the data applied in parallel to the first buffer unit and the second buffer unit. Will be authorized. The data applied to the first buffer unit is temporarily stored and then applied to the first frame memory unit, and the data applied to the second buffer unit is temporarily stored and then applied to the second frame buffer unit. The second frame memory unit performs a read and write operation according to a signal applied from the address selector to alternately apply data to the data selector. The data selector alternately selects data from the first frame memory unit and the second frame memory unit and applies the data to the PDP driver to display an image signal. At this time, when the clock-still signal is applied to the address selector from the microcomputer, the address selector controls the operations of the first frame memory unit and the second frame memory unit to repeatedly execute the current operation. Since only a signal is applied, a still image is displayed on the screen.

Description

PDP-TV Still Image Display

The present invention relates to a PDP-TV, and more particularly, to a still image display device of a PDP-TV capable of providing a viewer with a still image by temporarily stopping an operation of a video signal displayed on a screen in the PDP-TV. It is about.

In general, a plasma display (hereinafter referred to as a PDP) is a display device using light emission according to a discharge phenomenon in a mixed gas, and is suitable for a display device of a large screen, and since it can be colorized, its use as a flat wall TV has been studied. . When the PDP is classified by the discharge type, the AC type is classified into an AC type PDP (indirect discharge type) and a DC type PDP (direct discharge type) according to the type of driving voltage applied to the discharge cell. Although driven by pulse voltage, DC type PDP is driven by DC voltage. Therefore, the PDP has a different structure. In the AC type PDP, the electrode is covered by the dielectric of the glass, whereas in the DC type PDP, the electrode is exposed as it is and a discharge current flows while the discharge voltage is applied. The AC type PDP has a memory function inside the cell, but the DC type PDP has a merit such that gray scale is added to facilitate image display. In addition, the display format includes a memory type in which the panel stores display information, and a refresh type in which the panel has a memory of display information outside the panel and reads it out and repeatedly displays it on the panel. The panel has a lattice-shaped electrode according to the display shape of the panel, and the intersection of each electrode constitutes a pixel, and it is used for a dot matrix type for displaying characters and figures with a relatively high degree of freedom and a smaller degree of freedom according to the relationship between the points. There is a segment type.

FIG. 1A is a diagram schematically illustrating an electrode arrangement structure of a general PDP-TV.

FIG. 1B is a diagram illustrating data processing in a driving unit of a general PDP-TV.

Referring to FIG. 1A, a general electrode array has a structure in which outputs of a first driver (not shown) and a second driver (not shown) are alternately supplied one by one. The order of data supplied from the first driver to the electrodes is R1, B1, G2, R3, B3, G4, R5, B5, G6,... The order of data supplied from the second driver to the electrode is G1, R2, B2, G3, R4, B4, G5, R6, B6,... It is.

Referring to FIG. 1B, data of the RGB signal output from the A / D converter 10 is classified into two types in the switching unit 20 and again based on the order of the first driver (not shown). ) Includes R1, B1, G2, R3, B3, G4, R5, B5, G6,... In order, the second driving unit (not shown) includes G1, R2, B2, G3, R4, B4, G5, R6, B6,... Rearrange them in order.

SUMMARY OF THE INVENTION An object of the present invention is to provide a still picture display apparatus of a PDP-TV capable of providing a still image to a viewer by stopping an operation of a video signal displayed on a screen in a PDP-TV in a simple manner.

FIG. 1A is a diagram schematically illustrating an electrode arrangement structure of a general PDP-TV.

FIG. 1B is a diagram illustrating data processing in a driving unit of a general PDP-TV.

2 is a block diagram showing a still image display device of the PDP-TV according to the present invention.

3 is a diagram illustrating a pulse waveform of an operation signal generated in FIG. 2.

* Explanation of symbols for the main parts of the drawings

30: PISO unit 32: first buffer unit

34: second buffer unit 36: first frame memory unit

38: second frame memory unit 40: data selection unit

50: PDP driver 60: lead address signal generator

70: write address signal generator 80: address selector

90: micom 95: inverting terminal

The present invention for achieving the above object, the first and second buffer unit for receiving the image input data complementary to each other according to the input level of the data selection signal; A first frame memory unit for reading and writing input image data from the first buffer unit in units of frames; A second frame memory unit reading and writing the input image data from the second buffer unit in units of frames complementary to the first frame memory unit; A PDP driver for displaying image data read and input from the first and second frame memory units on a PDP panel; And a still picture control means for controlling one of the first and second frame memory units to continue only the write operation and the other to continue the read operation in accordance with a still picture selection signal from the outside. Provide the device.

According to the present invention, each data corresponding to the RGB signal is applied to the PISO unit in parallel from the memory unit in which the image signal data is stored, and the PISO unit converts the data applied in parallel to the first buffer unit and the first buffer unit. 2 It is applied alternately to the buffer part. The data applied to the first buffer unit is temporarily stored and then applied to the first frame memory unit, and the data applied to the second buffer unit is temporarily stored and then applied to the second frame buffer unit. The second frame memory unit performs a read and write operation according to a signal applied from the address selector to alternately apply data to the data selector. The data selector alternately selects data from the first frame memory unit and the second frame memory unit and applies the data to the PDP driver to display an image signal. At this time, when the clock-still signal is applied to the address selector from the microcomputer, the address selector controls the operations of the first frame memory unit and the second frame memory unit to repeatedly execute the current operation. Since only a signal is applied, a still image is displayed on the screen.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

2 is a block diagram showing a still image display device of the PDP-TV according to the present invention.

3 is a diagram illustrating a pulse waveform of an operation signal generated in FIG. 2.

Referring to FIG. 2, a still image display apparatus of a PDP-TV will be described below.

First, data corresponding to an RGB signal is input in parallel from a memory unit (not shown) in which image signal data is stored in the PISO unit 30, and the PISO unit 30 converts the data input in parallel into a series. Will be printed. The first buffer section 32 and the second buffer section 34 are connected to the PISO section 30, and the data from the PISO section 30 is connected to the first buffer section 32 and the second buffer section 34. (data) is applied. In addition, a data select signal is applied to the first buffer unit 32 and the second buffer unit 34. The first buffer unit 32 and the second buffer unit 34 are configured as a 3-state buffer, and an inverting terminal is connected to the second buffer unit 34 to which a data selection signal is applied from the PISO unit 30. The data selection signals are alternately applied to the first buffer section 32 and the second buffer section 34. The first frame memory unit 36 is connected to the first buffer unit 32, and the second frame memory unit 38 is connected to the second buffer unit 34, respectively.

The clock signal and the valid data signal are applied to the write address generator 70, and the clock signal and the clock 480 are applied to the read address generator 60. An address selector 80 is connected to the write address signal generator 70 and the read address signal generator 60, and the address selector 80 transmits an address select signal according to a write signal or a read signal in a first frame memory. The unit 36 is applied to the second frame memory unit 38. The microcomputer 90 is connected to the address selector 80, and the microcomputer 90 normally controls the operation of the address selector 80 and immediately receives a clock signal when a still signal is input from the outside. Is applied to the address selector 80 so that the address selector 80 executes a still operation. A data selector 40 is connected to the first frame memory unit 36 and the second frame memory unit 38, and the data selector 40 includes a first frame memory unit 36 and a second frame memory. The data applied from the unit 38 is selected and output to the PDP driver 50. The data selector 40 executes a still operation when a still pulse is applied from the address selector 80. Done.

According to the present invention, the respective data corresponding to the R signal, the G signal, and the B signal, which are video signals, are applied to the PISO unit 30 in parallel from the memory unit in which the image signal data is stored, and the PISO unit 30 Is converted in series to each data of the R signal, the G signal, and the B signal applied in parallel and alternately applied to the first buffer section 32 and the second buffer section 34 according to the data selection signal. That is, since the data selection signal applied to the second buffer unit 34 is applied through the inverting terminal 95, an operation opposite to the data selection signal applied to the first buffer unit 32 is executed. Accordingly, the data output from the PISO unit 30 is alternately applied to the first buffer unit 32 and the second buffer unit 34.

The data applied to the first buffer unit 32 is temporarily stored and then applied to the first frame memory unit 36, and the data applied to the second buffer unit 34 is temporarily stored and then the second frame memory unit 38. Is applied). In this case, data is alternately applied to the first frame memory unit 36 and the second frame memory unit 38 from the first buffer unit 32 and the second buffer unit 34. The first frame memory unit 36 and the second frame memory unit 38 perform read and write operations according to signals applied from the address selector 80 to alternately select data. The part 40 is applied. That is, a read address signal generator 60 and a write address signal generator 70 are connected to the address selector 80, and the address selector 80 is a read signal applied from the read address signal generator 60. And a write signal applied from the write address signal generator 70 to the first frame memory unit 36 and the second frame memory unit 38 alternately. Accordingly, since the first frame memory unit 36 and the second frame memory unit 38 alternately perform a read operation and a write operation, the second frame while the first frame memory unit 36 executes the read operation. The memory unit 38 executes the write operation, and the second frame memory unit 38 executes the read operation while the first frame memory unit 36 executes the write operation. The data selection unit 40 is connected to the first frame memory unit 36 and the second frame memory unit 38, and the data selection unit 40 includes the first frame memory unit 36 and the second frame. Since data are alternately selected from the memory unit 38 and applied to the PDP driver 50, the video signal is displayed on the screen.

At this time, if a stop signal for temporarily stopping the operation of the video signal displayed on the screen is applied to the microcomputer 90 connected to the address selector 80, the microcomputer 90 addresses the clock-still signal. To the selector 80. When the clock-still signal is applied from the microcomputer 90, the address selector 80 applies a still-pulse signal to the data selector 40, and at the same time, the first frame memory unit 36 And the data-select signal applied to the second frame memory unit 38 repeatedly apply the selected operation. That is, since the data-select signal applied from the address selector 80 to the first frame memory 36 and the second frame memory 38 corresponds to a pulse signal, the pulse operation stops and a constant high or low signal is received. Will continue to apply. When a constant data-select signal is applied from the address selector 80 to the first frame memory 36 and the second frame memory 38, the data selector 40 performs the read and write operations. It will continue to repeat. If the data selector 40 repeatedly executes the read and write operations, a constant image is continuously applied to the PDP driver 50 so that a still picture is displayed on the screen.

If the normal operation signal is applied to the microcomputer 90 while the still image is displayed on the screen while constant data is continuously applied to the PDP driving unit 50, the microcomputer 90 clocks again to the address selector 80. Since the steel signal is applied and the address selector 80 performs the normal operation by the second clock-steel signal applied from the microcomputer 90, the normal screen is displayed on the screen of the PDP driver 50. .

In more detail with reference to FIG. 3, the vertical synchronization signal Vsync and the clock-steel signal are applied from the microcomputer 90 to the address selector 80, and the clock-steel signal normally corresponds to a low state. The vertical synchronization signal is continuously applied with a pulse signal of a certain period. According to the pulse period of the vertical synchronization signal, the address selector 80 applies a data-pulse signal to the first frame memory unit 36 and the second frame memory unit 38 to perform read and write operations in the first frame. The memory unit 36 and the second frame memory unit 38 are executed. Since the address selector 80 normally applies the still-pulse signal in a low state to the data selector 40, the data selector 40 normally operates the first frame memory unit 36 and the second frame memory unit. Alternately select data from (38) and apply it to the PDP driving section (50). At this time, when a high pulse signal is generated from the microcomputer 90 to the clock-steel signal in the low state applied to the address selector 80, the address selector 80 immediately transmits the still-pulse to the data selector 40. The signal is switched to a high-state still-pulse signal, and a data-select signal applied to the first frame memory unit 36 and the second frame memory unit 38 is also immediately low or high. Will continue to be applied. The first frame memory section 36 and the second frame memory section 38 repeatedly execute read and write operations by the data select signal applied from the address selector 80. That is, if the first frame memory unit 36 has been performing the read operation, the read operation is repeatedly executed and the second frame memory unit 38 repeatedly executes the write operation. In addition, since the data selector 40 continuously applies the still-pulse signal applied from the address selector 80 to a high state, the data selector 40 is the same from the first frame memory 36 and the second frame memory 38. Since the data is repeatedly selected and applied to the PDP driver 50, still images appear on the screen of the PDP driver 50 because the image corresponding to the same data is displayed.

As can be seen from the above description, the present invention allows the microcomputer to apply a clock-still signal to the address selector when a stop signal for temporarily stopping the operation of the video signal displayed on the screen is applied to the microcomputer. When a clock-still signal is applied to the address selector from the microcomputer, the address selector controls the operations of the first frame memory unit and the second frame memory unit to repeatedly execute the current operation corresponding to the read operation or the write operation. Since only one constant image signal is applied to the PDP driver through the selection unit, a still image is displayed on the screen.

Claims (2)

First and second buffer units 32 and 34 receiving image input data complementary to each other according to the input level of the data selection signal; A first frame memory unit 36 which reads and writes input image data from the first buffer unit 32 in units of frames; A second frame memory unit 38 which reads and writes input image data from the second buffer unit 34 on a frame-by-frame basis, complementarily to the first frame memory unit 36; A PDP driver (50) for displaying image data read and input from the first and second frame memory units (36, 38) on a PDP panel; And PDP- including still picture control means for controlling one of the first and second frame memory sections 36 and 38 to continue only the write operation and the other to continue the read operation in accordance with a still picture selection signal from the outside. TV still picture display. 2. The apparatus of claim 1, wherein the still picture control means comprises: a data selector (40) for selectively outputting read data of the first and second frame memory parts (36, 38) to the PDP driver (50); The read and write address signals of the first and second frame memory units 36 and 38 are inputted by receiving the vertical synchronization signal Vsync, the still picture selection signal (Clock-still), the write address signal, and the read address signal of the image signal. And an address selector (80) for generating and outputting a select control signal (still-pulse) to the data selector (40).

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