JP3007771B2 - Lead frame - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame, and more particularly to a lead frame useful for inspection of dimensional errors.

[0002]

2. Description of the Related Art In general, a lead frame is subjected to fine processing using an etching technique to form inner leads, outer leads and the like. If the etching conditions (temperature, time, etc.) differ, overetching or underetching may occur, which may cause dimensional errors. Therefore, in order to make the semiconductor device as a final product more reliable, it is necessary to measure the dimensions of each part of the lead frame before mass production, and such a process becomes one of the important inspection processes. I have.

Hereinafter, a conventional lead frame will be described with reference to the drawings. FIG. 7 shows a configuration of a conventional lead frame. In FIG. 1, reference numeral 101 denotes a lead frame, the substrate of which is made of iron / nickel alloy, copper, or the like. Reference numeral 102 denotes a die pad on which a semiconductor chip is mounted. 103 is an inner lead part,
This is a portion that is electrically connected to the chip by wire bonding. Reference numeral 104 denotes an outer lead portion, which serves as an external terminal of the semiconductor integrated circuit. Reference numeral 105 denotes a guide hole formed of a through hole, and when the lead frame is transported by a machine, the guide hole 105 is supported and transported.

When performing dimensional inspection on a lead frame having such a structure, for example, the width of the tip of the inner lead, the distance between adjacent inner leads, the width of the outer lead,
Alternatively, actual dimensions such as the diameter of the guide hole were measured, and it was inspected whether or not these dimensions were within a standard allowable range. If the value is within the standard allowable range, the process proceeds to the next step such as mounting of the semiconductor chip or resin sealing, and the semiconductor device is completed. If the value is outside the standard allowable range, it is determined to be defective.

[0005]

However, the types of semiconductor devices generally range to several hundred types, and the dimensions of each part of the lead frame are different for each type. For this reason, data after dimensional measurement must be classified and managed for each product type, and data for a very large number of items must be managed, so that the conventional lead frame dimensional inspection process is very troublesome. Was.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to easily perform a dimension inspection of a lead frame irrespective of the type of a product.

[0007]

According to the present invention, a test pattern having a fixed size is formed on a substrate of a lead frame irrespective of the type of semiconductor device.

[0008]

[Function] Since a test pattern having a fixed size is formed regardless of the type, there is no need to measure the actual size that differs depending on the type, and dimensional data is managed based on the fixed size between different types. Can be.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the structure of a lead frame according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a lead frame, the substrate of which is made of an iron-nickel alloy, copper, or the like. Reference numeral 2 denotes a die pad on which a semiconductor chip is mounted. Reference numeral 3 denotes an inner lead portion which is electrically connected to the chip by wire bonding. Reference numeral 4 denotes an outer lead portion, which serves as an external terminal of the semiconductor integrated circuit. Reference numeral 5 denotes a guide hole formed of a through hole. When the lead frame is transported by a machine, the lead frame is supported and transported.

Reference numeral 6 denotes a test pattern forming area provided on the substrate of the lead frame 1. Although various modes are conceivable as test patterns formed in the test pattern forming region 6, the shape and dimensions of the test patterns formed on each lead frame are constant in any case, and the type of the semiconductor device is different. The size is constant even if different. Therefore, even when dimensional inspection is performed on lead frames covering a plurality of types, management can be performed with a constant value.

A specific embodiment of the test pattern will be described with reference to the drawings. FIG. 2 shows a first embodiment of the test pattern. In the figure, reference numeral 6 corresponds to the test pattern formation area 6 shown in FIG. Reference numeral 6a denotes a test pattern, which comprises a rectangular through hole. The through hole is formed with a predetermined size, and is formed by etching at the same time as etching the lead frame. Therefore, when an error occurs in the actual size of the inner lead or the like of the lead frame due to overetching or underetching, an error also occurs in the size of the test pattern 6a formed of the through-hole, and the error deviates from a predetermined value. .

The test pattern 6a has a fixed size regardless of the type of the semiconductor device. Therefore, the masks used for etching the lead frame have different patterns and dimensions depending on the product type. However, when the test pattern is formed at a constant size regardless of the product type, a fixed test pattern can be easily formed. it can.

However, if the thickness of the substrate of the lead frame is different, the dimensions of the test pattern may be different. That is, even if the mask has a certain size, the etching is spread in the lateral direction by etching deeper, and as a result, the area of the through hole is increased. In this way, even if the dimensions of the test pattern change according to the thickness of the lead frame, there are not so many types of substrate thickness compared to the hundreds of types, and the management data is smaller than before. Very low.

FIG. 3 shows a second embodiment of the test pattern. In the test pattern 6b shown in FIG. 5, five slits (or rectangular holes) having different widths are arranged in parallel. In the figure, the slit at the left end is the thickest, narrows in order, and the slit at the right end is the thinnest.

Also in this embodiment, the test pattern is formed by etching simultaneously with the etching of the lead frame. In the present embodiment, it is assumed that the thinnest slit at the right end does not penetrate during normal etching, and the thickest slit at the left end always penetrates during normal etching. The three middle slits are set so as to pass through or not pass through in a normal etching range. Therefore, in the case of overetch, the narrowest slit at the right end also penetrates, so that all five slits (or holes) penetrate, and conversely, in the case of underetch, all five slits (or holes) are blocked. Would.

In order to form the test pattern shown in FIG. 3, the width of the narrowest slit is made smaller than the thickness of the substrate, and the width of the thickest slit is made sufficiently larger than the thickness of the substrate. Good. Generally, it is difficult to penetrate a slit having a width smaller than the thickness of the substrate by etching. Therefore, if a slit that should not be penetrated is penetrated, it can be determined as over-etch, and if a slit that must be penetrated is always blocked, it can be determined as under-etch. Specifically, several slits having a width of about 0.25 mm to 0.08 mm may be formed in the thickness order on a substrate having a thickness of about 0.2 mm. The present invention is not limited to the above example, and the number of slits closed by under-etching or the number of slits penetrated by over-etching can be arbitrarily adjusted depending on how the width of the slit is set. Also, the test pattern 6b has a fixed size regardless of the type of the semiconductor device as in the first embodiment.

In the second embodiment, in addition to the same effects as those in the first embodiment, there is an advantage that over-etch and under-etch can be easily visually determined. For example, by irradiating light on the test pattern 6b at the time of inspecting the dimensions of the lead frame, overetching or the like can be determined only by looking at the shadow created by the transmitted light.

FIG. 4 shows a third embodiment of the test pattern. In the figure, the test patterns are composed of 6c and 6d. The configuration of 6c is the same as the test pattern 6b shown in FIG. On the other hand, the test pattern 6d is 6
The same five slits as in c are arranged perpendicular to 6c.

With this configuration, in addition to the same effect as in the second embodiment, the normality of the etching in the left and right direction and the degree of the etching in the normal direction of the vertical etching can be inspected.

FIG. 5 shows a fourth embodiment of the test pattern. In the drawing, a test pattern 6e is formed by arranging slits formed of through holes in a radial pattern. According to this configuration, it is possible to determine the degree of etching not only in the vertical and horizontal directions but also in all directions.

FIG. 6 shows a fifth embodiment of the test pattern. In the present embodiment, unlike the above-described embodiment, a test pattern for checking whether the plating position is correct or not is shown instead of checking the etching degree. When plating is performed on a part of the lead frame (for example, on the die pad), the plating is partially performed using a plating mask made of silicone rubber or the like. In this embodiment, plating can be performed on the test pattern. Holes in the mask as before. The holes of this mask are set so that plating is performed at a position and size corresponding to 6 g in FIG. 6A. On the other hand, a predetermined plating shift determination area 6f is set on the substrate of the lead frame, and if plating is performed within this area range, the plating position is determined to be normal, and FIG.
As shown in (b), when the plating 6g exceeds the range of the determination area 6f, it can be determined that the actual plating position is also abnormal.
The positioning of the determination region 6f can be easily realized by forming a circular groove by half etching, for example. Further, it is preferable that the dimension of the determination area 6f is set in accordance with the allowable range of the plating deviation. For example, if the permissible range of plating deviation is ± 1 mm, plating 6 g
The radius of the determination area 6f may be made larger by 1 mm than the radius of. With this setting, if a plating shift occurs, the plating 6g always exceeds the determination area 6f,
The presence / absence of plating deviation can be determined at a glance without having to determine the actual dimensions.

The shapes of the determination region 6f and the plating 6g are not limited to circles, but may be other shapes. Also, the test pattern has a constant shape and a constant size irrespective of the type of the product, or the size is changed in accordance with the difference in the allowable range of the plating deviation. Therefore, even when the plating position is inspected for the lead frames of a plurality of types, it is possible to manage a certain value.

[0024]

As described above, according to the present invention, a test pattern having a fixed size is formed on a substrate of a lead frame regardless of the type of semiconductor. The management can be performed, and the dimension inspection process of the lead frame is greatly simplified.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a lead frame of the present invention.

FIG. 2 is a diagram showing a configuration of a test pattern according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a test pattern according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a test pattern according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a test pattern according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a test pattern according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional lead frame.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Die pad 3 Inner lead 4 Outer lead 5 Guide hole 6 Test pattern formation area 101 Lead frame 102 Die pad 103 Inner lead 104 Outer lead 105 Guide hole

Claims (1)

(57) [Claims] 1. A lead formed by an etching technique.
Test putter that can inspect the degree of etching of the frame
A lead frame having a lead frame.
A test pattern having a predetermined size is formed on a substrate constituting a system.
The test pattern is formed by etching simultaneously with the formation of the lead frame, the test pattern is formed by arranging a plurality of slits having different widths in parallel, and the widest slit among the plurality of slits has a width larger than the thickness of the substrate. The width of the narrowest slit is smaller than the thickness of the substrate, and the dimensions of each slit forming the test pattern are different from other lead frames regardless of the product type. A lead frame characterized by being constant.