JP2996049B2 - Manufacturing method of multilayer ceramic electronic component - Google Patents

Manufacturing method of multilayer ceramic electronic component

Info

Publication number
JP2996049B2
JP2996049B2 JP9334393A JP9334393A JP2996049B2 JP 2996049 B2 JP2996049 B2 JP 2996049B2 JP 9334393 A JP9334393 A JP 9334393A JP 9334393 A JP9334393 A JP 9334393A JP 2996049 B2 JP2996049 B2 JP 2996049B2
Authority
JP
Japan
Prior art keywords
laminate
ceramic
mother
chips
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9334393A
Other languages
Japanese (ja)
Other versions
JPH06310366A (en
Inventor
良至 松浦
一隆 西
健一 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP9334393A priority Critical patent/JP2996049B2/en
Publication of JPH06310366A publication Critical patent/JPH06310366A/en
Application granted granted Critical
Publication of JP2996049B2 publication Critical patent/JP2996049B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、例えば積層コンデンサ
のような積層セラミック電子部品の製造方法に関し、特
に、未焼成のマザーの積層体から個々の積層セラミック
電子部品単位の積層体チップを得る工程が改良された積
層セラミック電子部品の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer ceramic electronic component such as a multilayer capacitor, and more particularly to a process for obtaining a multilayer chip for each multilayer ceramic electronic component from an unfired mother laminate. The present invention relates to a method for manufacturing a multilayer ceramic electronic component having improved characteristics.

【0002】[0002]

【従来の技術】積層セラミック電子部品の製造に際して
は、量産性を高めるために、通常、マザーの積層体を用
意し、該マザーの積層体を個々の積層セラミック電子部
品単位に切断してから焼成する方法が用いられている。
2. Description of the Related Art When manufacturing a multilayer ceramic electronic component, a mother laminate is usually prepared, and the mother laminate is cut into individual multilayer ceramic electronic component units and fired in order to enhance mass productivity. Is used.

【0003】例えば、積層コンデンサの製造方法を例に
とると、まず、多数の内部電極を並設して埋設した未焼
成のマザーの積層体を得る。しかる後、マザーの積層体
を切断し、マザーの積層体を個々の積層コンデンサ単位
の積層体チップに切断する。
For example, taking a method of manufacturing a multilayer capacitor as an example, first, an unfired mother laminate in which a number of internal electrodes are buried side by side is obtained. Thereafter, the mother laminate is cut, and the mother laminate is cut into laminate chips of individual multilayer capacitor units.

【0004】上記のようにして得られる積層体チップの
一例を図1に示す。積層体チップ1では、積層体2内
に、内部電極3,5が未焼成のセラミック層を介して隔
てられて厚み方向に重なり合うように配置されている。
FIG. 1 shows an example of a laminated chip obtained as described above. In the multilayer chip 1, the internal electrodes 3 and 5 are arranged in the multilayer body 2 so as to overlap with each other in the thickness direction while being separated by an unfired ceramic layer.

【0005】上記のようにして得られた積層体チップ1
は、通常、積層体チップ同士の合着を防止するために振
動を与えて分離され、しかる後、焼成される。焼成後
に、外部電極の形成等を行うことにより、最終的な積層
コンデンサが得られる。
[0005] The laminated chip 1 obtained as described above
Is usually separated by applying a vibration to prevent bonding of the stacked chips, and then fired. After firing, by forming external electrodes and the like, a final multilayer capacitor is obtained.

【0006】[0006]

【発明が解決しようとする課題】上記のように、従来の
積層セラミック電子部品の製造方法では、焼成に先立ち
マザーの積層体から個々のセラミック電子部品単位の積
層体チップに切断され、多数の積層体チップが得られて
いる。しかしながら、この積層体チップのセラミック部
分は、セラミック粉末の他に合成樹脂バインダー及び溶
剤を含む。従って切断された後において、隣接する積層
体チップ同士が接触すると、該バインダー及び溶剤によ
り合着しがちであるという問題があった。この積層体チ
ップ同士の合着は、上述した振動の付加による分離工程
を行うことにより、ある程度は防止される。
As described above, in the conventional method for manufacturing a multilayer ceramic electronic component, prior to firing, the mother laminate is cut into individual ceramic electronic component-unit laminate chips, and a large number of laminate chips are cut. A body chip has been obtained. However, the ceramic portion of the laminated chip contains a synthetic resin binder and a solvent in addition to the ceramic powder. Therefore, there is a problem in that when the adjacent stacked chips come into contact with each other after being cut, they tend to be coalesced by the binder and the solvent. The bonding of the laminated chips is prevented to some extent by performing the above-described separation step by applying vibration.

【0007】しかしながら、振動を与えて積層体チップ
同士の合着を防止したとしても、該分離工程後に、複数
の積層体チップ同士が再度接触し、その状態のまま焼成
されると、やはり、複数の積層体チップ同士が一体化さ
れた焼結体チップが得られることになる。
However, even if vibration is applied to prevent the bonding of the stacked chips, if the stacked chips come into contact again after the separation step and are fired in that state, a plurality of stacked chips will still be formed. Thus, a sintered chip in which the laminated chips of the above are integrated is obtained.

【0008】上記のように隣合う積層体チップ同士が合
着した結果得られた焼結体では、その後分離されたとし
ても、無理に分割されることになるため、所望どおりの
形状の焼結体を得ることはできない。すなわち、最終的
に得られた焼結体チップにおいて欠けや割れが生じがち
であった。
[0008] As described above, the sintered body obtained as a result of the bonding of the adjacent laminated chips is forcibly divided even if it is subsequently separated, so that the sintered body having the desired shape is sintered. You can't get your body. That is, chips and cracks tend to occur in the finally obtained sintered body chip.

【0009】本発明の目的は、個々の積層体チップ同士
の合着を効果的に防止し、それによって最終的に得られ
た焼結体チップにおける割れや欠けの発生を抑制し得
る、積層セラミック電子部品の製造方法を提供すること
にある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer ceramic which can effectively prevent the bonding of individual multilayer chips and thereby suppress the occurrence of cracks and chips in the finally obtained sintered chip. An object of the present invention is to provide a method for manufacturing an electronic component.

【0010】[0010]

【課題を解決するための手段】本発明は、複数個の内部
電極が並設して埋設された未焼成のマザーのセラミック
積層体を用意する工程と、前記マザーのセラミック積層
体を厚み方向に加圧する工程と、加圧された前記マザー
のセラミック積層体を減圧下において放置する前処理工
程と、前記前処理工程後に、前記マザーのセラミック積
層体を個々のセラミック電子部品単位の積層体チップに
切断する工程と、前記切断により得られたセラミック積
層体チップを焼成する工程とを備えることを特徴とす
る、積層セラミック電子部品の製造方法である。
The present invention SUMMARY OF THE INVENTION includes the steps of preparing an unfired mother ceramic laminate in which a plurality of internal electrodes are embedded in parallel, the ceramic laminate of the mother
Pressing the body in the thickness direction, a pretreatment step of leaving the pressurized mother ceramic laminate under reduced pressure, and after the pretreatment step, the mother ceramic laminate is separated into individual ceramic electronic component units. And a step of firing the ceramic laminated chip obtained by the cutting. A method of manufacturing a laminated ceramic electronic component, comprising:

【0011】本発明において、上記マザーのセラミック
積層体を用意する工程は、例えば、複数の内部電極を構
成するための導電ペーストが印刷されたセラミックグリ
ーンシートを複数枚積層し、必要に応じて上下に内部電
極の印刷されていない複数枚のセラミックグリーンシー
トを積層し、厚み方向に圧着することにより行われる。
あるいは、合成樹脂フィルム等の支持基材上において、
セラミック粉末含有ペーストを印刷し、乾燥し、次に導
電ペーストを印刷し乾燥する工程を適宜繰り返すことに
よっても行い得る。
In the present invention, the step of preparing the mother ceramic laminate includes, for example, laminating a plurality of ceramic green sheets on which a conductive paste for forming a plurality of internal electrodes is printed, and vertically This is performed by laminating a plurality of ceramic green sheets on which no internal electrodes are printed and pressing them in the thickness direction.
Alternatively, on a supporting substrate such as a synthetic resin film,
The step of printing and drying the ceramic powder-containing paste and then the step of printing and drying the conductive paste may be appropriately repeated.

【0012】また、本発明における前処理工程は、上記
のようにして得られたマザーのセラミック積層体を減圧
下に放置することにより行われるが、通常、常温におい
て、8000Pa以下(60mmHg以下)に30〜2
40分放置することにより行われる。もっとも、この減
圧度及び放置時間は、使用するマザーのセラミック積層
体の寸法及び材料組成によっても異なるため、一義的に
は定め得ない。しかしながら減圧度が大きい場合(すな
わち圧力が低すぎる場合)及び放置時間が長すぎる場合
には、マザーのセラミック積層体表面が乾燥し過ぎ、好
ましくない。また、減圧度が小さい場合(圧力が高すぎ
る場合)及び放置時間が短すぎる場合には、マザーのセ
ラミック積層体表面からの溶剤および水の飛散が十分に
行われないため、積層体チップ同士の合着を効果的に防
止することができない。上記減圧度及び放置時間は、上
記のような観点から個々のマザーの積層体に応じて定め
られる。 なお、上記前処理工程以後の工程、すなわ
ち、マザーのセラミック積層体を個々のセラミック積層
体チップに切断する工程及び個々のセラミック積層体チ
ップを焼成する工程等については従来より公知の積層セ
ラミック電子部品の製造方法に従って行うことができ
る。すなわち、上記切断は、切断刃を用いたりダイシン
グ等により行うことができ、焼成は、公知慣用の焼成炉
を用いて行うことができ、さらに焼成後の外部電極の付
与等についても従来より周知の積層セラミック電子部品
の製造方法に従って任意に行い得る。
The pretreatment step in the present invention is carried out by leaving the mother ceramic laminate obtained as described above under reduced pressure. 30-2
It is performed by leaving it for 40 minutes. However, since the degree of pressure reduction and the standing time vary depending on the size and material composition of the mother ceramic laminate used, they cannot be uniquely determined. However, when the degree of pressure reduction is large (that is, when the pressure is too low) and when the standing time is too long, the surface of the mother ceramic laminate is too dry, which is not preferable. In addition, when the degree of decompression is small (when the pressure is too high) or when the standing time is too short, the solvent and water are not sufficiently scattered from the surface of the mother ceramic laminate, so that the chip between the laminate chips is not formed. Coalescence cannot be effectively prevented. The degree of pressure reduction and the standing time are determined according to the individual mother laminates from the above viewpoint. The steps after the pretreatment step, that is, the steps of cutting the mother ceramic laminate into individual ceramic laminate chips and firing the individual ceramic laminate chips, etc., are conventionally known multilayer ceramic electronic components. Can be carried out in accordance with the production method. That is, the above-mentioned cutting can be performed by using a cutting blade or dicing or the like, and the firing can be performed using a known and commonly used firing furnace. It can be carried out arbitrarily according to the manufacturing method of the multilayer ceramic electronic component.

【0013】[0013]

【作用】本発明においては、マザーのセラミック積層体
段階において、上記のように減圧下に放置することによ
り、マザーのセラミック積層体中に含まれている溶剤及
び水分の一部が飛散される。その結果、切断により得ら
れた個々の積層体チップにおけるバインダー及び水分の
含有率が低められる。よって、切断された積層体チップ
同士の合着が、上記水分及び溶剤の含有率の低下により
効果的に抑制される。
In the present invention, in the stage of the mother ceramic laminate, a part of the solvent and moisture contained in the mother ceramic laminate are scattered by being left under the reduced pressure as described above. As a result, the content of the binder and water in each of the laminated chips obtained by cutting is reduced. Accordingly, the bonding of the cut laminated chips is effectively suppressed by the reduction in the content of the water and the solvent.

【0014】すなわち、本発明は、マザーのセラミック
積層体を得るに際してはある程度の水分及び溶剤等を含
有させることは避けられないが、マザーのセラミック積
層体を得た後には、上記のような水分及び溶剤の含有率
を低めてもよいこと、ならびに切断後の積層体チップの
合着が含有されている水分及び溶剤により引き起こされ
ることに着目し、マザーのセラミック積層体段階で上記
水分及び溶剤の一部を飛散させることにより、個々の積
層体チップ同士の合着を抑制したことに特徴を有する。
That is, in the present invention, it is inevitable that a certain amount of water and a solvent are contained in obtaining the mother ceramic laminate, but after obtaining the mother ceramic laminate, the above-mentioned water content is removed. And that the content of the solvent may be reduced, and that the bonding of the laminated chip after cutting is caused by the contained moisture and solvent, and the above-mentioned moisture and solvent are mixed at the mother ceramic laminate stage. It is characterized in that coalescence between individual stacked chips is suppressed by scattering a part.

【0015】[0015]

【発明の効果】本発明によれば、マザーのセラミック積
層体段階において、減圧下に放置することにより溶剤及
び水分の一部が飛散されてマザーのセラミック積層体の
水分及び溶剤の含有率が低下される。従って、切断によ
り得られた個々の積層体チップにおいても水分及び溶剤
の含有率が低められているため、該積層体チップ同士の
合着を効果的に抑制することができる。
According to the present invention, in the stage of the mother ceramic laminate, a part of the solvent and the moisture is scattered by being left under reduced pressure, and the content of the moisture and the solvent in the mother ceramic laminate is reduced. Is done. Accordingly, since the content of the water and the solvent is also reduced in each of the laminated chips obtained by cutting, the bonding of the laminated chips can be effectively suppressed.

【0016】よって、本発明によれば、積層体チップ同
士の合着が生じ難いため、所望どおりの形状の焼結体チ
ップを得ることができ、焼結体チップの割れや欠けの発
生を抑制することができる。従って、セラミック積層電
子部品の不良品率を低めることが可能となる。
Therefore, according to the present invention, it is difficult for the laminated chips to be bonded to each other, so that a sintered chip having a desired shape can be obtained, and the occurrence of cracks and chipping of the sintered chip can be suppressed. can do. Therefore, the defective product rate of the ceramic multilayer electronic component can be reduced.

【0017】[0017]

【実施例の説明】以下、本発明の一実施例を説明するこ
とにより、本発明を明らかにする。チタン酸バリウム粉
末、バインダーとしての酢酸ビニル樹脂(主成分として
の酢酸ビニル及び可塑剤等を含むもの)及び溶剤として
の水を混練してなるセラミックスラリーをドクターグレ
ード法によりシート成形し、厚み20μmのセラミック
グリーンシートを得た。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be clarified by describing one embodiment of the present invention. A ceramic slurry obtained by kneading barium titanate powder, a vinyl acetate resin (containing vinyl acetate and a plasticizer as a main component) as a binder, and water as a solvent is formed into a sheet by a doctor grade method, and has a thickness of 20 μm. A ceramic green sheet was obtained.

【0018】図2に示すように、上記のようにして得ら
れたセラミックグリーンシート11,12の一方主面に
導電ペーストをスクリーン印刷法により印刷し、厚み
1.0μmの複数の内部電極13,14を整列形成し
た。
As shown in FIG. 2, a conductive paste is printed on one main surface of the ceramic green sheets 11 and 12 obtained as described above by screen printing, and a plurality of 1.0 μm-thick internal electrodes 13 and 12 are formed. 14 were aligned.

【0019】内部電極の形成されたセラミックグリーン
シート11,12を交互に合計16枚積層し、上下に複
数枚の外部電極の印刷されていないセラミックグリーン
シートを積層し、厚み方向に圧着することにより、マザ
ーのセラミック積層体15を得た(図3参照)。
A total of 16 ceramic green sheets 11 and 12 on which internal electrodes are formed are alternately laminated, and a plurality of ceramic green sheets on which no external electrodes are printed are laminated one above the other and pressed in the thickness direction. Thus, a mother ceramic laminate 15 was obtained (see FIG. 3).

【0020】上記のようにして得たマザーのセラミック
積層体15を、8000Paの圧力下において60分放
置した。しかる後、マザーのセラミック積層体15を厚
み方向に切断して平面形状が1.6mm×0.8mmの
個々の積層体チップを得た。
The mother ceramic laminate 15 obtained as described above was left under a pressure of 8000 Pa for 60 minutes. Thereafter, the mother ceramic laminate 15 was cut in the thickness direction to obtain individual laminate chips having a planar shape of 1.6 mm × 0.8 mm.

【0021】上記のようにして得られた複数の積層体チ
ップを1300℃の温度に2〜4時間放置することによ
り焼成し、焼結体チップを得た。得られた焼結体チップ
の両端面に、導電ペーストを塗布し、焼き付けることに
より、一対の外部電極を形成し、積層コンデンサを得
た。
The plurality of laminated chips obtained as described above were fired by leaving them at a temperature of 1300 ° C. for 2 to 4 hours to obtain sintered chips. A conductive paste was applied to both end surfaces of the obtained sintered body chip and baked to form a pair of external electrodes, thereby obtaining a multilayer capacitor.

【0022】上記のようにして前処理工程後に切断され
た個々の積層体チップを焼結した段階において、積層体
チップ同士が合着して焼結されたものは皆無であった。
比較のために、上記減圧下に放置する前処理工程を行わ
なかった場合には、1.53%(1000個当たり)の
割合で積層体チップ同士の合着が生じており、従って同
じ割合で一体化された焼結体チップが発生していた。よ
って、本実施例によれば、上記減圧下に放置する前処理
工程により、積層体チップ同士の合着を確実に防止する
ことができ、従って所望どおりの焼結体チップの得られ
ることがわかる。
At the stage of sintering the individual laminated chips cut after the pretreatment step as described above, none of the laminated chips were bonded and sintered.
For comparison, when the pretreatment step of leaving the substrate under the reduced pressure was not performed, the bonding of the stacked chips occurred at a rate of 1.53% (per 1,000 pieces), and therefore, the bonding was performed at the same rate. An integrated sintered body chip was generated. Therefore, according to the present example, it can be seen that the pretreatment step in which the laminated chips are left under reduced pressure can reliably prevent the bonding of the laminated chips, and thus a desired sintered chip can be obtained. .

【0023】なお、上記実施例は積層コンデンサの製造
方法に適用した例を示したが、本発明は、マザーのセラ
ミック積層体を切断して個々の積層体チップを得てセラ
ミック積層電子部品を製造する方法一般に適用すること
ができる。従って、積層セラミック圧電部品や積層イン
ダクタ等の他の積層セラミック電子部品の製造方法にも
適用することができる。
Although the above embodiment has been described with reference to an example in which the present invention is applied to a method of manufacturing a multilayer capacitor, the present invention manufactures a ceramic multilayer electronic component by cutting a mother ceramic multilayer to obtain individual multilayer chips. The method can be generally applied. Therefore, the present invention can be applied to a method of manufacturing another multilayer ceramic electronic component such as a multilayer ceramic piezoelectric component and a multilayer inductor.

【図面の簡単な説明】[Brief description of the drawings]

【図1】積層体チップを示す斜視図。FIG. 1 is a perspective view showing a laminated chip.

【図2】(a),(b)は、それぞれ、マザーのセラミ
ックグリーンシート及びその上に形成される内部電極パ
ターンを示す各平面図。
FIGS. 2A and 2B are plan views respectively showing a mother ceramic green sheet and an internal electrode pattern formed thereon.

【図3】マザーのセラミック積層体を示す斜視図。FIG. 3 is a perspective view showing a mother ceramic laminate.

【符号の説明】[Explanation of symbols]

11,12…マザーのセラミックグリーンシート 13,14…内部電極 15…マザーのセラミック積層体 11, 12: mother ceramic green sheet 13, 14, ... internal electrode 15: mother ceramic laminate

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01G 4/12 364 H01G 13/00 391 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. 6 , DB name) H01G 4/12 364 H01G 13/00 391

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 複数個の内部電極が並設して埋設された
未焼成のマザーのセラミック積層体を用意する工程と、前記マザーのセラミック積層体を厚み方向に加圧する工
程と、 加圧された 前記マザーのセラミック積層体を減圧下にお
いて放置する前処理工程と、 前記前処理工程後に、前記マザーのセラミック積層体を
個々のセラミック電子部品単位の積層体チップに切断す
る工程と、 前記切断により得られたセラミック積層体チップを焼成
する工程とを備えることを特徴とする、積層セラミック
電子部品の製造方法。
1. A step of preparing an unfired mother ceramic laminate in which a plurality of internal electrodes are juxtaposed and embedded, and a step of pressing the mother ceramic laminate in a thickness direction.
And a pretreatment step of leaving the pressurized mother ceramic laminate under reduced pressure; and after the pretreatment step, cutting the mother ceramic laminate into laminate chips of individual ceramic electronic component units. A method for manufacturing a multilayer ceramic electronic component, comprising: a step of firing the ceramic laminate chip obtained by the cutting.
JP9334393A 1993-04-20 1993-04-20 Manufacturing method of multilayer ceramic electronic component Expired - Fee Related JP2996049B2 (en)

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Application Number Priority Date Filing Date Title
JP9334393A JP2996049B2 (en) 1993-04-20 1993-04-20 Manufacturing method of multilayer ceramic electronic component

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JPH06310366A JPH06310366A (en) 1994-11-04
JP2996049B2 true JP2996049B2 (en) 1999-12-27

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Publication number Priority date Publication date Assignee Title
US7688567B2 (en) 2005-08-05 2010-03-30 Tdk Corporation Method of manufacturing multilayer capacitor and multilayer capacitor

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JPH06310366A (en) 1994-11-04

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