JP2993731B2 - Control method of hardware trace information - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for controlling hardware trace information in an input / output bus of a vector interrupt system.

[Conventional technology]

Generally, a computer system has a tracer for cyclically storing signals on a bus in the system for each clock or command for analysis of a cause when an error occurs, and for freezing the stored contents when an error occurs.

In the conventional tracer control system, when an error is detected, the tracer is frozen as shown in the specification of Japanese Patent Application No. 58-194152. It remains frozen until it is released.

However, as shown in the “VME Bus Architecture Manual”, when an interrupt is generated from an I / O device, the processor uses an interrupt acknowledgment to fetch the interrupt factor (vector) from the I / O device. A bus access called a cycle is performed. One of the input / output devices that is pending the interrupt request responds to this access. However, when the input / output device is a terminal or a communication line, the interrupt request may be interrupted. In particular, in the case of a terminal, it may occur frequently depending on the operation. As a result, no input / output device that is pending an interrupt request for bus access happens to receive a response, and a timeout may occur. As a result, there is a problem that the tracer is frozen.

If the tracer is frozen by mistake, the trace is kept frozen until the maintenance person releases the freeze, so that the trace information at the time of the occurrence of the abnormality cannot be collected. Also,
A method of saving the file and releasing the freeze at regular intervals is also conceivable, but the capacity of the tracer is very large due to the use of a large-capacity memory element, and there is no room to save unnecessary trace information in the file. In addition, the load on the input / output bus and file transfer for transferring large amounts of data for saving is large.Especially, even if the capacity of the memory element or the file increases, the speed does not change so much. Is unbearable due to the load balance of the entire system. (Timeouts due to interrupt request interruptions occur a few times within a few minutes, depending on the system.
In general, the process level is low due to low urgency, and it takes about several minutes to save trace information of several tens to several hundreds of bytes, so that trace information cannot be collected at a necessary timing. [Problem to be Solved by the Invention] In the above-mentioned prior art, no consideration is given to the tracer of the bus of the vector interrupt system, and there is a problem that the tracer is erroneously frozen.

It is an object of the present invention to solve this problem and to provide a tracer control system suitable for a bus of a vector interrupt system.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, a bus tracer determines a signal indicating a vector fetch cycle on a bus, and suppresses the freeze of the tracer if the vector fetch cycle is detected upon timeout. I made it.

[Action]

As a result, the tracer is not frozen even if the interruption request of the terminal or the like is interrupted, but is frozen only when the original abnormality occurs, and the trace information at that time can be collected.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described.

FIG. 1 shows the overall configuration of the embodiment. System bus 5
Is connected to a processor 11, a main memory 12, and an input / output adapter 14. An input / output bus 19 is connected to the input / output adapter, and an input / output device 15 is connected to the bus. The tracer 1 is connected to the system bus 5. Next, inside the tracer 1, there are provided a trace data memory 4 for cyclically storing signals on the bus for each command, a trace control unit 3 for controlling this, and a timeout monitoring mechanism 2 for monitoring a bus timeout. .

Gate 16 and gate 17 in the tracer control the freeze of the tracer. The timeout monitoring mechanism 2 turns on the signal 8 when the timeout is detected. The signal 6 is an interrupt acknowledge signal, which is ON when the processor 11 accesses to take in an interrupt factor (vector) from the input / output adapter 14, and other accesses (access to the main memory 12 or input / output). It is OFF when the output adapter 14 or the internal memory of the input / output device 15 is accessed. Therefore, when the timeout is detected, the signal 16 is turned on in the vector fetch cycle, so that the gate 16 is masked and the output 9 remains off. On the other hand, in a normal cycle, since the signal 6 is in the off state, the gate 16 is not masked, and when the signal 8 is turned on due to timeout detection, the gate output 9 is also turned on. The off gate 17 ORs the output 9 and the error response signal 7 on the bus, and the output 10 is input to the tracer control unit 3 as a freeze request signal.

FIG. 2 shows the internal configuration of the trace data memory 4. The RAM 30 is a RAM that stores trace information. The data input includes the main signal group 37 in the system bus 5.
Is entered. The output 38 returns to the gate 32 and is output to the read data bus 40. Gate 32 is controlled by tracer read enable signal 39. RAM writing is controlled by a tracer write signal 35. The output 36 of the counter 31 is connected to the address of the RAM. The control of the counter 31 is performed by a tracer count-up signal 34 and a count-down signal 33.

FIG. 3 shows the internal configuration of the trace control unit 3. The freeze flag 50 indicates the frozen state of the tracer, and is in the set state when in the frozen state. A freeze request signal 10 is connected to the set input. An access signal 54 for the freeze release address is input to the reset input, and the program or maintenance personnel can release the freeze by accessing the same address. When the program or maintenance person accesses the freeze flag read address, the signal 56 is turned on, and the output 57 of the freeze flag 50 is output to the read data bus 40 via the gate 50 and can be read. In the unfrozen state, the signal 58 is on, and each time the transfer request signal on the bus turns on, the tracer count-up signal 34 and the tracer write signal 35 turn on. As a result, updating and writing of the address of the RAM 30 are performed.
In the frozen state, the signal 57 is on, and the access to the tracer read address causes the signal 39 and the signal 53 to go off.
Turns on, the tracer countdown signal 33 turns on. Therefore, RAM3 is read every time a tracer is read.
The address of 0 is updated. The tracer read enable signal 39 is turned on by accessing the tracer read address.

FIG. 4 shows the internal configuration of the timeout monitoring mechanism 2. The counter 70 remains cleared when the transfer request signal 53 on the bus is in the off state, but starts counting up when the transfer request signal 53 is turned on. Clock generator 71
Supplies a clock for the count up.
Even if a certain time elapses, when this signal remains on, that is, when a timeout occurs, the output 72 of the counter 70 turns on and the timeout signal 8 turns on.

FIG. 5 shows a time chart of the embodiment. The first half of the time chart represents a case where a timeout has occurred in the vector fetch cycle. When the timeout signal 8 turns on, the interrupt acknowledge signal 6
Is in the ON state, the freeze request signal 10 is suppressed, and no freeze is performed. The latter half represents a case where a timeout has occurred in a normal bus access other than the vector fetch cycle. When the timeout signal 8 is turned on, the interrupt acknowledge signal 6 is in the off state.
The freeze request signal 10 turns on, and the freeze is performed.

FIG. 6 shows a modification of the present invention. In this case, the tracer and the timeout monitor are mounted on separate boards, and special signals cannot be passed between the two. The time-out monitoring mechanism 2 turns on the time-out signal 8 at the time of time-out detection. As a result, the error response signal 7 on the bus is turned on. On the other hand, in the tracer, when the interrupt acknowledge signal 6 is turned on by the AND gate 16, the freeze request signal 10 is suppressed even if the error response signal 7 is turned on, thereby preventing an erroneous freeze.

Further, as another modified example of the present invention, there is a method in which each processor determines whether or not it is a vector fetch cycle when a time-out is detected, and issues a tracer freeze command to the tracer only when it is not the fetch cycle. In particular,
The tracer is provided with a means for setting a freeze flag when an access is made to the freeze set address. On the other hand, the processor is provided with means for accessing the same address only when the time-out is detected, except in the vector fetch cycle. This method is effective in the case of a split transfer method in which another access can be activated between activation and response on the system bus.

〔The invention's effect〕

According to the present invention, it is possible to prevent an erroneous freeze of a tracer due to interruption of an interrupt in a vector interrupt bus, and to collect trace information at the time of occurrence of an original abnormality.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is an internal block diagram of the trace control unit, FIG. 4 is an internal block diagram of the timeout monitoring mechanism, FIG. 5 is a time chart of the embodiment, and FIG. FIG. 4 shows a block diagram of another embodiment of the present invention. 1 ... tracer, 11 ... processor, 12 ... main memory.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinichi Hanada 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Inventor Soichi Takatani 5-2-2 Omikacho, Hitachi City, Ibaraki Prefecture No. 1 Omika Plant, Hitachi, Ltd. (72) Inventor Eiki Shoko 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside of Hitachi Process Computer Engineering Co., Ltd. (72) Yoshihiro Nakano Omikamachi, Hitachi City, Ibaraki Prefecture 5-2-1, Hitachi, Ltd. Omika Factory (58) Fields surveyed (Int.Cl. ⁶ , DB name) G06F 13/00 G06F 11/30

Claims (4)

(57) [Claims] An apparatus having a bus, one or more interrupt generating means connected thereto, an apparatus having one or more interrupt receiving means, and a specific signal group stored cyclically. However, when an error occurs, the system is composed of a tracer that freezes the stored contents and a bus timeout monitoring mechanism.
In a system adopting a vector interrupt method for taking an interrupt factor from the interrupt generating device, a freeze of a tracer is suppressed if a vector capture cycle is detected when a timeout is detected. method. 2. The bus time-out monitoring mechanism according to claim 1, wherein the bus time-out monitoring mechanism outputs an error response signal on the bus when a time-out is detected, and the tracer freezes the tracer when the error response is detected in a vector fetch cycle. Control method of hardware trace information to be released. 3. The method according to claim 1, wherein said interrupt accepting device turns on an interrupt acknowledge signal on a bus during a bus access, while the tracer detects the interrupt acknowledge signal upon detecting a timeout. If is ON, a hardware trace information control method that suppresses the tracer freeze. 4. An interrupt receiving device according to claim 1, wherein the interrupt receiving device determines whether or not a time-out detection vector fetch cycle has occurred.
A hardware trace information control method that suppresses the tracer freeze when a timeout occurs in the vector capture cycle by issuing a tracer freeze command to the tracer only when not in the capture cycle.