JPS6232819B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a storage device control system, particularly a storage device control system which includes a disk cache memory to reduce read/write processing to the storage device.・For tracks or track groups where the frequency of staging processing performed when memory is accessed and no hits occur is undesirably high, further occurrence of staging processing is suppressed, and processing delays associated with staging processing are eliminated. The present invention relates to a storage device control system configured as described above.

When reading/writing a storage device, the processing time is longer than, for example, reading/writing from a RAM. Focusing on this point, we developed a disk cache memory in which the contents of the direct access storage device are staged and held in track units, and when accessing, if desired data is held, that data is accessed. It is being considered for use. This method is extremely effective when the desired data exists on the disk cache memory, that is, when the data has been hit. However, if there is no hit,
It is necessary to transfer the desired data to the host device and to stage the contents of the track containing the data on a disk cache memory. For this reason, in the case of a system that does not have disk cache memory, the processing of the input/output control unit (disk controller) is freed up by simply transferring the desired data to the host device. , this has the opposite effect of not being released until one track is staged on the disk cache memory.

In order to avoid this point, tuning is performed in advance according to the processing mode in order to improve the hit rate, but this alone is not necessarily sufficient and the staging processing increases undesirably. Something happens.

The present invention aims to solve this problem by preventing a new staging process from being performed for a predetermined period for a track or a group of tracks that have been staged an undesirably large number of times. The purpose is to suppress the occurrence of the above-mentioned adverse effects as much as possible. To this end, the storage device control system of the present invention includes a cache memory between the main storage device and the auxiliary storage device, and in response to a request for data transfer to the main storage device, requested data is transferred. When the data exists in the cache memory, data transfer is executed only between the cache memory and the main memory, and when the data does not exist in the cache memory, the data is included and has a predetermined amount of information. storage device control configured to perform both staging processing for storing track data consisting of a data group from the auxiliary storage device to the cache memory and processing for transferring data in the track data to the main storage device. In the system, for a track group that is a set of one or more track data on the auxiliary storage device, a staging count that counts the number of times that the track data belonging to the track group has been staged. A holding means and a timing means for setting an appropriate variable or fixed time interval are provided, and when the content of the staging number holding means exceeds a predetermined upper limit value within the set time interval, the above-mentioned When the data does not exist in the cache memory, the processing operation is to
The present invention is characterized in that processing related to data staging processing is prohibited until a new time interval is set by the timer. This will be explained below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 shows the configuration of essential parts of an embodiment of the input/output control device used in the present invention.

In FIG. 1, 1-0 and 1-1 are disk controllers corresponding to the input/output control device according to the present invention, 2 is a disk cache memory, 3 is a disk cache controller, and 4 is a disk cache memory. 5 is a cross call adapter that allows access to the storage device (disk memory) described later from multiple systems.
-0 and 5-1 respectively represent disk memories corresponding to direct access storage devices.

The disk cache memory 2 is configured to be read/written by the disk cache controller 3, and is configured to read/write data from, for example, several tens to several hundred tracks from the disk memories 5-0 and 5-1. Transferred and retained. Then, in response to access from the host device, the disk controller 1-0, for example,
The desired data is stored in disk cache memory 2.
If there is a hit, the disk cache memory 2 is accessed instead of accessing the disk memories 5-0 and 5-1. Also, if there is no hit, disk memory 5-0 or 5-1
access the desired data (e.g. a few bytes)
is transferred to the host device, and one track worth of data containing the desired data is staged on the disk cache memory 2 so as to be easily hit in subsequent accesses.

However, due to circumstances on the disk memories 5-0 and 5-1, the above-mentioned staging process is performed in units of one track, and as stated at the beginning of this specification, the staging process is performed in units of one track. This will produce the opposite effect of making a profit.

FIG. 2 shows the configuration of essential parts of an embodiment of an input/output control device used in the present invention, which attempts to solve this problem. Reference numerals 1-0 in the figure correspond to those in FIG. 1, and 6 is a control unit for stored program control that controls the disk controller 1-0, which is represented by a flowchart showing the main processing. , 7 is a loop counter, which corresponds to the timing device of the present invention, which counts up when the processing of the disk controller 1-0 is idle; 8 is a staging number holding unit; The number of times (i) that a track belonging to a track group corresponding to one or more tracks has been staged is counted.

As shown as the illustrated control unit 6, the disk
Only when there is no access request to the controller 1-0, the loop counter 7 is incremented by 1 every predetermined unit time through the illustrated route. When the contents of the loop counter 7 overflow, the contents (i) of the stage counter corresponding to each group in the staging count holding section 8 are reset.

On the other hand, when an access request occurs and the disk cache memory 2 is accessed and hit, the desired data is transferred from the disk cache memory 2 to the host device through the illustrated route, and Demonstrate the meaning of existence. If there is no hit in response to the access request, the contents of the staging count holding unit 8 are checked for the track group to which the track containing the desired data belongs. If the content (i) of the staging counter for the relevant track group has not reached the upper limit value, the content of the staging counter is incremented by 1 through the route shown in the diagram, and then the data is stored in the disk memory 5-0. Alternatively, 5-1 is accessed and the desired data is transferred to the host device, and the contents of one track containing the desired data are transferred to the disk cache.
It is staged on the memory 2 (at this time, roll-in/roll-out is performed using an LRU algorithm or the like as necessary, but this is omitted as it is not directly related to the present invention).

If the above-mentioned hit does not occur, the content (i) of the above-mentioned staging counter is checked, and if the upper limit value has been reached, the disk memory 5-0 or 5-1 is accessed through the illustrated route, The desired data is only transferred to the host device, and the above-mentioned staging process is not performed. Needless to say, this route corresponds to access processing for a system in which the disk cache memory 2 does not exist.
Even if the above-mentioned staging process is not performed, if another track belonging to the group existing on the disk cache memory 2 is accessed, it will become a hit and the processing speed will increase greatly, but if it does not become the above-mentioned hit again, When the track that was previously accessed is accessed, the illustrated route is retraced. However, the processing speed is substantially the same as in a system without disk cache memory 2.

In response to an access request, the contents of the staging count holding unit 8 are generally updated as described above. In some cases, the content (i) of the staging counter for a certain track group may reach the upper limit value, and the track group will not be newly staged. However, at the point when the contents of the loop counter 7 overflow after a predetermined period of time has elapsed, the staging
Since the contents of the counter (i) will be incremented all at once, the staging process will be canceled as follows:
limited to a certain period of time. However, in the case of the illustrated embodiment, if the disk controller is infrequently in an empty state, staging will be stopped for a relatively long period of time for a group for which staging has been stopped, that is, a group for which tuning has not been performed correctly. The desired effect will be greatly exerted. In addition, when the frequency of empty states is high, the adverse effect of staging is small, the staging is canceled more quickly, and the hit rate of the disk cache memory 2 is increased.

As described above, according to the present invention, it is possible to effectively suppress the adverse effects caused by staging processing for disk cache memory as much as possible, and improve the overall processing speed.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 shows the configuration of essential parts of an embodiment of the input/output control device used in the present invention. In the figure, 1-i is the disk controller, 2 is the disk cache memory, and 3 is the disk controller.
4 is a cross call adapter, 5-i is a disk memory, 6 is a control section, 7 is a loop counter, and 8 is a staging number holding section.

Claims (1)

[Claims] 1. A cache memory is provided between a main storage device and an auxiliary storage device, and in response to a request for data transfer to the main storage device, requested data is transferred to the cache memory. When the cache memory exists, data transfer is executed only between the cache memory and the main storage device, and when the data does not exist in the cache memory, the track is composed of a series of data groups containing the data and having a predetermined amount of information. - In a storage device control system that performs both a staging process for storing data from the auxiliary storage device to a cache memory and a process for transferring data in the track data to the main storage device, the auxiliary storage device a staging count holding means for counting the number of times of staging processing of track data belonging to the track group corresponding to a track group including one or more track data on the device; and clock means for setting a fixed and appropriate time interval, and when the content of the staging number holding means exceeds a predetermined upper limit value within the set time interval, the data is cached.
A storage device characterized in that, as a processing operation when the track data does not exist in the memory, processing related to staging processing of track data belonging to the track group is prohibited until the time measuring means sets a new time interval. control system. 2. The clocking means comprises a counter that increments at a constant period under the condition that there is no request for data transfer, and the time interval is set by an overflow of the counter. 2. The storage device control system according to item 1. 3. Claim 1 or 2, characterized in that the auxiliary storage device is a magnetic disk device.
The storage device control system described in Section 1.