JP2993645B2 - 4 phase demodulation circuit - Google Patents

Description

The present invention relates to a four-phase demodulation circuit for demodulating an audio signal in a satellite broadcast receiver.

[Prior Art] Generally, as shown in FIG. 5, a satellite broadcast receiver receives a radio wave from a broadcast satellite (1) with a parabolic antenna (2). It is converted to a frequency band and sent to the BS tuner (4). In the BS tuner (4), a desired channel is selected by a tuning circuit (5), FM demodulation is performed by an FM demodulation circuit (6), and then separated into a video signal and an audio signal by a video-audio separation circuit (7). I do. The video signal is reproduced from the original video signal by a de-emphasis circuit (8) and an energy diffusion signal removal circuit (9), and is applied to a video input terminal (11) of a television receiver (10). On the other hand, audio signals are four-phase demodulated (hereinafter referred to as QPSK)
The signal is demodulated by a circuit (12) and a PCM demodulation circuit (13), and the original audio signal is reproduced by a de-emphasis circuit (14). The audio input terminal (1) of the television receiver (10)
Add to 5). In this way, satellite broadcasting can be received.

In the above satellite broadcasting receiver, the QPSK circuit (1
2) is configured as shown in FIG. 4, and performs analog processing on demodulation of an audio signal. In this conventional QPSK circuit (12), the QPSK signal is divided into multipliers (17) (18), LPF (19) (2
0), the binarizers (21) and (22) and the phase difference detector (2
Sent to 3). In the phase difference detector (23), the phase of the carrier on the generation side of the QPSK signal and the VCO
The phase difference of the reproduced carrier generated from (24) is compared, and the VCO is passed through the loop filter (35) so that the difference becomes zero.
Apply control signal to (24). The oscillation signal from this VCO (24) is sent to one multiplier (17) via a -90 ° phase shifter (25), and is sent to the other multiplier (18) as it is to input the QPSK signal. Multiplied by the signal. Then, the phase difference gradually becomes 0, and is output from the binarizers (21) and (22) as demodulated signals. (26) is a bit clock recovery circuit.

However, since the conventional QPSK circuit (12) processes all analog signals, there are variations in circuit parameters, operation is somewhat unstable, and the output from the VCO (24) is a sine wave. Therefore, there is a problem that an error occurs in the phase shift amount in the −90 ° phase shifter (25).

Therefore, as shown in FIG. 3, the present applicant has proposed a circuit that solves the conventional problems by digitally demodulating QPSK.

The difference from the circuit of FIG. 4 is that the A / D converter (3) is connected between the QPSK input terminal (16) and the digital multipliers (27) and (28).
1) Insert and also multipliers (27) (28) and LPF (29)
(30) is the use of the digital form.

The problem is solved by adopting a configuration for performing such digital processing.

However, there are still some problems. That is, it is difficult to integrate the phase shifter (25), the multipliers (27) and (28), and the LPFs (29) and (30) into ICs.

The object of the present invention is to make this part an IC with a simple configuration.

"Means for Solving the Problems" The present invention provides two data information components each having a phase difference of 90 ° by splitting a QPSK signal input to a QPSK input terminal into two, and extracting the data information from the QPSK signal. The two data information components are sent to a demodulation output terminal for data information discrimination, the QPSK signal is sent to a VCO via a phase detector, and the VCO signal is sent to a phase shifter. A data information extraction signal is sent from the detector to the data information extraction means, and the phase difference between the input carrier and the reproduced carrier is fed back to the phase detector which controls the phase difference to be 0. In the subsequent stage, an A / D converter is interposed, and the data information extracting means receives the digital signal of the QPSK input signal and converts the reproduced carrier signal having a 90 ° phase difference into data. Consists of two D-FF circuits to broadcast extracting signal, said phase shifter is at least 3 for operating the four times the frequency of the reproduced carrier of the carrier from the VCO as a clock
D-FF circuits, and π / 2
A phase shifter configured to output a signal having a phase difference between the phase shifter and the phase detector, a sawtooth wave generated every π / 2 based on the output of the shift register,
The level of the sawtooth wave is detected by holding the coincidence point of the time axis with the sample pulse serving as the phase detection reference point of the QPSK input signal, and when the level is at the set intermediate position of the generated sawtooth wave, A four-phase demodulation circuit characterized in that an output for making the phases of a QPSK wave and a reproduced carrier coincide with each other is used as the VCO control signal.

"Operation" The A / D converter converts the QPSK signal into a digital
A sample pulse serving as a signal phase detection reference point is input to a sample hold circuit.

The VCO outputs a reproduced carrier wave having a frequency four times the frequency of the input QPSK wave and outputs at least three, specifically, four D-FFs.
Input to the clock terminal of the shift register
Each D-FF circuit sequentially outputs signals having a phase shift of 90 °. To the two D-FF circuits as the data information extracting means, a signal having a 90 ° phase shift is sent as a data information extracting clock. Also,
The reproduced carrier waves of each of the four D-FF circuits are sent to a phase detector via a logic circuit to generate saw-tooth waves having phases shifted by 90 °. Further, the phase detector detects the level of the sawtooth wave when the time axis of the sample pulse matches the time axis of the sawtooth wave, and when the level is at a set intermediate position of the generated sawtooth wave, It is determined that the phases of the QPSK wave and the reproduced carrier wave match each other. If it is shifted lower or higher, the phase of the recovered carrier needs to be advanced or delayed accordingly. Therefore, the output of the sample hold circuit is sent to the VCO as a control signal via the loop filter circuit and the D / A converter. Then, a signal from the VCO controlled by the control signal is added as a clock signal for the four D-FF circuits. The above operation is repeated until the phase difference becomes zero. A combination of data having a phase difference of 90 ° from the data information extracting means is binarized by a binarizer and sent to a television receiver as a demodulated output to determine the phase of the QPSK signal.

Embodiment An embodiment of the present invention will be described with reference to FIG.

The difference between FIG. 1 and FIG.
相 Phase shifter (25), multiplier (27) (28), LPF (29) (3
The part (0) is composed of six D-FF circuits and one NAND circuit, and the phase difference detector (23) is a logic circuit (40), a sawtooth wave generation circuit (41), a sample hold circuit (42),
It consists of a loop filter (35), and the VCO (24)
This is to output a signal having a frequency four times the frequency of the carrier. Of these, two D-FF circuits (36a) (36b) constitute data information extracting means, and four D-FF circuits (38
a) to (38d) shift register and NAND circuit (3
9) constitutes a phase shifter (25) as -90 ° phase shift means. Also, as described above, the VCO (24)
(B1) (b2) (b3) (b4) As shown in Fig. (A), a signal having a frequency four times that of the input QPSK signal is output.
Thus, a reproduced carrier wave with a phase shift of every 90 ° is obtained,
With these reproduced carrier waves, the sawtooth wave generation circuit (4
1) generates a sawtooth wave as shown in FIG. 2 (c) which is repeated every 90 °.

(32) is a D / A converter. A signal of a binary 1-bit digital value is input to the sample and hold circuit (42), and a sawtooth wave of the sawtooth wave generation circuit (41) is sampled by a sample pulse obtained based on the signal to obtain the D signal. Returning to the control signal as shown in (g) by the / A converter (32) is called D / A conversion.

In the above configuration, the QPSK signal as shown in FIG. 2 (d) input to the QPSK input terminal (16) is converted into a binary 1-bit digital quantity by the A / D converter (31). That is, as is clear from FIG. 2 (d), the pulse is limited as shown in FIG. This pulse (e) is applied to the sample and hold circuit (4
2), a sample pulse (f) for detecting a sawtooth wave shift as shown in (f) is obtained in the sample and hold circuit (42), and the shift of the sawtooth wave (c) is detected. The pulse (e) is supplied to two D-FF circuits (36a) (36b) functioning as a digital multiplier and a digital LPF.
To enter. As shown in FIG. 2 (a), the VCO (24) outputs a reproduced carrier having a frequency four times the frequency of the input QPSK wave and
And input to the clock terminal of a shift register composed of the D-FF circuits (38a) to (38d).
From d), the reproduced carrier signals are sequentially shifted in phase by 90 ° as shown in (b1), (b2), (b3), and (b4) and output. Then, as shown in (i1) and (i2), signals with phases shifted by 90 ° and 180 ° are transmitted as clocks for extracting data information to the CK terminals of the D-FF circuits (36a) and (36b). Can be These clocks (i1) and (i2) are (38a) and (38b) themselves shown in (b1) and (b2), respectively. Reproduced carriers shown in (b1), (b2), (b3), and (b4) of the four D-FF circuits (38a) to (38d) are transmitted through a logic circuit (40) to a sawtooth wave generating circuit. The signal is sent to (41), and a sawtooth wave having a phase shift of 90 ° as shown in (c) is generated and sent to the sample and hold circuit (42). In the sample and hold circuit (42), when the time axis of the sample pulse (f) obtained based on the signal from the A / D converter (31) coincides with the time axis of the sawtooth wave (c), When the level is detected and the level is half the amplitude, which is the set intermediate value of the generated sawtooth wave, it is assumed that the phases of the QPSK wave and the reproduced carrier wave match each other. If the phase is delayed, a low voltage is sampled, and if the phase is advanced, a high voltage is sampled. The output voltage of the sample and hold circuit (42) is output to the loop filter circuit (35) and the D / A converter (32). ) To the VCO (24) as a control signal,
The voltage is controlled according to the deviation to advance or delay the phase of the reproduced carrier. Then, the VCO (2
The signal from 4) is added as clock signals for the four D-FF circuits (38a) to (38d). The above operation is repeated until the phase difference becomes 0, and the D-FF circuits (36a) and (36b) output binarized signals (for example, + is set to 1 and-is set to 0), and demodulated. Is sent from the output terminal to the television receiver (10).

If the output of this output terminal is (1,1) respectively, QPSK signal 0 ゜ as (h1), and if (1,0), QPSK signal as (h2)
K signal 90 ゜ and QPSK signal 180 like (h3) for (0,0)
゜ and (0,1) become a QPSK signal 270 よ う as in (h4), and the phase can be determined.

[Effect of the Invention] As described above, the present invention provides an A / D
With the converter interposed, the data information extracting means includes two D
-FF circuit, and the phase shifter includes at least three D-FF circuits.
Mainly the circuit, the phase detector holds the point of coincidence of the time axis between the sawtooth wave generated every π / 2 based on the output of the shift register and the sample pulse that is the phase detection reference point of the QPSK input signal. To detect the level of the sawtooth wave, and when that level is at the set intermediate position of the generated sawtooth wave, QP
Since the output for assuming that the phase of the SK wave and the phase of the reproduced carrier coincide with each other is used as the control signal of the VCO, the circuit portion functioning as the conventional multiplier, LPF, and phase shifter is replaced by the D- It can be composed of an FF circuit, and the processing of the phase detector can be digitally processed.Therefore, it is possible to easily implement the IC, and the operation of extracting the data information and adjusting the phase of the QPSK wave and the reproduced carrier wave can be reliably performed by the digital processing. , Stabilize.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a four-phase demodulation circuit according to the present invention, FIG. 2 is a waveform diagram, FIG. 3 is a block diagram of a four-phase demodulation circuit for digital processing, and FIG. FIG. 5 is a block diagram of a conventional analog processing circuit, and FIG. 5 is a block diagram of a general satellite broadcast receiver. (1) Broadcast satellite, (2) Parabolic antenna,
(3) ... BS converter, (4) ... BS tuner,
(5) Tuning circuit, (6) FM demodulation circuit, (7)
... video-audio separation circuit, (8) ... de-emphasis circuit, (9) ... energy spread signal removal circuit, (10) ...
... TV receiver, (11) ... Video input terminal, (12) ...
Four-phase demodulation circuit, (13), (14) De-emphasis circuit, (15) Audio input terminal, (16) QPSK input terminal, (17) (18) Multiplier, (19) ) (20) ... LPF,
(21) (22) ... binarizer, (23) ... phase difference detector,
(24) VCO, (25) -90 ° phase shifter, (26)
Bit clock recovery circuit, (27) (28) Multiplier,
(29) (30) LPF, (31) A / D converter, (32)
… D / A converter, (33) (34) …… Output terminal, (35)…
Loop filter (40) Logic circuit (41) Sawtooth wave generation circuit (42) Sample hold circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-215158 (JP, A) JP-A-54-80663 (JP, A) JP-A-54-21158 (JP, A) 100548 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 27/00-27/38

Claims (2)

(57) [Claims] 1. A QPSK signal input to a QPSK input terminal is branched into two, and two data information components each having a phase difference of 90 ° are extracted from the QPSK signal by data information extracting means. The component is sent to a demodulation output terminal for data information discrimination, the QPSK signal is sent to a VCO via a phase detector, the signal of this VCO is sent to a phase shifter, and a data information extraction signal is output from the phase shifter. While sending to the data information extracting means, in the feedback to the phase detector that controls the phase difference between the input carrier and the recovered carrier to be 0, A / D conversion after the QPSK input terminal The data information extracting means receives the digital signal of the QPSK input signal as input and sets two reproduced information carrier signals having a phase difference of 90 ° as the data information extracting signal. A D-FF circuit, and the phase shifter operates at least three times using a recovered carrier having a frequency four times the frequency of the carrier from the VCO as a clock.
D-FF circuits, and π / 2
A phase shifter configured to output a signal having a phase difference between the phase shifter and the phase detector, a sawtooth wave generated every π / 2 based on the output of the shift register,
The level of the sawtooth wave is detected by holding the coincidence point of the time axis with the sample pulse serving as the phase detection reference point of the QPSK input signal, and when the level is at the set intermediate position of the generated sawtooth wave, 4. A four-phase demodulation circuit, wherein an output for making the phases of a QPSK wave and a reproduced carrier coincide with each other is used as the VCO control signal. 2. A QPSK signal input to a QPSK input terminal is branched into two, and two data information components each having a phase difference of 90 ° are extracted from the QPSK signal by data information extracting means. The component is sent to a demodulation output terminal for data information discrimination, the QPSK signal is sent to a VCO via a phase detector, the signal of this VCO is sent to a phase shifter, and a data information extraction signal is output from the phase shifter. While sending to the data information extracting means, in the feedback to the phase detector that controls the phase difference between the input carrier and the recovered carrier to be 0, A / D conversion after the QPSK input terminal The data information extracting means receives the digital signal of the QPSK input signal as input and sets two reproduced information carrier signals having a phase difference of 90 ° as the data information extracting signal. A D-FF circuit, and the phase shifter comprises four D-FFs operating with a recovered carrier having a frequency four times the frequency of the carrier from the VCO as a clock.
A shift register configured to output a signal having a phase difference of π / 2 from each D-FF circuit sequentially from each D-FF circuit, and the phase detector detects π / 2 based on the output of the shift register. A sawtooth wave generating circuit for generating a sawtooth wave every time, and holding the coincidence point on the time axis between the sample pulse serving as the phase detection reference point of the QPSK input signal and the sawtooth wave output to reduce the level of the sawtooth wave. When the detected level is half the amplitude of the generated sawtooth wave, the output for assuming that the phases of the QPSK wave and the reproduced carrier wave match each other is output.
A four-phase demodulation circuit comprising a sample-and-hold circuit for controlling a VCO.