JPH10304276A - Receiver for digital satellite broadcast - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a front end compact by selecting either a demodulation and error correcting means corresponding to QPSK modulation or a demodulation and error correction means corresponding to 8PSK modulation, and outputting a demodulated signal and a clock regeneration signal. SOLUTION: An I signal and a Q signal which are outputs of an orthogonal detection means 12 are converted by an A/D converter 26, and carrier reproduction is performed by a digital demodulator 27 in common use for QPSK/8PSK and clock reproduction is performed by a clock regeneration means 29. Error correction or de-interleaving of the demodulated output is performed by an FEC means 28 in common use for QPSK/8PSK, and an error-corrected demodulated output 118 and a clock signal 119 are outputted. An AGC voltage is inputted to the control terminal of a detection means 12 for controlling the amplitude of the I signal and the Q signal being the output of the orthogonal detection means 12. The QPSK and 8PSK demodulation or error correction is selected and processed by the demodulating means 27 and the FEC means 28 according to the result of a modulation system decision means 33 or the information of a modulation system included in the demodulated output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a QPSK modulation system and 8P
The present invention relates to a tuner and digital demodulation suitable for downsizing and stable reception of a digital satellite broadcast receiver capable of receiving different phase modulation schemes in common by performing digital satellite broadcasting using different phase modulation schemes such as the SK modulation scheme.

[0002]

2. Description of the Related Art Different phase modulation methods are used depending on the transmission amount and broadcast contents. For example, in CS satellite digital broadcasting,
While QPSK modulation is used, 8PSK is being considered in satellite digital broadcasting of BS. FIG. 6 shows a main part of a conventional digital satellite broadcast receiver using individual QPSK demodulation means and 8PSK demodulation means. 1 is a high-pass filter, 2 is a preamplifier, 3 is a tunable filter, 4 is an RFAGC amplifier, 5 is a mixer, 6 is a first oscillator, 7 is a frequency synthesizer, 8 is a bandpass filter, 9 is RFAGC control means, 10 is an IF amplifier, 11 is a second oscillator, 12 is a quadrature detection means, 13 is a 90-degree phase shifter, 14 is an IFAGC amplifier, 15A and B are multipliers, 50 is a front end, and 16 is an analog-digital converter. , 17 is QPSK demodulation means, 18 is clock recovery means, 19 is QPSK FEC means, 2
0 is the first digital demodulation means, 21 is an analog-to-digital converter, 22 is 8PSK demodulation means, 23 is clock recovery means, 24
Is an 8PSK FEC means, 25 is a second digital demodulation means, 100 is a high frequency input terminal, 101 is a power terminal of an outdoor unit, 102 is a tuned power terminal, 103 is a clock terminal of a frequency synthesizer, 104 is a data terminal of a frequency synthesizer. , 105 is a power supply terminal, 106 is an AGC control terminal, 107 is an I output signal of a quadrature detector, 108 is a Q output signal of a quadrature detector, 109 is a control signal clock terminal of QPSK digital demodulation means, and 110 is QPSK digital demodulation. Data signal terminal for control signal of means, 111 is output signal of digital demodulation means of QPSK, 112 is reproduced clock output signal of QPSK, 113 is clock terminal for control signal of 8PSK digital demodulation means, 114 is control signal of 8PSK digital demodulation means Data terminal, 115 is the output signal of 8PSK digital demodulation means, 1
16 is 8PSK reproduction clock output signal, 200 is switching means, 1
17 is a control terminal of the selection means, 118 is a selected digital demodulation signal, and 119 is a selected reproduced clock output signal.

A front end 50 receives a digital modulation signal of 1 GHz band from an outdoor unit (not shown) through an input terminal 100, and removes and amplifies unnecessary waves by a high-pass filter 1, a preamplifier 2 and a tunable filter 3. The signal level input to the mixer 5 is adjusted by the RFAGC amplifier 4, and the frequency conversion means including the mixer 5, the first oscillator 6, and the frequency synthesizer 7 controls the receiver microcomputer (not shown).
The desired channel is converted to an intermediate frequency of, for example, 479.5 MHz by the information added to the clock terminal 103 of the frequency synthesizer and the data terminal 104 of the frequency synthesizer, and the output of the mixer 5 is changed to the band-pass filter 8 and the IF amplifier.
The two carrier signals generated by the 90 ° phase shifter 13 from the output of the second oscillator 11 are multiplied by 90 ° different two carrier signals from the output of the second oscillator 11 by multipliers 15A and 15B via The output of I is output from 107 and the output of Q is output from 108.

The I signal 107 obtained from the front end 50
And the Q signal 108 are branched and input to the first digital demodulation means 20 and the second digital demodulation means 25, respectively.

The first digital demodulation means 20 performs QPSK demodulation, and the I signal 107 and the Q signal 108 are digitally converted by an analog-to-digital converter 16 respectively. The carrier is reproduced by the QPSK demodulation means 17 and the clock reproduction means 18 is used. Clock recovery is performed, and the demodulated output is subjected to processing such as error correction and deinterleaving by the FEC unit 19 of QPSK, and the demodulated output 111 and the clock signal 112 that have been corrected are output. AGC information is input to the AGC control terminal 106 of the front end 50 to control the amplitudes of the I signal 107 and the Q signal 108. The first digital demodulation means 20 is controlled by information input to a control signal clock terminal 109 of the QPSK digital demodulation means and a control signal data terminal 110 of the QPSK digital demodulation means from a control microcomputer of the receiver. .

The second digital demodulation means 25 performs QPSK demodulation, and the I signal 107 and the Q signal 108 are digitally converted by the analog-digital converter 21 respectively. Clock recovery is performed, and the demodulated output is subjected to processing such as error correction and deinterleaving by the 8PSK FEC means 23, and an error-corrected demodulated output 115 and clock signal 116 are output. AGC information is input to the AGC control terminal 106 of the front end 50 to control the amplitudes of the I signal 107 and the Q signal 108. The second digital demodulation unit 25 is controlled by information input to a control signal clock terminal 113 of the QPSK digital demodulation unit and a control signal data terminal 114 of the QPSK digital demodulation unit from the control microcomputer of the receiver.

[0007]

However, the above-mentioned conventional example requires two independent sets of analog-to-digital converters, demodulation means, clock recovery means, and FEC means. In order to reduce the size of the circuit block shown in FIG. 6 because it is built into a device or a VTR, the circuit area and the circuit scale are disadvantageous. Also, when signals are transmitted from different satellites using different digital modulation schemes, it is necessary to switch the front-end high-frequency input terminals to the outputs of the two antennas.

An object of the present invention is to provide a tuner suitable for incorporating a digital satellite broadcast receiver into a television receiver or a VTR, and a digital demodulation digital satellite broadcast receiver which solves the above-mentioned disadvantages. To provide.

[0009]

In order to achieve the above object, a digital satellite broadcast receiver according to the present invention uses a common analog-to-digital converter to convert an orthogonal detection output signal from analog-to-digital to nPSK (nPSK). Where n is an integer) and double nPSK
Means for selectively demodulating and recovering the clock and correcting the error, and means for determining whether the received signal is nPSK or double the nPSK based on information contained in the received digitally modulated signal or the demodulated digital signal. A demodulation and error correction means corresponding to nPSK modulation or a demodulation and error correction means corresponding to double nPSK modulation is selectively operated by a control microcomputer of the machine, and a demodulated signal and a clock reproduction signal after error correction are output. In the example of the conventional example, n is 4 and the digital demodulation means converts the quadrature detection output signal from analog to digital by the same demodulation means, and performs QPSK (n = 4) and 8PSK (n = 2 × 4 = 8).
Is selectively demodulated to recover the clock and correct the error. Also, first and second high-frequency input terminals are provided, and the first and second high-frequency input terminals are provided.
The two high-frequency input terminals are connected to antennas, respectively, and the determination result is achieved by interlocking the selection of the first high-frequency input terminal or the second high-frequency input terminal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, the same numbers as those in the other figures indicate the same functional blocks, 26 is an analog-digital converter, 27 is a QPSK / 8PSK shared digital demodulation means, 28 is a QPSK / 8PSK shared FEC means, 29 is a clock recovery means, 30 Is a demodulation / FEC means, 33 is a modulation method determination means, 120 is a clock terminal, 121 data terminal, and 200 is a control microcomputer.

The I signal and the Q signal of the quadrature detection output of the quadrature detection means 12 are digitally converted by an analog-to-digital converter 26, respectively, and carrier recovery is performed by a QPSK / 8PSK shared digital demodulation means 27 and clock recovery by a clock recovery means 29. The demodulated output is subjected to processing such as error correction and deinterleaving by the QPSK / 8PSK shared FEC means 28,
An error-corrected demodulated output 118 and a clock signal 119 are output. Also, an AGC voltage is input to the AGC control terminal of the quadrature detection means 12 in order to control the amplitudes of the I signal and the Q signal of the quadrature detection output of the quadrature detection means 12. The QPSK / 8PSK shared digital demodulation means 27 and the QPSK / 8PSK shared FEC means 28 selectively process QPSK and 8PSK demodulation and error correction based on the result of the modulation scheme determination means 33 or information on the modulation scheme included in the demodulation output 110. In contrast to the conventional example, the present invention is an embodiment in which the analog-digital converter 26 and the digital demodulation means are integrated into the front end 50, and is an example which is effective for incorporating a digital satellite broadcast receiver into a television or VTR. . FIG. 3 is a block diagram showing QPSK / 8PSK demodulation means used in FIG.

31a and 31b are complex multipliers, 32 is an oscillator, 34a and 3
4b is a roll-off filter, 35 is a carrier reproducing means, 36 is an identification means, 37 is a constellation of 8PSK, 38 is a slice reference of 8PSK, 39 is a constellation of QPSK, and 40 is a constellation of QPSK.
SK slice reference, 130 is an I signal of quadrature detection output, 131
Is the Q signal of the quadrature detection output, 132 is the demodulated I signal, 133 is the demodulated Q
Signal. The I signal and the Q signal of the quadrature detection output of the quadrature detection means 12 are digitized by an analog-to-digital converter 26 and input to complex multipliers 31a and 31b, respectively, and the outputs of the complex multipliers are passed through roll-off filters 34a and 34b. The signals are input to the carrier reproduction 35, the clock reproduction 29, and the identification means 36 via the interface.
The output of the carrier reproducing means 35 is fed back to the oscillator 32 to form a Costas loop, and the complex multipliers 31a and 31b perform synchronous detection. The discriminating means has the slice reference 38 of 8PSK or the slice reference 40 of QPSK shown in the figure, and decodes QPSK and 8PSK. The selection of QPSK and 8PSK of the carrier reproducing means 35, the clock reproducing means 29, and the identifying means 36 is performed based on the result of the modulation method determining means 33 shown in FIG. QPSK and 8P by means
The size is reduced by supporting SK.

FIG. 3 is a block diagram showing a digital satellite broadcast receiver according to another embodiment of the present invention. 1a is a first high-pass filter, 1b is a second high-pass filter, 2a is a first high-pass filter.
2b is a second preamplifier, 100a is a first high-frequency input terminal, 100b is a second high-frequency input terminal, and 101a is a second high-frequency input terminal.
1 is an outdoor unit power terminal, 101b is a second outdoor unit power terminal, and 201 is an input switching means. The present invention is different from FIG. 1 in that a second high-frequency input terminal 100b is provided, and switching between the first high-frequency input terminal 100a and the second high-frequency input terminal 100b is performed by the input switching means 201 with the first preamplifier 2a and the second high-frequency input terminal 100b. The input switching means 201 is controlled by a microcomputer for controlling the receiver, and the first high-frequency input terminal 100a and the second high-frequency input terminal 100b are connected to each other by turning on / off the power supply of the preamplifier 2b. Each is selected in association with the reception of the QPSK modulated wave and the reception of the 8PSK modulated wave, and QPSK and 8PSK are determined and selected according to the result of the modulation method determining means 33 or the information on the modulation method included in the demodulation output 110.

This embodiment is also an example in which the size of the digital satellite broadcast receiver can be reduced and incorporated into a television or VTR. FIG. 4 is a block diagram showing a digital satellite broadcast receiver according to another embodiment of the present invention.

Reference numeral 41 denotes a first outdoor unit, 42 denotes a second outdoor unit, 44 denotes decryption means, 45 denotes demultiplexer means, 46 denotes digital expansion means, 47 denotes video signal processing means, 48
Is an audio signal processing means, 140 is a video output terminal, and 141 is an audio output terminal. The signals from the first outdoor unit 41 and the second outdoor unit 42 are respectively connected to the first end of the front end 50.
Input to the high-frequency input terminal and the second high-frequency input terminal of
The demodulated output of the front end is decrypted by the decryption means 44 on the received signal, the desired program is selected by the demultiplexer means 45, and the program information selected by the digital decompression means is decompressed. A video signal output 140 and an audio output 141 are obtained via the 47 and the audio signal processing means 48, respectively. Since the demodulation process corresponding to both QPSK and 8PSK is incorporated in the front end 50, the receiver can be downsized.

FIG. 5 is a block diagram showing the application of the digital satellite broadcast receiver of the present invention to a television.

Reference numeral 49 denotes a digital satellite broadcast receiver, 60 denotes a television, 61 denotes a display means, and 62 denotes a speaker. The digital broadcast receiver 49 shown in FIG. 4 is built in the television 60, and the video output and the audio signal output are connected to the display means and the speaker, respectively. Since demodulation processing for both QPSK and 8PSK is built in the front end 50, the size of the digital satellite broadcasting receiver can be reduced, and this is an example in which the receiver can be easily built into a television.
Although the present embodiment is a television, it is apparent that similar effects can be obtained with a VTR.

[0019]

According to the present invention, a quadrature detection output signal is analog-to-digital converted using a common analog-to-digital converter, and QPSK (where n is an integer) and 8PSK are selectively demodulated to perform clock recovery and error correction. Means for determining whether the received signal is QPSK or 8PSK based on the information contained in the received digitally modulated signal or the demodulated digital signal, and from the determination means, the control microcomputer of the receiver performs demodulation and error corresponding to QPSK modulation. By selectively operating the demodulation and error correction means corresponding to the correction means or 8PSK modulation, and outputting the demodulated signal after error correction and the clock reproduction signal, the digital demodulation means which was conventionally required two sets can be reduced to one set, This is effective for downsizing the front end. Also,
By linking the selection of the first high-frequency input terminal and the second high-frequency input terminal to the determination result, the effect of easily switching the output of the two antennas is obtained even when the signals are transmitted from different satellites in different digital modulation systems. Can be According to the present invention, a compact tuner and digital demodulation suitable for incorporating a digital satellite broadcast receiver into a television receiver, a VTR, or the like can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital satellite broadcast receiver according to one embodiment of the present invention.

FIG. 2 is a block diagram showing QPSK / 8PSK demodulation means used in the present invention.

FIG. 3 is a block diagram showing a digital satellite broadcast receiver according to another embodiment of the present invention.

FIG. 4 is a block diagram showing the application of the digital satellite broadcast receiver of the present invention to a television.

FIG. 5 is a block diagram showing a digital satellite broadcast receiver according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional digital satellite broadcast receiver.

[Explanation of symbols]

1 ... High-pass filter, 2 ... Preamplifier, 3 ... Variable tuning filter, 4 ... RFAGC amplifier, 5 ... Mixer, 6 ... First oscillator, 7 ... Frequency synthesizer, 8 ... Bandpass filter,
9 ... RFAGC control means, 10 ... IF amplifier, 11 ... second oscillator, 1
2… Quadrature detection means, 26… Analog-digital converter, 27…
QPSK / 8PSK shared digital demodulation means, 28 ... QPSK / 8PSK shared FE
C means, 29: clock recovery means, 30: demodulation / FEC means, 31
... complex multiplier, 32 ... oscillator, 33 ... measurement method of modulation method,
34a, 34b: roll-off filter, 35: carrier regeneration means, 36: identification means, 37: 8PSK constellation, 38
… 8PSK slice standard, 39… QPSK constellation, 40… QPSK slice standard, 44… Decryption means, 45…
Demultiplexer means, 46 ... Digital expansion means, 47 ... Video signal processing means, 48 ... Audio signal processing means, 49 ... Digital satellite broadcast receiver, 50 ... Front end, 100a, 100b ...
High frequency input terminal, 130: Quadrature detection I signal input, 131: Quadrature detection Q signal input, 132: Demodulation output, 133: Clock recovery output

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Katsumasa Yokouchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Japan

Claims (9)

[Claims] 1. A frequency conversion means comprising at least a high-frequency input terminal, a first oscillator, a mixer and a variable gain amplifier; a quadrature detection means comprising a second oscillator and a multiplier;
A digital demodulation means for quasi-synchronous detection of the output of the frequency conversion means by the quadrature detection means, wherein the digital demodulation means is a digital satellite broadcasting receiver for generating a carrier signal, error correction and a clock signal; The means is a means for analog-to-digital conversion of the quadrature detection output signal with the same demodulation means, selectively demodulates nPSK (where n is an integer) and twice the nPSK, reproduces the clock, and corrects the error. Received signal is nPSK based on information contained in demodulated digital signal
Has a determination means for determining nPSK of 2 times or more, and performs a demodulation and error correction means corresponding to nPSK modulation or a demodulation and error correction means corresponding to twice nPSK modulation by the determination means, and performs error correction. A digital satellite broadcast receiver which outputs a demodulated signal and a clock reproduction signal. 2. The digital satellite broadcast receiver according to claim 1, wherein n is 4, and said digital demodulation means converts the quadrature detection output signal from analog to digital by the same demodulation means. And a means for selectively demodulating QPSK and 8PSK for clock recovery and error correction. 3. A high frequency input terminal, frequency conversion means comprising a first oscillator, a mixer, and a variable gain amplifier; quadrature detection means comprising a second oscillator and a multiplier;
A digital demodulation means for performing pseudo-synchronous detection of the output of the frequency conversion means by the quadrature detection means, wherein the digital demodulation means is a digital satellite broadcast receiver for generating a carrier signal, error correction and a clock signal. Having a high-frequency input terminal and a second high-frequency input terminal,
The digital demodulation means converts the quadrature detection output signal into an analog signal.
Means for digitally converting and selectively demodulating QPSK and 8PSK for clock recovery and error correction, and determining means for determining whether the received signal is QPSK or 8PSK based on information contained in the received digital modulated signal or demodulated digital signal, The first high-frequency input terminal or the second high-frequency input terminal depends on the result of the determination means.
High-frequency input terminal is selected, and demodulation and error correction corresponding to QPSK modulation or demodulation and error correction corresponding to 8PSK modulation are selectively operated, and a demodulated signal and a clock reproduction signal after error correction are output. Digital satellite broadcasting receiver. 4. The digital satellite broadcast receiver according to claim 1, wherein said frequency conversion means, said quadrature detection means, and said digital demodulation means are arranged in an integrated housing, and A digital satellite broadcast receiver, wherein a digital modulation signal is input and a digital demodulation signal or an error correction output is obtained. 5. The digital satellite broadcast receiver according to claim 1, wherein said quadrature detection means includes a second detector.
A digital satellite broadcast receiver characterized in that the oscillator is a SAW oscillator. 6. The digital satellite broadcast receiver according to claim 3, wherein said 8PSK determination means and demodulation means correspond to trellis-encoded 8PSK determination and demodulation. Digital satellite broadcasting receiver characterized by the above-mentioned. 7. At least channel selection demodulation means, decryption means, demultiplexing means, digital decompression means, video processing means, and audio processing means. 7. A digital satellite broadcast receiver for outputting an audio signal, wherein the channel selecting and demodulating means is the digital satellite broadcast receiver according to any one of claims 1 to 6. 8. A television receiver comprising at least channel selection demodulation means, decryption means, demultiplex means, digital decompression means, video processing means, audio processing means, image display means, and speakers. The television receiver according to claim 1, wherein the channel selection demodulation means is the digital satellite broadcast receiver according to any one of claims 1 to 6. 9. A video recording and reproducing apparatus comprising at least channel selection demodulation means, decryption means, demultiplexing means, digital decompression means, video processing means, audio processing means and video recording and reproduction means. 7. A video recording / reproducing apparatus, wherein the channel selecting / demodulating means is the digital satellite broadcast receiver according to claim 1.