JP2001024721A - Sheared reception equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide small-sized shared reception equipment which receives broadcast signals of satellite broadcasts and the like in analog and digital systems of different types. SOLUTION: A tuner circuit, consisting of a filter 8, gain control circuit 98, mixer circuit 9, local oscillation circuit 10, PLL circuit 11 for channel selection, etc., is shared for reception signals of analog modulation signals and digital modulation signals and an orthogonal detection frequency and an FM demodulation frequency are made identical to share a gain control circuit 12, an IF filter 13 and an oscillation circuit 65 for detection, and further the size and the power consumption of reception equipment are reduced by power control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared receiver, and more particularly, to BPSK (Binary Phase Shift Keying) modulation, QPSK (Quadrature Phase Shift Keying) modulation, 8PSK (8 Phase Shift Keying) modulation, QAM (Q
The present invention relates to a shared receiver that receives a digitally modulated signal such as uadrature amplitude modulation and a broadcast signal that is analog FM modulated.

[0002]

2. Description of the Related Art At present in Japan, analog FM modulation TV broadcasting using broadcasting satellites and 12
Digital TV broadcasting using the QPSK modulation method in the GHz band is performed, and in the future, B
Digital TV broadcasting using SPK modulation, QPSK modulation, and 8PSK modulation is being planned.

[0003] These analog and digital satellite broadcast receivers include, for example, an MSK (Minimum Shift Keying) demodulation circuit described in Japanese Patent Application Laid-Open No. 63-30049, and a document "Compact front end with IC for satellite broadcast tuner" television. John Society Technical Report Vol.14, N0.6, PP.53-58, ROFT'9
As shown in 0-6 (Japan. 1990), it consists of individual receivers.

[0004]

It is anticipated that analog and digital satellite broadcasting will be implemented in a mixed manner in the future, and a shared front-end device capable of receiving a plurality of types of broadcast signals will be realized. In order to keep the demodulation processing of the broadcast signal with good characteristics, it is important to keep the signal amplitude input to the demodulation processing system constant.

It is an object of the present invention to provide a small-sized common receiving apparatus capable of receiving such different types of analog and digital broadcasting signals such as satellite broadcasting.

Another object of the present invention is to provide a shared receiving apparatus capable of economically receiving such different types of analog and digital broadcast signals such as satellite broadcasts.

It is another object of the present invention to provide a shared receiving apparatus capable of receiving broadcast signals of such different types of analog and digital satellite broadcasts with good reception characteristics.

[0008]

One feature of the present invention is that:
PLL type FM having a tuner section and first oscillating means
An analog modulation signal processing system including a demodulation circuit, a digital modulation signal processing system including a quadrature detector having an oscillating means, an A / D converter, and a digitizing demodulation circuit, and control means for controlling these are provided. In the shared receiving device, the tuner unit includes: a quadrature detection frequency of a received digital modulation signal; frequency conversion means for equalizing a demodulation frequency of an analog modulation signal; and at least one gain control circuit. The first and second oscillating means include an oscillator and first and second resonators selectively connected to the oscillator, and the control means switches the first resonator when receiving an analog modulation signal. Selection, the FM demodulation circuit is enabled and the analog modulation signal processing system functions, and when receiving a digital modulation signal, the second resonator is selected and the quadrature detection circuit is selected. , An A / D converter and a digitizing demodulation circuit are enabled to make the digital modulation signal processing system function. When the digital modulation signal is received, the digital modulation signal processing system sets the amplitude of the signal input to the digital modulation signal processing system. Is detected, feedback control is performed on a gain control circuit of the tuner unit, and the amplitude of a signal input to the digital modulation signal processing system is maintained at a constant value.

Another feature of the present invention is that a tuner, first and second detection circuits, a detection oscillation circuit, an A / D converter,
In a shared receiving apparatus including a digitizing demodulation circuit and a control means, the tuner section includes at least one or more gain control circuits, and the detection oscillation circuit is selectively connected to first and second resonance circuits. And the control means, when receiving the analog modulated signal, the one detector and the first detector.
And turns on the power supply to one of the detectors to enable the analog modulation signal processing system and to supply power to the other detector, A / D converter, and digitized demodulation circuit. When the digital modulation signal processing system is turned off and the digital modulation signal is received, the first and second detectors and the second resonance circuit are selected to receive the digital modulation signal, and the first and second detectors, A / D converter, means for turning on the power supply to the digitizing demodulation circuit to enable the digital signal processing system,
When receiving a digitally modulated signal, the digitized demodulation circuit
Detects the amplitude of the signal input to the digital demodulation circuit,
An object of the present invention is to maintain a constant amplitude of a signal input to a digitization demodulation circuit by performing feedback control on a gain control circuit of a tuner unit.

More specifically, the analog modulation signal (F
Input terminal for receiving M modulation) and digital modulation signals (QPSK modulation signals, etc.), means for switching between analog modulation signals and digital modulation signals, means for converting received signals into intermediate frequency signals (IF signals), and selecting desired signals A local oscillation circuit for performing the frequency conversion of the received signal into an IF signal,
Or, gain control means provided in the subsequent stage or both of the preceding and succeeding stages, means for demodulating an analog modulated signal, means for quadrature detecting a digital modulated signal into two signals of I (In-Phase) and Q (Quadrature-Phase), analog demodulation And an oscillation circuit for digital quadrature detection, means for switching the resonance circuit of the oscillation circuit when receiving an analog or digital modulation signal, means for switching power supply when receiving an analog or digital modulation signal, and A / D conversion of I and Q signals Means, demodulation means for demodulating the A / D conversion output, detecting the amplitude of the A / D conversion output, and outputting a signal corresponding to the amplitude, and adjusting the IF signal frequency when receiving the analog modulation signal AFC means, means for sweeping the oscillation frequency of the local oscillation circuit when receiving a digital modulation signal, oscillation frequency control of the local oscillation circuit, analog and digital Control means for switching the respective circuit portions when Le signal reception (microcomputer), the received signal comprises means for determining whether the analog modulation signal or the digital modulation signal.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of an analog / digital shared receiving apparatus according to the present invention. Reference numerals 1 and 2 denote input terminals, reference numerals 3 and 4 denote input signal switching circuits composed of amplifier circuits and the like, reference numeral 7 denotes a control circuit for outputting switching signals 5 and 6, reference numeral 40 denotes a control signal for controlling the control circuit 7, and reference numeral 8 denotes a control signal. A filter circuit for suppressing an interference wave, 98 is a gain control circuit, 9 is a mixer circuit, 10 is a local oscillation circuit, 11 is a PLL circuit for channel selection, 41 is a control signal for controlling the PLL circuit 11, and 12 is a gain. A control circuit, 13 is an intermediate frequency filter (hereinafter, IF filter), 16 is an IF signal switching circuit, and 46 is the IF signal switching circuit 16
, A quadrature detection circuit 17 for quadrature detection of a digital modulation signal and outputting two signals 30 and 31 of I (In Phase) and Q (Quadrature Phase), 22 an A / D converter, 23 Is a digitized demodulation circuit, 24 is a detection signal that detects the amplitude of the demodulation signal and is output from the digitization demodulation circuit 23, 25 is a demodulation output terminal, 18 is a phase detection circuit that performs FM demodulation of the analog modulation signal, and 26 is FM
A detection output terminal, 65 is an oscillation circuit for quadrature detection of a digital modulation signal and a PLL detection for an analog FM modulation signal, 67 is a resonance circuit capable of controlling a resonance frequency by an applied voltage, 68 is a resonance circuit of a fixed frequency, 66 Is the resonance circuit 6
Switching circuit for selectively enabling one of 7, 68,
1 is a control circuit for outputting a switching signal for controlling the switching circuit 66; 42 is a control signal for controlling the control circuit 21; 32 is a frequency demodulation of the IF signal from the FM demodulation signal 49 to output an AFC signal 50 AFC circuit,
33 is an IF from the demodulated signal 47 of the digitized demodulation circuit 23
An AFC circuit that detects a frequency shift of the signal and outputs an AFC signal 51, and 34 is an output signal 5 of the AFC circuits 32 and 33.
A switching circuit for selectively enabling one of 0 and 51;
43 is a control signal for controlling the switching circuit 34;
Are AFC signals output from the switching circuit 34,
8 is a synchronization detection signal for detecting whether or not the digitized demodulation circuit 23 is synchronized; 36 is a fixed signal generation circuit; 64 is an output signal of the fixed signal generation circuit 36; and the digitized demodulation circuit 23 is in a synchronized state. 35, a switching circuit for selectively switching one of the synchronization detection signal 48 and the fixed signal 64 so as to be valid, 44 a control signal for controlling the switching circuit 35, and 100 a synchronous / asynchronous determination circuit. , 101 is a judgment signal output from the judgment circuit 100, 37 is a microcomputer (hereinafter, microcomputer) containing RPM data, 38 is a channel selection device for selecting a broadcast signal desired to be received, 39 is channel selection data, 27 Is a power supply terminal, 71 is a power supply switching circuit, 45 is a control signal for controlling the power supply switching circuit, and 29 is a signal for FM demodulation. Supplying power to the phase detector circuit 18,
Reference numeral 28 denotes a power supply to the quadrature detection circuit 17, the A / D converter 22, and the digitization demodulation circuit 23.

An analog FM-modulated signal (broadcast reception signal of about 1 to 2 GHz band) is input from an input terminal 1, and a digitally-modulated signal (modulation system is, for example, a QPSK system) from an input terminal 2. A broadcast signal of about 1 to 2 GHz band) is input. One of the input analog FM modulation signal or digital modulation signal is selected by input signal switching circuits 3 and 4 operating based on switching signals 5 and 6 output from the control circuit 7.
The selected reception signal is input to the mixer circuit 9 after suppressing and removing the interference wave by the filter circuit 8 and controlling the gain by the gain control (AGC) circuit 98. The mixer circuit 9 mixes the oscillation signal 59 from the local oscillation circuit 10 with the reception signal, converts the frequency into an IF signal (for example, an intermediate frequency of 479.5 MHz), and outputs the IF signal. Here, the local oscillation circuit 10
The oscillation frequency is controlled by data 41 input to the PLL tuning circuit 11, and a signal of a desired broadcasting station is selected (tuned) in the mixer circuit 9. The data 41 is ROM data in the microcomputer 37 and is selectively read out according to tuning data 39 from the channel tuning circuit 38. Here, when the digital modulation signal input from the input terminal 2 is selected and received, the data 41 includes sweep data for sweeping the oscillation frequency of the local oscillation circuit 10.

The IF signal output from the mixer circuit 9 is gain-controlled by a gain control circuit 12,
After extracting the F signal, it is input to the IF signal switching circuit 16. When the received signal is a digitally modulated signal, the IF signal switching circuit 16
7 so that the received signal is
In the case of M modulation, switching is performed so that the IF signal is input to the FM demodulation phase detection circuit 18. This input switching is controlled by control data 46 provided from the microcomputer 37.

Hereinafter, the operation of each of the case where the received signal is a digitally modulated broadcast signal and the case where the received signal is an analog FM modulated broadcast signal will be described in detail.

The case where the received signal is a digitally modulated signal will be described. The digitally modulated signal is detected by the quadrature detection circuit 17 using the oscillation signal from the oscillation circuit 65, output as an I signal 30 and a Q signal 31, and converted into a digital modulation signal by the A / D converter 22. The I and Q digitally modulated signals are subjected to synchronous reproduction, clock reproduction, synchronization detection, error correction and the like in a digitizing demodulation circuit 23, and are output from a demodulation output terminal 25 as digital demodulated signals.

The resonance circuits 67 and 6 connected to the oscillation circuit 65
8 selects a fixed resonance circuit 68 by a switching circuit 66 that operates based on a switching signal 69 output from the control signal generation circuit 21. The control signal generation circuit 21 is controlled by control data 42 from the microcomputer 37.

The digitized demodulation circuit 23 detects the amplitude of the demodulated signal and outputs a detected signal 24.
In addition, the detection signal 24 is fed back to the gain control circuits 98 and 12 as a gain control signal 121 via the switching circuit 120 to perform gain control so as to keep the amplitude of the demodulated signal output constant. Here, the gain control circuit 98 has approximately 1 to 1 input to the input terminals 1 and 2.
The gain control circuit 12 is designed to operate well in the 2 GHz band signal frequency, and the gain control circuit 12 is designed to operate well in the IF frequency band. The same operation is performed even if the replacement is performed. In this description, the gain control signals 24, 1
Reference numeral 21 designates gain control circuits 98 and 12, and AG in the quadrature detection circuit.
Although the description has been given of the configuration in which the signal is fed back to three points of the C circuit, the same applies to the case where the signal is fed back to an arbitrary number of AGC circuits as long as the amplitude of the signal input to the digitizing demodulation circuit 23 is kept constant. The effect of is obtained. The digitizing demodulation circuit 23 outputs a frequency error signal 47 corresponding to the frequency deviation of the IF signal, converts the frequency error signal 47 into an AFC signal 51 by the AFC circuit 33, and then switches the PLL channel selection circuit 11 through the switching circuit 34.
And an AFC circuit is applied to the local oscillation circuit 10 so as to correct the frequency deviation of the IF signal. Furthermore,
The digitized demodulation circuit 23 outputs a synchronization detection signal 48 for detecting whether or not the demodulation circuits are synchronized, inputs the synchronization detection signal 48 to the synchronous / asynchronous determination circuit 100 via the switching circuit 35, and inputs the determination data to the microcomputer 37. To do it.
For example, when the digitized demodulation circuit 23 is in an asynchronous state, the sweep data from the ROM in the microcomputer 37 is superimposed on the tuning data 41 based on the determination data 101, and the PLL tuning circuit 11 is controlled to oscillate the local oscillation circuit 10. The frequency is swept in a minute range (for example, ± 3 MHz), and the digitized demodulation circuit 23 is synchronized. Then, the digitized demodulation circuit 23
Are synchronized, the superimposition of the sweep data is stopped according to the determination data 101.

The power supply voltage from the power supply terminal 27 is supplied to the quadrature detection circuit 17 and A
The power is applied to the / D converter 22 and the digitized demodulation circuit 23, and the power supply 29 of the phase detection circuit 18 is turned off to suppress wasteful power consumption.

Next, the case where the received signal is an analog FM-modulated signal will be described. The analog FM-modulated signal is PLLFM-demodulated by the phase detection circuit 18 and the oscillation circuit 65, and a demodulated signal is output from a terminal 26. At this time, the resonance circuits 67 and 68 connected to the oscillation circuit 65
The variable resonance circuit 67 is selected by the switching circuit 66 that operates based on the switching signal 69 output from the control signal generation circuit 21, and forms a PLL loop that controls the resonance frequency with the FM demodulation signal 49. The control signal generation circuit 21 is controlled by data 42 from the microcomputer 37. The signal input to the phase detection circuit 18 is also input to the level detection circuit 14. The level detection circuit 14 outputs the gain control signal 15 and, via the switching circuit 120,
The gain control circuits 98 and 1 are controlled so that the amplitude of the signal input to the phase detection circuit 18 as the gain control signal 121 becomes constant.
2 is controlled. The switching circuit 120 outputs the gain control signal 24 output from the digitized demodulation circuit 23 as a gain control signal 121 when receiving the digital modulation signal, and the gain control signal 15 output from the level detection circuit 14 when receiving the analog FM modulation signal. Is output by the control signal 122 so as to be output as the gain control signal 121.

The AFC circuit 32 detects a frequency shift of the IF signal based on the FM demodulated signal 49 output from the phase detection circuit 18 and outputs an AFC signal 50. The AFC signal 50 is transmitted to the PLL tuning circuit 1 via the switching circuit 34.
AFC is performed to control the oscillation frequency of the local oscillation circuit 10 so as to correct the frequency deviation of the IF signal. When a broadcast signal modulated by analog FM is received, if the local oscillation circuit 10 is swept, the characteristics will be degraded. Therefore, it is necessary to stop the sweeping. The fixed signal 64 output from the fixed signal generation circuit 36 is switched to the switching circuit 35. To the determination circuit 100 via The determination circuit 100 is in a state where the sweep is stopped in order to always determine that the fixed signal 36 is in a synchronous state.

The power supply voltage from the power supply terminal 27 is applied to the phase detection circuit 18 as a power supply 29 via a switching circuit 71, and the power supply 28 to the quadrature detection circuit 17, the A / D converter 22, and the digitized demodulation circuit 23 Useless power consumption is suppressed in the cutoff state.

The AFC switching circuit 34 selects the AFC signal 51 based on the data 43 when receiving a digitally modulated broadcast signal, and selects the AFC signal 50 when receiving an analog FM modulated broadcast signal. I do. The switching circuit 35 selects the synchronization signal 48 based on the data 44 when receiving the digitally modulated broadcast signal, and selects the fixed signal from the fixed signal generation circuit 36 when receiving the analog FM modulated broadcast signal. Select signal 64.

According to this embodiment, an analog FM modulated broadcast signal and a digitally modulated broadcast signal are received,
Filter circuit 8 for suppressing interference wave, gain control circuit 98, mixer circuit 9, local oscillation circuit 10, PLL circuit 1 for channel selection
1 and the like, and the quadrature detection frequency and the FM demodulation frequency are made equal by the frequency conversion by the mixer circuit 9, so that the gain control circuit 12, the IF filter 13,
By using the detection oscillation circuit 65 in common, the effects of downsizing and low power consumption of the receiving device are obtained, and when the digital modulation broadcast signal is received, the gain control circuit 12,
98 is subjected to feedback control so that the input amplitude value of the digitized demodulation circuit is kept constant and good demodulation characteristics are maintained.

When an analog modulated broadcast signal is received, the frequency deviation of the IF signal is detected from the demodulated signal and AFC is applied to the local oscillation circuit 10. When a digital modulated broadcast signal is received, synchronization is established. Local oscillation circuit 10
To correct the frequency shift of the IF signal, stop AFC when receiving a digitally modulated broadcast signal, and stop sweeping when receiving an analog modulated broadcast signal, so that two types of broadcast signals are not interfered with each other. , Good receiving characteristics can be obtained.

Further, when an analog modulated broadcast signal is received, a digital modulated broadcast signal detection circuit 17, 2,
When receiving the digitally modulated broadcast signal, the power supply of the detection circuit 18 for the analog modulated broadcast signal is cut off when receiving the digitally modulated broadcast signal, thereby obtaining good reception characteristics without interfering with each other and reducing power consumption. The effect of realizing electric power is obtained.

FIG. 2 is a block diagram showing a second embodiment of the analog / digital shared receiving apparatus according to the present invention. Blocks having the same functions as those of the above-described embodiment are denoted by the same reference numerals. Description is omitted. In this embodiment, the detection circuits of the demodulation circuits 17 and 18 are shared, and the detection circuits 90 and 91 are switched and selectively used.

First, reception of a digitally modulated broadcast signal will be described. The IF signal from the IF filter 13 is input to a detection circuit 90 via a switching circuit 95, and is also input to a detection circuit 91 via a phase shifting circuit 105 having the same phase shift amount and loss as the switching circuit 95.
The switching circuit 95 is controlled by the control data 96, and is turned on when the received signal is a digital modulation signal. The oscillation signal 70 from the oscillation circuit 65 is divided into two and supplied to the detection circuits 90 and 91. A part of the oscillation signal 70 is input to the detector 90 via the switching circuit 93 and the 90-degree phase shifter 92. The other part is connected to the detection circuit 9 via the phase shift circuit 111 having the same phase shift amount and loss as the switching circuit 93.
Enter 1 The switching circuit 93 is controlled by control data 94, and is turned on when the received signal is a digital modulation signal.

The detection signals from the detection circuits 90 and 91 are controlled in amplitude by gain control circuits 84 and 85. One detection signal is input to the A / D converter 22 via a buffer circuit 110, and the other detection signal is input to the A / D converter 22. The detected signal is supplied to A /
Input to the D converter 22. The buffer circuit 110 includes:
It is assumed that the switching circuit 80 has the same circuit characteristics as the phase shift amount and the loss. The switching circuit 80 is controlled by data 83,
When the received signal is a digitally modulated signal, a signal 31 is output. The output signal of the A / D converter 22 is input to a digitizing demodulator 23, where it is demodulated and output from a demodulation output terminal 25 as demodulated data. The digitized demodulation device 23
Further, it outputs the gain control signal 24 and returns it to the gain control circuits 84 and 85 via the switching circuit 88. This switching circuit 88 is controlled by control data 87. When the received signal is a digital modulation signal, the gain control signal 24 is selected and output as an output signal 89. When an analog modulation signal is received, a fixed voltage is output. The fixed voltage from the generator 86 is selected and output as an output signal 89.

Next, a case where the received signal is an analog modulated signal will be described. The switching circuit 95 is turned off.
The IF signal output from the F filter 13 is
5, and is input to the detection circuit 91. The switching circuit 93 is turned off, and the oscillation signal 70 from the oscillation circuit 65 is turned off.
Are supplied to the detector 91 via the phase shift circuit 111. An output signal from the detector 91 is a gain control circuit 84 in a fixed gain state at a fixed voltage from a fixed signal generation circuit 86.
Is input to the switching circuit 80 via the. Switching circuit 80
Is controlled by the control data 83 to control the FM detection output terminal 2
6 so that the signal is output from the FM detection output terminal 26 as a demodulated signal. The output signal 97 from the gain control circuit 84 is also input to the switching circuit 81 and forms a PLL loop which is input to the resonance circuit 67 via the switching circuit 81 turned on by the control data 82.

According to this embodiment, an analog-modulated signal and a digital-modulated signal are received, and the interference elimination filter 8, the gain control circuit 98, the mixer circuit 9, the local oscillation circuit 10, the tuning circuit 11 and the like are received. By sharing the tuner circuit and making the orthogonal detection frequency and the FM demodulation frequency the same, the gain control circuit 12, the IF filter 13, the detection oscillation circuit 65, and the detectors 90 and 91 can be shared. This has the effect of reducing the size of the device and reducing power consumption.

FIG. 3 is a block diagram showing a third embodiment of the analog / digital shared receiving apparatus according to the present invention. Blocks having the same functions as those of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted. This embodiment is an example of a receiver that automatically determines whether a received signal is an analog modulation signal or a digital modulation signal and selects a corresponding reception circuit. In this embodiment, the analog modulation signal and the digital modulation signal are separately input from the input terminals 1 and 2. However, the configuration may be modified such that two types of modulation signals are supplied from one input terminal at a time. It is possible. It is also conceivable to change the transmission channel in accordance with diversification of emergency measures and services. In order to cope with a system in which an analog modulation signal and a digital modulation signal are mixed and a change in a transmission channel as described above, a reception method for automatically determining the modulation method of the transmission signal is required. In this embodiment, at the start of reception, a circuit for receiving an analog modulated signal (the demodulation circuit 18,
The resonator 67, the AFC circuit 32, and the signal generating circuit 36) are selected, and the output signal 49 of the demodulating circuit 18 is
02 is input.

If the received signal is a broadcast signal that has been subjected to analog modulation, the synchronization discriminating circuit 102 generates a synchronization signal 103 indicating that the system is in a synchronized state. The microcomputer 37 determines from the synchronization signal 103 that the circuit system is in a configuration state suitable for receiving an analog modulation signal, and continues to select the circuit system. On the other hand, if the received signal is a digitally modulated broadcast signal,
Since the demodulation circuit 18 is not synchronized, the synchronization determination circuit 102
Outputs a signal 103 indicating that the system is in an asynchronous state. The microcomputer 37 determines from the signal 103 that the circuit system is in an incompatible state, and determines a circuit for receiving the digital modulation signal (the quadrature detection circuit 17, the A / D converter, the digitized demodulation circuit 23, the AFC circuit 33, Control for selecting the device 68). The configuration of the synchronization determination circuit 102 is P
A method for determining the synchronization of the PLL loop of the LLFM demodulation circuit, a method for detecting the vertical and horizontal synchronization signals of the demodulated video signal, a method for detecting the frame synchronization signal, and the like can be adopted.

In this description, the case where the synchronization determination circuit 102 is configured to receive the output signal of the demodulation circuit 18 and the circuit for receiving the analog modulated signal is selected at the start of the reception has been described. A signal may be output from the circuit 23 to the synchronization determination circuit, and a circuit for receiving a digital modulation signal may be selected at the start of reception. Also in this case, a method of detecting a frame synchronization signal or the like can be adopted as the configuration of the synchronization determination circuit 102.

According to this embodiment, a circuit system in which an analog modulation signal and a digital modulation signal coexist or a transmission channel change is dealt with by configuring a circuit system which automatically determines and modulates the modulation method of a received signal. Things become possible easily.

FIG. 4 is a block diagram showing a fourth embodiment of the analog / digital shared receiving apparatus according to the present invention. Blocks having the same functions as those of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted. This embodiment is an example in which when a received signal is a digitally modulated signal, the oscillation circuit 65 for detection is controlled by a PLL to form a fixed oscillator.
In this embodiment, reference numeral 106 denotes a PLL control circuit, and 107 denotes a switching circuit. The microcomputer 37 uses the control data 105 to output the signal 4 when receiving an analog modulation signal.
The switching circuit 107 is controlled so as to constitute a PLLFM demodulation circuit that inputs 9 to the resonator 67. When a digital modulation signal is received, the signal 104 is input to the resonator 67 to fix the oscillation frequency of the oscillator 65. The switching circuit 107 is controlled so as to constitute a PLL oscillation circuit.

According to this embodiment, a good oscillation circuit with little change over time can be obtained by applying PLL control to make the oscillation circuit 65 a fixed oscillation circuit. Further, sharing the resonator 67 has the effect of reducing the size of the circuit system.

FIG. 5 is a block diagram showing a fifth embodiment of the analog / digital shared receiving apparatus according to the present invention. Blocks having the same functions as those of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, reference numeral 73 denotes a processing circuit for processing the frequency error signal 47 from the digitizing demodulator 23, and resonator 68 is a variable resonator. In this embodiment, a frequency error signal 47 is transmitted to a resonator 68 through a processing circuit.
This is an example in which a PLL circuit that feeds back a digital signal is configured to expand the synchronous frequency range when receiving a digitally modulated broadcast signal.

FIG. 6 is a block diagram showing a sixth embodiment of the analog / digital shared receiving apparatus according to the present invention. Blocks having the same functions as those of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, 19 is a fixed frequency oscillation circuit, and 20 is a variable frequency oscillation circuit. 58 is a switching circuit. When receiving the analog modulated signal, the microcomputer 37 selects the oscillation circuit 20 and selects the demodulation circuit 18.
When receiving the digital modulation signal and the digital modulation signal, the switching circuit 58 is controlled so that the oscillation circuit 19 is selected and the oscillation signal 54 is supplied to the quadrature detection circuit 17. The switching circuit 58 is a signal 57 for selecting the variable frequency oscillation circuit 20 when receiving the analog modulation signal.
Is controlled by the microcomputer 37 so as to output a signal 58 for selecting the fixed frequency oscillation circuit 19 when receiving the digital modulation signal.

In this embodiment, two oscillation circuits 20 and 21
Is used by switching between reception of the analog modulation signal and reception of the digital modulation signal, whereby an effect of suppressing interference between the analog modulation signal processing circuit and the digital modulation signal processing circuit can be obtained.

FIG. 7 is a block diagram showing a main part of a seventh embodiment of an analog / digital shared receiving apparatus according to the present invention. 1 and 2 are input terminals, 3 and 4 are input switching circuits, and 107 is an R such as a filter or a gain control circuit.
F circuit, 9 is a frequency conversion circuit, 10 is a local oscillation circuit, 1
3 is an IF circuit such as a gain control circuit or an intermediate frequency filter,
7 demodulates the digitally modulated signal to obtain I (In Phase) and Q
(Quadrature Phase) quadrature detection circuit that outputs quadrature detection signals, 22 is an A / D converter, 23 is a digitization demodulation circuit, 25 is a digital signal output terminal, 18 is a demodulation circuit that demodulates an analog modulation signal, and 26 is a demodulation circuit. An analog demodulation signal output terminal, 65 is an oscillation circuit for quadrature detection and FM demodulation detection,
A control circuit 37 controls the oscillation frequency of a detection oscillation circuit or a local oscillation circuit and switching of an analog or digital modulation signal processing circuit.
Reference numeral 9 denotes a shared receiver in which the above circuits are integrated.

This embodiment is a shared receiving apparatus for receiving a first intermediate frequency signal (hereinafter referred to as RF) of analog and digital satellite broadcasting, and receives analog-modulated broadcast signals of approximately 1-2 GHz band from an input terminal 1. A signal is input, and a digitally-modulated broadcast reception signal of about 1 to 2 GHz is input from an input terminal 2, and one of the reception signals is selected by the switching circuits 3 and 4. The selected received signal is RF
The circuit 107 performs signal processing such as interference wave removal and gain control, and the frequency conversion circuit 9 mixes the signal with the oscillation signal from the local oscillation circuit 10 and converts the signal into an IF signal. The IF signal is subjected to gain control, filtering, and the like in the IF circuit 13 and is input to the quadrature detection circuit 17 and the demodulation circuit 18.

When the received signal is a digitally modulated signal, the quadrature detection circuit 17 is selected so as to function effectively, and the received signal is subjected to quadrature detection using the oscillation signal from the oscillation circuit 65.
The signal is output from an output terminal 25 via a / D converter 22 and a digitizing demodulation circuit 23. In the case of an analog modulation signal, the oscillation circuit 6 is selected so that the demodulation circuit 18 functions effectively.
A demodulated signal FM-demodulated with the oscillation signal of No. 5 is output from the output terminal 26. Further, the IC demodulation unit 112 includes the RF circuit 10
7, the AGC circuit in the IF circuit 13, or the AGC circuit in both the RF circuit 107 and the IF circuit 13.
The gain control signal 121 is output to the GC circuit, and feedback control is performed on each gain control circuit so that the amplitude of the input signal to the IC 112 becomes a constant value.

According to this embodiment, an analog-modulated broadcast signal and a digital-modulated broadcast signal are received,
Circuit, a frequency conversion circuit, a local oscillation circuit, and the like, and the tuner circuit 107 is shared. Also, by making the orthogonal detection frequency and the FM demodulation frequency the same, the IF circuit 13 and the detection oscillation circuit can be shared. Digitizing demodulation circuit 23
By integrating the demodulation unit including the above into an IC and integrating it as a receiver, there is an effect that the receiver can be made smaller, more functional, and lower in power consumption.

[0047]

According to the present invention, a filter, a gain control circuit, a mixer circuit, a local oscillation circuit, a tuning PLL circuit, common to received analog and digital modulated signals,
The tuner section with the level detection circuit is shared and processed.
Further, by making the quadrature detection frequency and the FM demodulation frequency the same, the effect of being able to reduce the size of the receiving device is obtained by sharing the IF filter and the detection oscillation circuit.

In addition, when the analog modulation signal is received, the power supply of the digital modulation signal detection circuit is cut off, and when the digital modulation signal is received, the power supply of the analog modulation signal detection circuit is cut off, so that good reception characteristics can be obtained without interfering with each other. And the effect of reducing power consumption can be obtained.

More specifically, when an analog modulation signal is received, the frequency deviation of the IF signal is detected from the demodulated signal and AFC is applied to the local oscillation circuit. When the digital modulation signal is received, the local oscillation circuit is activated until synchronization is established. Sweep to correct the frequency shift of the IF signal.
, And the sweep is stopped when the analog modulated signal is received, whereby good reception characteristics can be obtained without interfering with each other. In addition, by incorporating a circuit unit that automatically determines the modulation method of the received signal, it is possible to easily cope with a system in which an analog modulation signal and a digital modulation signal coexist or a transmission channel change.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an analog / digital shared receiving apparatus according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the analog / digital shared receiving apparatus according to the present invention.

FIG. 3 is a block diagram showing a third embodiment of the analog / digital shared receiving apparatus according to the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the analog / digital shared receiving apparatus according to the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the analog / digital shared receiving apparatus according to the present invention.

FIG. 6 is a block diagram showing a sixth embodiment of the analog / digital shared receiving apparatus according to the present invention.

FIG. 7 is a block diagram showing a seventh embodiment of the analog / digital shared receiving apparatus according to the present invention.

[Explanation of symbols]

1, 2, ... input terminal, 3, 4, ... input switching circuit, 8 ... filter, 12, 98 ... gain control circuit, 9 ... frequency conversion circuit, 10 ... local oscillation circuit , 11 ... PLL circuit, 13 ... IF filter,
14: level detection circuit, 16: switching circuit,
17: Quadrature detection circuit, 18: FM demodulation circuit, 2
2 ... A / D converter, 23 ... digitization demodulation circuit, 25, 26 ... output terminal, 27 ... power supply terminal,
32, 33: AFC circuit, 37: microcomputer, 3
8 ... channel selection circuit, 65 ... oscillation circuit, 6
7, 68 ... resonance circuit, 71 ... power supply switching circuit, 100 ... synchronization discrimination circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C025 BA03 BA16 BA20 DA01 5K004 AA05 AA08 FA03 FA05 FA06 FG02 FH01 FH04 FK13 FK14 JG01 JH03 JJ13

Claims (10)

[Claims] A first oscillator having a tuner section and a first oscillating means;
An analog modulation signal processing system including an LL type FM demodulation circuit, a digital modulation signal processing system including a quadrature detector having an oscillating means, an A / D converter, and a digitization demodulation circuit, and control for controlling these. A tuner section comprising: frequency conversion means for equalizing a quadrature detection frequency of a received digital modulation signal and a quadrature detection frequency of an analog modulation signal; and at least one gain control means. Wherein the first and second oscillating means include an oscillator and first and second resonators selectively connected to the oscillator, and the control means includes a first resonator for receiving an analog modulated signal.
And the FM demodulation circuit is enabled to make the analog modulation signal processing system function. When a digital modulation signal is received, the second resonator is selected and the quadrature detection circuit, A / A Enabling the D converter and the digitized demodulation circuit to function the digital modulation signal processing system, wherein the digital modulation signal processing system has means for detecting the amplitude of a signal input to the digital modulation signal processing system; A shared receiving apparatus, wherein feedback control is performed on a gain control means of the tuner unit so that the amplitude becomes a constant value. 2. The filter according to claim 1, wherein the tuner section includes a filter common to the analog modulation signal and the digital modulation signal.
Gain control circuit, mixer circuit, local oscillation circuit, tuning PL
A shared receiving circuit comprising an L circuit and a level detection circuit. 3. The control means according to claim 1, wherein said control means turns on a power supply to said FM demodulation circuit when receiving an analog modulation signal, and outputs said quadrature detection circuit, an A / D converter, and a digitalization signal. When the power supply to the demodulation circuit is turned off and the digital modulation signal is received, the power supply to the quadrature detection circuit, the A / D converter, and the digitization demodulation circuit is turned on, and the power supply to the FM demodulation circuit is turned off. A shared receiving device that is turned off. 4. A shared receiver comprising a tuner, first and second detection circuits, a detection oscillation circuit, an A / D converter, a digitized demodulation circuit, and control means, wherein the tuner is at least One gain control means, the detection oscillation circuit includes first and second resonance circuits selectively connected, and the control means, when receiving an analog modulation signal, one of the detection circuits and the second resonance circuit. The first resonance circuit is selected, the power supply to one of the detection circuits is turned on to enable the analog modulation signal processing system, and the power supply to the other detector, A / D converter, and digitized demodulation circuit is made. To disable the digital modulation signal processing system, and when receiving the digital modulation signal, select the first and second detectors and the second resonance circuit to select the first and second detectors, A / D converter, digitized demodulation circuit Means for turning on a power supply to the digital modulation signal processing system to enable the digital modulation signal processing system, wherein the digitized demodulation circuit has means for detecting the amplitude of a signal input to the digitized demodulation circuit, and A shared receiving device, wherein feedback control is performed on a gain control means of the tuner unit so as to have a constant value. 5. The shared receiver according to claim 4, wherein said first resonance circuit is a variable resonance circuit for controlling a resonance frequency by an output signal of said second detector. 6. The analog modulation signal processing system according to claim 1, further comprising: a synchronization determination unit configured to determine whether a received signal is an analog modulation signal or a digital modulation signal. A shared receiver, wherein the digital modulation signal processing system is switched. 7. The lPLL according to claim 1, wherein
A shared receiving device comprising a fixed resonance circuit formed by a circuit. 8. The demodulation circuit according to claim 1, wherein the first resonance circuit is a variable resonance circuit for controlling a resonance frequency by an output signal of the FM demodulation circuit, and the second resonance circuit is a digitized demodulation circuit. A shared resonance device which is a variable resonance circuit for controlling a resonance signal with an output signal of the common reception device. 9. The method according to claim 1, further comprising a first oscillation circuit for supplying an oscillation signal to the quadrature detection circuit and a second oscillation circuit for supplying an oscillation signal to the FM demodulation circuit. Sharing receiver. 10. The control system according to claim 1, wherein said tuner section, an FM demodulation circuit, a quadrature detector having a second oscillating means, an A / D converter, and a digitized demodulation circuit are controlled. A shared receiving device, wherein the receiving device is integrated into a single housing.