JP3134801B2 - Shared receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared receiver, and more particularly, to a shared receiver compatible with at least two cellular systems.

[0002]

2. Description of the Related Art A common receiver for receiving digitally modulated signals such as MSK, QPSK, and QAM and analog FM modulated signals is described in, for example, JP-A-8-130490. In the receiver of the same publication, a separate receiving system is provided for each of the digital modulation signal and the analog modulation signal, and the intermediate frequency (IF) band oscillation circuit is shared.

FIG. 3 is a block diagram of a main part of the receiver of the same publication in the 3IF band.

[0004] The digital IF signal is supplied to a quadrature detection circuit 101.
Are subjected to quadrature detection by the first output signal from the oscillation circuit 100, and are converted into I and Q signals.

On the other hand, the analog IF signal is phase-detected by a second output signal from the oscillation circuit 100 in a phase detection circuit 102 and is converted into an FM demodulated signal.

In the case of a digital IF signal, the oscillation circuit 100 is controlled by a signal from a resonance circuit 104 having a fixed frequency via a switching circuit 103 to obtain a first output signal. In the case of an analog IF signal, a second output signal is obtained by being controlled by a signal from a resonance circuit 105 whose resonance frequency can be controlled by an applied voltage.

As described above, by selecting and using two resonance circuits, one oscillation circuit can share analog and digital signals.

[0008]

However, in the conventional shared receiver, an oscillation circuit is required for a CDMA signal that requires a clock of N (N is an integer) times the chip rate of the PN spread sequence synchronized with the received signal. Cannot be shared. Therefore, in a receiver that can be used for both CDMA signals and analog signals, it is necessary to separately provide a synthesizer circuit including a VCO and a PLL circuit. In particular, a clock generation circuit for demodulating a CDMA signal is required. Therefore, the size of the apparatus is increased and the cost is increased.

An object of the present invention is to solve the above-mentioned problems,
It is to provide an improved shared receiver.

It is another object of the present invention to provide an inexpensive shared receiver which can be shared by CDMA signals and analog signals, has a small circuit size, and is inexpensive.

It is still another object of the present invention to provide a shared receiver with high utilization efficiency, as will become clear later.

[0012]

In order to achieve the above object, a shared receiver according to the present invention is a shared receiver capable of receiving at least two types of first and second modulated signals, A first reception signal processing unit that performs signal processing on a first modulation signal; a second reception signal processing unit that performs signal processing on the second modulation signal; and the first and second reception signal processing units. Control means for supplying first and second control signals, respectively, wherein the control means
A local oscillation signal for frequency conversion of the first modulated signal is output as the first control signal to the received signal processing means, and the second modulated signal is output to the second received signal processing means. A clock having an integer multiple of the synchronized clock frequency is output as the second control signal.

It is preferable that the first modulation signal is an analog cellular modulation signal and the second modulation signal is a CDMA modulation signal.

The first received signal processing means is a signal processing means in a second intermediate frequency band of a double superheterodyne receiver, and the second received signal processing means is:
The signal processing means in the first intermediate frequency band of the single superheterodyne receiver is desirable.

[0015] The first control signal is a local signal to a downconverter in the second intermediate frequency band.
Is preferably a clock that is an integral multiple of the chip rate of the spread code sequence used for spreading on the transmitting side.

Further, the shared receiver according to the present invention is compatible with at least two types of first and second cellular systems and has an intermediate frequency band independent of the first and second cellular systems. A single or multi-stage superheterodyne shared receiver having first and second signal processing units, wherein the first signal corresponding to the first cellular system is received; When a local signal for frequency-converting the first signal is supplied to a processing unit and a second signal corresponding to the second cellular system is received, the local signal is transmitted to the second signal processing unit. A clock that is an integral multiple of the clock frequency synchronized with the second signal is supplied.

The first signal processing unit is a signal processing unit in a double superheterodyne system operating in an analog cellular system, and the second signal processing unit is a CDMA system.
It is preferably a signal processing unit in a single superheterodyne system that operates in a system.

The second signal processing unit has quadrature detection means for quadrature detection of the CDMA signal, and demodulation means for demodulating a quadrature detection signal from the quadrature detection means. Preferably, it is supplied to the demodulation means.

The common receiver of the present invention switches between the case of receiving a CDMA signal and the case of receiving an analog signal by a mode switching signal, and changes the frequency setting of the PLL circuit. Thus, in the CDMA mode, a clock N times the chip rate is generated, and in the analog mode, a local signal of the downconverter in the IF stage is generated. As described above, since the synthesizer circuit required for the analog signal demodulation circuit is shared, there is no need to provide a separate synthesizer circuit for generating an N-fold chip rate clock.

[0020]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a receiving circuit of a dual mode cellular terminal of an analog system such as CDMA and FM. The CDMA signal handled here is subjected to CDMA modulation (spread spectrum) on information data on the base station side, and then QP
This is a signal that is subjected to digital modulation such as SK and transmitted.

Reference numeral 1 denotes an antenna, 2 denotes a first band-pass filter, 3 denotes an LNA (low noise amplifier), 4 denotes a second band-pass filter, and 5 denotes a first IF (intermediate frequency) signal for converting a received signal into a first IF (intermediate frequency) signal. A down converter 1 is a switch for separating the first IF signal into a CDMA path and an analog path by a mode switching signal.

Reference numeral 11 denotes a CDMA channel filter for blocking the passage of signals outside the CDMA channel band, and 12 denotes an AGF (Auto Gain Control) for changing the gain according to the input signal level so that the output level becomes constant.
l) The amplifiers 13 and 15 perform quadrature detection of the digital modulation signal by a local signal from an oscillator (not shown),
(Inphase) and Q (Quadra-phas)
e) A quadrature detection circuit that outputs a component signal, 14 and 16 are low-pass filters that block signals outside the CDMA baseband band of the I and Q signals, and 17 is a CDMA signal dropped to the baseband band. C that performs spread demodulation of
DMA demodulation circuit. These circuits constitute a CDMA reception signal processing circuit.

Reference numeral 21 denotes a first analog channel filter for preventing a signal outside the analog signal channel band from passing;
Reference numeral 2 denotes a second downconverter for converting the frequency of the first IF signal into a second IF signal based on a local oscillation signal generated by the shared synthesizer circuit 30, and reference numeral 23 denotes passage of a signal outside the analog signal channel band around the second IF frequency. A second analog channel filter for blocking, 24 is a limiter circuit, and 25 is an analog demodulation circuit for demodulating an analog signal. These circuits constitute an analog reception signal processing circuit.

Numeral 30 includes a VCO 31 and a PLL circuit 32, a shared synthesizer circuit as a control section for outputting a clock or a local oscillation signal having a clock rate N (N is an integer) times the chip rate of the PN spread sequence synchronized with the received signal. Is a VCO capable of outputting N times the chip clock frequency and the frequency of the local oscillation signal supplied to the second down converter 22, 32 is a PLL circuit for changing the frequency setting by a mode switching signal, 41 is a TCXO (temperature compensated crystal oscillator) .

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG.

In both the CDMA mode and the analog mode, a received signal is inputted from the antenna 1, and the first band-pass filter 2, the LNA 3, the second band-pass filter 4
And the frequency is converted to a first IF signal by the first down converter 5. The switch 6 selects the mode at that time by the mode switching signal, and switches between the CDMA path and the analog path.

In the case of the CDMA mode, the CDMA path is selected, and the first IF signal is supplied to the CDMA channel filter 11.
In the interfering wave outside the CDMA channel band is suppressed and removed,
The gain is controlled by the AGC amplifier 12 according to the input signal level so that the output level becomes a constant value, and input to the quadrature detection circuit 13. Quadrature detection circuits 13 and 15 perform quadrature detection on digital modulation such as QPSK and output I and Q component signals.
The low-pass filters 14 and 16 suppress and remove frequency components outside the baseband. The CDMA signal dropped to the baseband is spread and demodulated by the CDMA demodulation circuit 17. At this time, the CDMA demodulation circuit 17 uses N times the chip clock.

Although N may be 1, in this case, since the filtering characteristics of the filter are strictly required, it is preferable to increase the sampling rate of the filter and loosen the filtering characteristics. Therefore, N
Is preferably 4 or 8.

In the case of the analog mode, the analog path is selected, and the first IF signal is suppressed by the first analog channel filter 21 to suppress an interference wave outside the analog signal channel band.
The signal is removed and input to the second down converter 22.
The second down converter 22 is a shared synthesizer circuit 3
0, the first IF signal is converted to the second I
Frequency conversion to F signal. The second IF signal passes through the second analog channel filter 23 and the limiter circuit 24, demodulates the analog signal in the analog demodulation circuit 25, and outputs demodulated data.

The shared synthesizer circuit 30 generates an N-fold chip clock and a local oscillation signal according to each of the CDMA and analog modes. The PLL circuit 32 changes the frequency setting according to the mode switching signal. The frequency setting is N times the chip clock in the CDMA mode, and the second clock in the analog mode.
Is set to a predetermined frequency of the local oscillation signal to be supplied to the down converter 22 of FIG. The output signal of the TCXO 41 controlled to synchronize with the received signal is a VCO as a reference clock.
The output of the PLL circuit 32 is input together with the output of the PLL circuit 31. PL
The L circuit 32 supplies a control voltage to the VCO 31 so that the VCO 31 oscillates at a predetermined frequency. Since the TCXO 41 is synchronized with the received signal, the output of the VCO 31, that is, the output signal of the shared synthesizer circuit 30 is a signal synchronized with the received signal.

The method of synchronizing the TCXO 41 with the received signal is based on, for example, a phase shift of the quadrature detection output, and an automatic frequency control circuit (AFC) is used to eliminate the phase shift.
Can be performed.

The mode switching signal generates a signal for selecting one of them, for example, by an operator. That is, when a receiver is purchased, a setting is made so as to output a switching signal for selecting a receiving system corresponding to the system used by the operator when the receiver is purchased. This setting is preferably performed by a ROM or the like.

If the receiver is compatible with a plurality of systems, the initial setting is set to one of the receiving systems, so that the receiving electric field can not be received due to the timing of the signal to be received. When the level is high, it may be switched to another receiving system.

Further, when a transmission system is provided like a telephone, a switching signal may be supplied so that a reception system corresponding to a system used for transmission is selected.

In the above-described embodiment, two types of receiving systems have been described. However, even with three or more types, the frequency of oscillation may be changed in accordance with a mode switching signal.

In the above embodiment, the single superheterodyne system is used for the CDMA system and the double superheterodyne system is used for the analog system. However, the present invention is not limited to this. Applicable to parts.

In the present invention, the common receiver generates a chip clock used in the CDMA demodulation circuit in the CDMA mode, and generates a local signal to be supplied to the downconverter in the IF stage in the analog mode. Therefore, there is no need to provide a separate synthesizer circuit to generate the chip clock, which contributes to a reduction in the size and cost of the device,
Further, since the synthesizer circuit is used in both the CDMA mode and the analog mode, the utilization efficiency is increased.

Therefore, the common oscillation circuit can be used for detection in both modes, and the local oscillation in the analog mode can be shared with the clock oscillator in the CDMA mode.

[0040]

As described above, according to the present invention, the CD
Since a synthesizer circuit that generates a chip clock used in the MA mode and a synthesizer circuit that generates a local oscillation signal used in another mode called the analog mode are shared, it is necessary to provide a separate synthesizer circuit for generating the chip clock. There is no. Therefore, it is possible to reduce the size and cost of the device, and it is possible to increase the efficiency of use of the circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 antenna 2 first band-pass filter 3 LNA (low noise amplifier) 4 second band-pass filter 5 first down-converter 6 switch 11 CDMA channel filter 12 AGC amplifier 13, 15 quadrature detection circuit 14, 16 low-pass Filter 17 CDMA demodulation circuit 21 First analog channel filter 22 Second down converter 23 Second analog channel filter 24 Limiter circuit 25 Analog demodulation circuit 30 Shared synthesizer circuit 31 VCO 32 PLL circuit 41 TCXO

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04B 1/16-1/26 H04J 13/00 H04L 27/14 H04L 27/22

Claims (3)

(57) [Claims] 1. At least two types of first and second transformations.
A shared receiver capable of receiving a modulated signal , wherein the first received signal processing performs signal processing on the first modulated signal.
Means, and second received signal processing for signal processing the second modulated signal
Means and the first and second received signal processing means, respectively.
Control means for supplying first and second control signals.
For example, the first reception signal processing means, double super hetero
Signal processing means in second intermediate frequency band of Dyne receiver
And the second received signal processing means is a single super
Signal processing method in first intermediate frequency band of Rodyne receiver
Stage, wherein the first control signal is down in the second intermediate frequency band.
The second control signal is a local signal to the converter, and the second control signal is
The clock is an integral multiple of the chip rate of the code sequence, and the control unit sends the first reception signal processing unit the
The local oscillation signal for frequency-converting the first modulation signal is
The second modulated signal is output to the second received signal processing means as the first control signal.
The clock of an integral multiple of the synchronized clock frequency is
Shared reception characterized by outputting as a control signal
Machine. 2. The shared receiver according to claim 1, wherein the first modulation signal is an analog cellular modulation signal, and the second modulation signal is a CDMA modulation signal. 3. At least two types of first and second cells.
Ruler system and the first and second
Independent intermediate frequency for each cellular system
A single antenna having several bands of first and second signal processing units
Or multi-stage superheterodyne configuration
Receiver, wherein the first signal processing unit operates in an analog cellular system.
Signal processing unit in the double super heterodyne system that
And the second signal processing unit operates in a CDMA system.
Signal processing unit in the super-heterodyne system.
Ri, the second signal processing unit, direct the signal of the CDMA system
Orthogonal detection means for performing cross-detection, and direct detection from the orthogonal detection means.
Demodulating means for demodulating the cross-detection signal, and receiving a first signal corresponding to the first cellular system.
When transmitting, the first signal is sent to the first signal processing unit.
A local signal for frequency conversion is supplied, and a second signal corresponding to the second cellular system is received.
The second signal processing means,
Provide a clock that is an integral multiple of the clock frequency synchronized with the signal.
And the clock is supplied to the demodulation means.
Shared receiver.