JP2004343730A - Broadcast signal receiving apparatus and demodulation mode control apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform quicker tuning to a channel of a desired broadcast signal even when a viewer who watches only free broadcasting, or the like does not load a security card into a set-top box. <P>SOLUTION: When it is detected that a security card 200 for storing security information of a broadcast trader and extracting transmission information for receiving a modulated broadcast signal from a control signal from a head end is not loaded in a set-top box 100 configured to load the security card 200 therein, a demodulation mode or/and a frequency for the broadcast signal are changed to search a broadcast channel on which the transmission information of the broadcast signal is transmitted, and the broadcast signal of the broadcast channel is received. When it is decided that a QAM demodulator 12 is synchronized to the broadcast signal, the transmission information of the broadcast channel is extracted from the demodulated broadcast signal, and the broadcast signal is received on the basis of the extracted transmission information of the broadcast signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention controls a broadcast signal receiving apparatus for receiving a broadcast signal such as a cable television (hereinafter referred to as CATV) and a demodulation mode when demodulating a modulated received signal such as the broadcast signal. To a demodulation mode control device.

  2. Description of the Related Art In recent years, digitalization of video has been advanced, and digital broadcasting has been started in various countries on satellite, CATV, and terrestrial broadcast media. Various transmission systems have been proposed as systems suitable for the characteristics of each transmission path. In particular, in CATV, various services such as pay-per-view are provided by utilizing the stability and bidirectionality of the transmission path. In the CATV system according to the prior art, the transmission method including conditional access (CA) is adopted for each network operator, which is a CATV broadcaster, so that the manufacturer conforms to the standard of each network operator. Based on this, we manufacture set-top boxes (STBs) and deliver them to each network operator. On the other hand, a form has been adopted in which a viewer signs a viewing contract with each network operator and then borrows a set-top box from each network operator.

  In such a situation, more than 70% of television viewers receive from CATV, and in North America, to promote the commercialization of CATV set-top boxes, equipment parts that depend on network operators such as conditional access (CA) have been introduced. For example, "OpenCable (registered trademark)", which is a non-patent document 1, is issued by Cable Television Laboratories, Inc. as a standard separated from a CATV set-top box. , Which allows manufacturers to commercialize CATV set-top boxes with television receivers, DVD players or DVD recorders, etc. And consumers will have more choices in products.

  In the set-top box disclosed in Non-Patent Document 1, a security card which stores security information and a control program concerning a network operator and a broadcast signal from the network operator depends on the network operator. Here, the security card is also called a POD module (Point of Deployment Module) or a cable card. When a viewer of this set-top box watches pay broadcasts, the security card generates a descramble key based on the CA information and outputs it to the set-top box by inserting the security card into the set-top box, The set-top box descrambles the data of the pay broadcast signal based on the input descramble key and performs MPEG decoding to obtain video and audio signals.

Cable Television Laboratories, Inc .: "OpenCable (TM) Host Device Core Functional Requirements", Issued Specification, OC-SP-HOST-CFR-I10-020628, pp.1-47, updated on June 28, 2002, http: / /www.opencable.com/specifications/.

  However, viewers who only watch free broadcasts do not always attach a security card to a set-top box, and in that case, there is a problem that it takes a lot of time to select a channel of a broadcast signal.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and a broadcast signal receiving apparatus capable of selecting a desired broadcast signal channel faster even when a viewer who only watches free broadcasts does not mount a security card in a set-top box. And a demodulation mode control device for the broadcast signal receiving device and the like.

A broadcast signal receiving device according to a first aspect of the present invention stores security information of a broadcaster, and transmits transmission information for receiving a broadcast signal modulated in a predetermined modulation mode from a control signal from the broadcaster. A broadcast configured to separate a security device to be extracted from a receiver that receives a broadcast signal from the broadcaster apparatus based on the extracted transmission information, and that the security device can be attached to the receiver. In the signal receiving device,
Tuning means for controlling a frequency of a received broadcast signal to select a predetermined broadcast signal;
In a plurality of demodulation modes corresponding to a modulation mode of a broadcast signal modulation method, it is possible to demodulate a broadcast signal from the broadcaster device, and the demodulation mode is set by the tuning means in the set demodulation mode among the plurality of demodulation modes. Demodulation means for demodulating the selected broadcast signal;
First control means for controlling a demodulation mode of the demodulation means;
Synchronization determining means for determining whether the demodulation means is synchronized with the received broadcast signal and outputting a synchronization determination result signal;
Device detection means for detecting whether or not the security device is mounted on the receiver;
When the device detection unit detects that the security device is not mounted on the receiver, the device controls the channel selection unit, the demodulation unit, and the first control unit to demodulate the broadcast signal. At least one of the mode and the frequency is changed to search for a broadcast channel on which the transmission information of the broadcast signal is transmitted, and the broadcast signal of the searched broadcast channel is received. When it is determined that the broadcast signal is synchronized with the broadcast signal, transmission information of the broadcast channel is extracted from the broadcast signal demodulated by the demodulation means, and a broadcast signal is received based on the extracted broadcast signal transmission information. And control means.

  In the above broadcast signal receiving apparatus, the second control means initializes a demodulation mode control process by the first control means immediately after changing the frequency of the tuning means.

  Further, in the broadcast signal receiving device, the first control means controls the demodulation means based on a synchronization determination result signal from the synchronization determination means until the demodulation means synchronizes with the received broadcast signal. It is characterized in that at least one of the set modulation speed, filter coefficient, and code point arrangement is controlled.

Further, in the broadcast signal receiving device, the demodulation means includes a carrier recovery circuit that reproduces a carrier of the received broadcast signal,
The synchronization determination means determines whether or not the demodulation means is synchronized with a received broadcast signal based on a phase error of a signal reproduced by the carrier reproduction circuit.

Further, in the broadcast signal receiving device, the demodulation means includes a clock recovery circuit that reproduces a clock signal of the received broadcast signal,
The synchronization determination means determines whether or not the demodulation means has synchronized with a received broadcast signal based on a phase error of a clock signal recovered by the clock recovery circuit.

Further, in the broadcast signal receiving device, the demodulation means includes an error correction circuit for correcting an error of the received broadcast signal,
The synchronization determination means determines whether the demodulation means has synchronized with the received broadcast signal based on whether a frame synchronization signal output from the error correction circuit can be detected. .

  Still further, in the above-mentioned broadcast signal receiving apparatus, the first control means and the synchronization determination means are constituted by hardware circuits.

A demodulation mode control device according to a second invention is capable of demodulating a reception signal modulated in a predetermined modulation mode in a plurality of demodulation modes corresponding to a modulation mode of a modulation scheme of the reception signal. Demodulation means for demodulating the received signal in the set demodulation mode,
Control means for controlling a demodulation mode of the demodulation means,
Synchronization determination means for determining whether the demodulation means is synchronized with the received broadcast signal and outputting a synchronization determination result signal,
The control means controls a demodulation mode of the demodulation means based on a synchronization determination result signal from the synchronization determination means until the demodulation means synchronizes with the reception signal.

  Further, in the demodulation mode control device, the control means, based on a synchronization determination result signal from the synchronization determination means, is set in the demodulation means until the demodulation means synchronizes with the reception signal. It is characterized in that at least one of the speed, the filter coefficient, and the code point arrangement is controlled.

Further, in the demodulation mode control device, the demodulation means includes a carrier recovery circuit that reproduces a carrier of the received broadcast signal,
The synchronization determination means determines whether or not the demodulation means is synchronized with a received broadcast signal based on a phase error of a signal reproduced by the carrier reproduction circuit.

Further, in the demodulation mode control device, the demodulation means includes a clock recovery circuit that reproduces a clock signal of the received broadcast signal,
The synchronization determination means determines whether or not the demodulation means has synchronized with a received broadcast signal based on a phase error of a clock signal recovered by the clock recovery circuit.

Further, in the demodulation mode control device, the demodulation means includes an error correction circuit for correcting an error of the received broadcast signal,
The synchronization determination means determines whether the demodulation means has synchronized with the received broadcast signal based on whether a frame synchronization signal output from the error correction circuit can be detected. .

  Still further, in the demodulation mode control device, the control means and the synchronization determination means are configured by a hardware circuit.

  According to the broadcast signal receiving apparatus of the present invention, when the device detecting means detects that the security device is not mounted on the receiver, the channel selecting means, the demodulating means, and the first control Controlling the means to change at least one of a demodulation mode and a frequency of the broadcast signal to search for a broadcast channel on which transmission information of the broadcast signal is transmitted; Receiving, when the synchronization determining unit determines that the demodulation unit is synchronized with the broadcast signal, extracts transmission information of the broadcast channel from the broadcast signal demodulated by the demodulation unit, and transmits the extracted broadcast signal. It controls to receive a broadcast signal based on the information. Therefore, even if a viewer who only watches free broadcasts does not attach the security card to the set-top box, the desired broadcast signal channel can be selected more quickly.

  Further, according to the demodulation mode control device according to the present invention, the demodulation mode of the demodulation unit is controlled based on the synchronization determination result signal from the synchronization determination unit until the demodulation unit synchronizes with the reception signal. Therefore, it is possible to detect and control the demodulation mode of the received signal at a higher speed and more reliably than in the prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components are denoted by the same reference numerals.

  FIG. 1 is a block diagram showing a configuration of a set-top box 100 and a security card 200 for receiving a CATV broadcast signal according to an embodiment of the present invention. In the slot 200S of the set-top box 100 according to the present embodiment, security information on a broadcast signal transmitted from a CATV broadcaster and its headend device is stored, and broadcast is performed from a control signal from the headend device of the broadcaster. A security card 200, which is a security device storing a control program for extracting transmission information for receiving a channel signal, is mounted. Here, the security card 200 is also referred to as a network operator dependent module (Point of Deployment Module) in order to execute signal processing depending on a broadcaster.

  In FIG. 1, a set-top box 100 includes an RF terminal 10, a QAM tuner 11, a QAM demodulator 12, a demodulation mode controller 17, a synchronization determination circuit 16, a tuner frequency controller 18, a QPSK tuner 13, and a QPSK tuner. The demodulator 14 includes a demodulator 14, a QPSK modulator 15, a switch 20, an MPEG (Moving Picture Experts Group) decoder 21, a descrambler 22, and a device controller 23 having a data memory 23m. In particular, the set-top box 100 according to the present embodiment includes a demodulation mode controller 17 for controlling the demodulation mode of the QAM demodulator 12, and a synchronization determination circuit for performing a synchronization determination based on an output signal from the QAM demodulator 12. 16 and a tuner frequency controller 18 for controlling the tuning frequency of the QAM tuner 11.

  In FIG. 1, signals input and output via the RF terminal 10 are roughly classified into the following three types of channel signals, and bidirectional service is possible. The signals of these three types of channels are transmitted while being divided into frequency bands shown in FIG.

  In FIG. 9, a first channel is a frequency band from 54 MHz to 864 MHz, a frequency band per channel is 6 MHz, and is a channel for transmitting broadcast signals related to applications such as video and audio, and a FAT channel. (Forward Application Transport channel), and the broadcast signal is modulated by a 256 QAM or 64 QAM digital modulation method. The second channel has a frequency band of 70 MHz to 130 MHz, a frequency band per channel of 1 MHz to 2 MHz, and SI (Service Information) information for selecting a FAT channel and conditional access (CA). A channel for transmitting information, which is called an FDC channel (Forward Data Channel), and the control signal is digitally modulated by QPSK. Further, the third channel has a frequency band of 5 MHz to 42 MHz, and the frequency band per channel is 1 MHz to 2 MHz. For example, the third channel is for transmitting request information from a broadcast signal receiving device such as a set-top box to a head end. The channel is called an RDC channel (Reverse Data Channel), and the control signal is digitally modulated by QPSK.

  Next, the signal processing for each of the three types of signals input and output via the RF terminal 10 will be described below.

  After the broadcast signal of the FAT channel is input via the RF terminal 10, the QAM tuner 11 outputs only one desired broadcast signal among a plurality of QAM-modulated broadcast signals existing in a frequency band from 54 MHz to 864 MHz. Is extracted and output to the QAM demodulator 12. The QAM demodulator 12 is capable of demodulating a broadcast signal received in a plurality of demodulation modes corresponding to a modulation scheme of a modulated broadcast signal. After performing processing such as control, carrier wave reproduction, waveform equalization, and error correction, the FAT data is demodulated in a demodulation mode of a demodulation method corresponding to a broadcast signal modulation method, and then output to the switch 20. Here, the switch 20 is controlled by the device controller 23 to be selectively switched to the contact a side or the contact b side. When the security card 200 is installed in the slot 200S of the set-top box 100, the switch 20 is switched to the contact b side, and the FAT data from the QAM demodulator 12 is output to the security card 20. On the other hand, when the security card 200 is not installed in the slot 200S of the set-top box 100, the switch 20 is switched to the contact a side, and the FAT data from the QAM demodulator 12 is output to the MPEG decoder 21.

  When the security card 200 is inserted in the slot 200S of the set-top box 100, the security card 200 generates a descramble key based on the CA information extracted from the FDC data or the FAT data, and generates a descrambling key. The descrambler 22 descrambles the paid FAT data based on the descrambling key, and then outputs the descrambled FAT data to the MPEG decoder 21. The MPEG decoder 21 reproduces and outputs video and audio signals by performing MPEG decoding on FAT data input from the switch 20 or FAT data input from the descrambler 22. When the security card 200 is not inserted into the slot 200S of the set-top box 100, the switch 20 is switched to the contact a side, and the FAT data from the QAM demodulator 12 is input to the MPEG decoder 21 and the FAT When the data is not scrambled, the MPEG decoding process is executed.

  The FDC data is input to the QPSK tuner 13 via the RF terminal 10. The QPSK tuner 13 extracts a control signal of QPSK modulation in a frequency band from 70 MHz to 130 MHz and outputs the control signal to the QPSK demodulator 14. The QPSK demodulator 14 performs processing such as clock recovery, automatic gain control, carrier recovery, waveform equalization, and differential decoding on the input QPSK modulation control signal to demodulate the FDC data, and then performs Output to 200. In response, security card 200 extracts SI (Service Information) information and CA (conditional access) information for selecting a FAT channel based on the FDC data output from QPSK demodulator 14.

  The RDC data is generated by the security card 200 and then input to the QPSK modulator 15. The QPSK modulator 15 performs QPSK modulation according to the input RDC data, generates a modulated control signal, and sends the modulated control signal to the QPSK tuner 13. Output. Next, the QPSK tuner 13 frequency-converts the input control signal into a frequency band from 5 MHz to 42 MHz, and sends the frequency-converted control signal via the RF terminal 10 to the head end device of the broadcaster. Send.

  FIG. 2 is a block diagram showing the configurations of the QAM demodulator 12, the demodulation mode controller 17 and the synchronization determination circuit 16 of FIG. 2, the QAM demodulator 12 includes an input terminal 120, a clock recovery and sampling circuit 121, a roll-off filter 122, a carrier recovery and waveform equalization circuit 123, an error correction circuit 124, and an output terminal 125. It is configured with. The demodulation mode controller 17 includes a baud rate controller 170, a filter coefficient controller 171, a code point arrangement controller 172, and a controller 173.

  First, the basic operation of the QAM demodulator 12 will be described. The QAM modulation signal input via the input terminal 120 is first input to the clock recovery and sampling circuit 121, which performs phase synchronization with the modulation clock of the received QAM modulation signal at a predetermined baud rate. The reproduced clock signal is reproduced, that is, a clock signal that allows the QAM modulated signal to be sampled at the QAM code point is reproduced, and the input QAM modulated signal is sampled based on the reproduced clock signal, and then the sampled signal is sampled. The QAM modulation signal is output to a carrier recovery and waveform equalization circuit 123 via a roll-off filter 122 that limits the band with a predetermined roll-off coefficient. Next, the carrier reproduction and waveform equalization circuit 123 reproduces a carrier that is phase-synchronized with the carrier of the input QAM modulation signal using a code point arrangement of a predetermined modulation scheme, and inputs the carrier based on the reproduced carrier. After removing the phase and frequency shifts of the QAM modulation signal and the reflection components included in the input QAM modulation signal, the output signal is output to the error correction circuit 124. Further, the error correction circuit 124 decodes the error correction code coded on the transmission side with respect to the input output signal of the carrier wave recovery and waveform equalization circuit 123, so that the bit error caused by the noise on the transmission path or the like is obtained. Is corrected, and the data after the error correction is output as FAT data via the output terminal 125.

  Next, the demodulation mode control processing will be described below.

  The baud rate controller 170 is controlled by the controller 173 and is connected to the clock recovery and sampling unit 121 of the QAM demodulator 12 and receives the clock recovery and sampling unit 121 as an initial value of a phase locked loop for performing clock recovery. A baud rate corresponding to a QAM modulated signal that is likely to be generated is set. Clock recovery and sampling section 121 recovers the clock signal by calculating the error between the set baud rate and the baud rate of the received QAM modulated signal.

  The filter coefficient controller 171 is controlled by the controller 173, is connected to the roll-off filter 122 of the QAM demodulator 12, and supplies the roll-off filter 122 with a filter coefficient corresponding to a QAM modulation signal that may be received. Set. Further, the code point arrangement controller 172 is controlled by the controller 173 and is connected to the carrier recovery and waveform equalization circuit 123 of the QAM demodulator 12, and the possibility of reception to the carrier recovery and waveform equalization circuit 123. Of an ideal code point constellation (constellation) corresponding to a QAM modulated signal having a certain value. The carrier recovery and waveform equalization circuit 123 performs a carrier recovery and waveform equalization process by calculating an error between the set ideal code point arrangement and the code point arrangement of the received QAM modulated signal.

  The synchronization determination circuit 16 determines whether a synchronization signal (unique word) of a specific frame in the transmission frame of the QAM modulated signal can be detected based on the output signal from the error correction circuit 124 of the QAM demodulator 12. It is determined whether or not the QAM demodulator 12 has been able to synchronize with the received QAM modulated signal, and outputs a synchronization determination result signal to the controller 173, the tuner frequency controller 18, and the device controller 23.

  The controller 173 controls the baud rate controller 170, the filter coefficient controller 171, and the code point arrangement controller 172 based on the synchronization determination result signal of the QAM demodulator 12 output from the synchronization determination circuit 16. For example, when the demodulation mode for the QAM modulated signal that may be received has a plurality of demodulation modes MODE in the demodulation mode table of FIG. 3 stored in the data memory 23m, for example, A baud rate (in the present invention, not limited to a baud rate, but a modulated broadcast signal such as a symbol rate) corresponding to a demodulation method of a demodulation mode MODE = 0 (refers to a demodulation method corresponding to a modulation method of a modulated broadcast signal). A modulation rate corresponding to the signal modulation method may be used, and the same applies to the following.), The code point arrangement corresponding to the roll-off coefficient and the modulation format is determined by using the clock recovery and sampling circuit 121 of the QAM demodulator 12 and the roll-off. After setting in each of the filter 122 and the carrier recovery and waveform equalization circuit 123, a certain time When the QAM demodulator 12 cannot synchronize with the input signal, it corresponds to a setting different from the previously set one, for example, a baud rate, a roll-off coefficient, and a modulation format corresponding to the demodulation mode of the demodulation mode MODE = 1. The baud rate controller 170, the filter coefficient controller 171 and the code point arrangement controller 172 are instructed to switch to the code point arrangement.

  As described above, since the demodulation mode is detected and controlled based on the synchronization result of the QAM demodulator 12, high-speed and reliable control of the demodulation mode can be performed.

  In the synchronization determination circuit 16, the QAM demodulator 12 is in a synchronization state based on whether or not a specific frame synchronization signal (unique word) in a transmission frame can be detected based on an output signal from the error correction circuit 124. Although it is determined whether or not the synchronization is determined, another method may be used as a synchronization determination method, which will be described later in detail.

  FIG. 4 is a flowchart showing an initial operation process executed by the device controller 23 of FIG. The initial operation processing is executed, for example, when the set-top box 100 is initially installed or when the power is turned on. In FIG. 4, first, in step S1, it is determined whether or not the security card 200 is inserted in the slot 200S. When YES, the process proceeds to step S2, and when NO, the process proceeds to step S3. In step S2, after performing the FAT channel transmission information acquisition processing of FIG. 5, the initial operation processing ends. In step S3, after performing the FAT channel search processing of FIG. 6, the initial operation processing ends.

  FIG. 5 is a flowchart showing the FAT channel transmission information acquisition processing (step S2) which is a subroutine of FIG. To select a FAT channel, it is necessary to know at which frequency in the frequency band from 54 MHz to 864 MHz and which modulation method is used. The SI information is transmitted as FDC data as information for that purpose. Before the set-top box 100 selects a FAT channel, the security card 200 controls the set-top box 100 as an initial operation to transmit the FAT channel. Extract information from the FDC channel.

  In FIG. 5, first, in step S11, an FDC channel, which is the frequency of FDC data, is searched from the frequency band of 70 MHz to 130 MHz. In step S12, SI information is obtained from the searched FDC data. In step S13, the SI information is obtained. The transmission information of the FAT channel is extracted from the obtained SI information. Further, in step S14, the obtained FAT channel transmission information is transmitted to the device controller 23 of the set-top box 100, and the process returns to the original main routine. By executing the processing of FIG. 5, it becomes possible to receive the FAT channel thereafter.

FIG. 6 is a flowchart showing the FAT channel search process (step S3) which is a subroutine of FIG. Here, the channel number of a frequency in the FAT channel and _{f n,} the channel number _{f n} is assumed to be from 1 to _{f max.}

6, first, in step S21, the device controller 23 issues a command to the tuner frequency controller 18 to set the tuning frequency of the QAM tuner 11 to a certain initial frequency. In other words, it initializes the channel number _{f n} to 1. Next, when the frequency setting of the QAM tuner is completed, in step S22, the device controller 23 sets the demodulation mode MODE of the QAM demodulator 12 to 0 via the demodulation mode controller 17 for the QAM demodulator 12. That is, the demodulation mode MODE is initialized to zero. Further, in step S23, the synchronization determination circuit 16 determines whether the QAM demodulator 12 has synchronized. If the determination is YES, the process proceeds to step S24. If the determination is NO, the process proceeds to step S31. In step S31, the device controller 23 increments the standby demodulation mode MODE of the QAM demodulator 12 by 1 to the QAM demodulator 12 via the demodulation mode controller 17, and determines in step S32 whether the modulation mode has become 2 or more. If YES, the process proceeds to step S33, while if NO, the process returns to step S23 to execute the process of step S23. Furthermore, in step S33, and increments the channel number _{f n,} the channel number _{f n} is whether it is greater than the maximum channel number _{f max} is determined in the step S34, whereas the process proceeds to step S35 when YES, the If NO, the process returns to step S22. In step S35, an error process is executed, and information such as the presence / absence of each channel obtained in the channel search executed so far and the demodulation system corresponding to the modulation system that can be synchronized is stored in the data memory 23m. Thereafter, the process returns to the original main routine.

  Next, in step S24, the transmission information of the FAT channel is acquired from the FAT data, and it is determined whether or not the transmission information of the FAT channel has been acquired in step S25. If YES, the process proceeds to step S26, while if NO, Proceed to step S33. Further, in step S26, the transmission information of the FAT channel is stored in the data memory 23m in the device controller 23, the FAT channel signal is received based on the acquired transmission information of the FAT channel, and the process returns to the original main routine.

  As described above, even when the security card 200 is not inserted into the slot 200S of the set-top box 100, such as a viewer who only watches free broadcasts, the set-top box 100 performs the initial operation shown in FIG. By executing the processing, FAT channel transmission information can be obtained, and thereafter, a desired FAT channel can be quickly and efficiently selected from a plurality of FAT channels in a frequency band from 54 MHz to 864 MHz.

  In the above embodiment, the contents of the demodulation mode table in FIG. 3 are merely examples, and other various baud rates (or modulation rates such as a symbol rate) and roll-off coefficients can be used. Further, although only two demodulation modes are described in the demodulation mode table of FIG. 3, until the synchronization of the QAM demodulator 12 is established, the code point arrangement of the modulation scheme, the modulation speed such as the baud rate, and the roll-off coefficient May be individually controlled. Until the QAM demodulator 12 establishes synchronization, it may be controlled to at least one of a code point arrangement of a modulation scheme, a modulation speed such as a baud rate, and a roll-off coefficient.

  In the above embodiment, the demodulation mode controller 17, the synchronization determination circuit 16, and the tuner frequency controller 18 are configured by hardware circuits, but may be configured by software using an MPU or DSP, for example. However, when these circuits are configured by hardware circuits, the communication time of the device controller 23 can be reduced, and the processing can be executed at higher speed.

  FIG. 7 is a block diagram showing the configurations of the carrier recovery circuit 123A and the synchronization determination circuit 16A according to the first modification of the present invention. The first modification is characterized in that synchronization determination is performed based on a phase error after carrier wave reproduction. 7, the carrier recovery circuit 123A includes a complex multiplier 51, a phase error detector 52, a low-pass filter (LPF) 53, and a numerically controlled oscillator (NCO) 54.

  In FIG. 7, the digital modulation signal whose waveform has been shaped by the roll-off filter 122 is input to the complex multiplier 51. The digital modulation signal (hereinafter, referred to as an input signal) Sin has a frequency error (or frequency shift) Δω and a phase error (or phase shift) Δθ remaining, and the input signal Sin on the IQ axes orthogonal to each other. If the in-phase signal component of the I-axis at S is S i and the quadrature signal component of the Q-axis is S q, the following equation is obtained.

[Equation 1]
Sin = (Si + jSq) · exp (j (Δωt + Δθ)) (1)

On the other hand, the numerical control oscillator 54 is a signal of a conjugated relationship with the carrier signal exp of the input signal Sin (j (Δωt + Δθ) ) represented by the formula (1), a complex multiplier an oscillation signal _{S NCO} expressed by the following formula 51.

[Equation 2]
S _NCO = exp (−j (Δωt + Δθ)) (2)

Next, the complex multiplier 51 performs a complex multiplication of the oscillation signal S _NCO from the numerically controlled oscillator 54 and the input signal Sin to obtain the frequency error Δω and the phase error of the input signal Sin as shown in Expression (3). Δθ is removed, and a demodulated signal Sout = (Si + jSq) is output.

[Equation 3]
Sout
= (Si + jSq) · exp (j (Δωt + Δθ)) · exp (−j (Δωt + Δθ))
= (Si + jSq) (3)

On the other hand, the demodulated signal Sout from the complex multiplier 51 is also input to the phase error detector 52, and the phase error detector 52 outputs the demodulated signal based on the control signal indicating the code point arrangement from the code point arrangement controller 172. The phase error of the digital modulation signal received by the real part Si and the imaginary part Sq of Sout is detected. The output signal from the phase error detector 52 is input to a low-pass filter 53 which is a loop filter, whereby high-frequency components of the phase error are removed, and input to a numerically controlled oscillator 54 as a control signal. Then, the oscillation signal S _NCO from numerically controlled oscillator 1234 which is controlled by the output signal from the low-pass filter 53 is supplied to a complex multiplier 51.

By the way, as shown in Expressions (1) and (2), when the oscillation signal S _NCO from the numerically controlled oscillator 54 and the carrier signal of the input signal Sin have a conjugate relationship, that is, the frequency error Δω and the phase error Δθ. Is not present, the phase error detected by the phase error detector 52 is 0. However, if there is a phase difference between the above equations (1) and (2), the phase error And outputs the corresponding voltage to the numerically controlled oscillator 54 via the low-pass filter 53.

  Note that the synchronization determination circuit 16A time-averages the output signal indicating the phase error from the phase error detector 52, compares the averaged phase error with a predetermined threshold, and If it is smaller, it is determined that synchronization has been achieved, and the synchronization determination result signal is output to the demodulation mode controller 17, tuner frequency controller 18 and device controller 23 of FIG.

  In the carrier recovery circuit 123A of FIG. 7, since the negative feedback control loop is configured to cancel the phase error detected by the phase error detector 52, the carrier phase-synchronized with the received digital modulation signal is numerically controlled. It will be reproduced by the oscillator 54. The reproduced carrier has a conjugate relationship with the carrier of the input signal Sin, and has no frequency error Δω and phase error Δθ, so that a correct demodulated signal can be obtained.

  By the way, when the code point arrangement indicated by the control signal output from the code point arrangement controller 172 matches the received digital modulation signal, the phase error detector 52 can accurately detect the phase error, and Since the negative feedback control loop works so as to cancel the error, the phase error is finally stabilized in a state where the phase error detected by the phase error detector 52 becomes zero. However, if the code point arrangement indicated by the control signal output from the code point arrangement controller 172 does not match the received digital modulation signal, an accurate phase error cannot be detected, so that the negative feedback control loop operates normally. Therefore, a state where the phase error is not stable, that is, a state where the phase error does not become 0 continues.

  FIG. 8 is a block diagram showing a configuration of a clock recovery and sampling circuit 121A and a synchronization determination circuit 16B according to a second modification of the present invention. The second modification is characterized in that synchronization determination is performed based on the phase error detected by the clock recovery and sampling circuit 121A. 8, the clock recovery and sampling circuit 121A includes a sampling circuit 61, a phase error detector 62, a low-pass filter (LPF) 63 as a loop filter, and a sampling timing signal generation circuit 64. You.

  8, the digital modulation signal input to the input terminal 120 of FIG. 2 is input to the sampling circuit 61, and the input digital modulation signal is one modulated signal tuned and extracted by the QAM tuner 11 of FIG. Are signals that have been A / D converted by an A / D converter (not shown) at the last stage in the QAM tuner 11. Since the sampling timing at the time of A / D conversion in the A / D converter is not the timing including the code point of the received digital modulation signal, the sampling circuit 61 is output from the sampling timing signal generation circuit 64. Based on the sampling timing signal, the input digital modulation signal is subjected to interpolation processing so as to obtain its code point, and clock reproduction and sampling processing are performed. The output signal from the sampling circuit 61 sampled so as to include the code point of the digital modulation signal input to the sampling circuit 61 in this way is output to the subsequent roll-off filter 122 shown in FIG. Output to the phase error detector 62. Next, the phase error detector 62 detects a sampling phase shift (error) with respect to the digital modulation signal output from the sampling circuit 61 and outputs a voltage corresponding thereto via the low-pass filter 63 to the sampling timing signal. The sampling timing signal generation circuit 64 generates a sampling timing signal based on the voltage of the phase error of the sampling timing so that it becomes 0, and outputs it to the sampling circuit 61 in response to the output. .

  Note that the synchronization determination circuit 16B averages the voltage indicating the phase error of the sampling timing output from the phase error detector 62 over time, compares the averaged phase error with a predetermined threshold value, and If it is smaller than the threshold value, it is determined that synchronization has been achieved, and the synchronization determination result signal is output to the demodulation mode controller 17, tuner frequency controller 18 and device controller 23.

  By the way, if the code point timing generated by the sampling timing signal generation circuit 64 includes the code point of the input digital modulation signal, the phase error of the sampling timing detected by the phase error detector 62 becomes zero. Is the code point timing of the sampling timing signal output from the sampling timing signal generation circuit 64, and if the input digital modulation signal does not include the code point, the phase error detector 62 detects the phase error. Output.

  In the clock recovery and sampling circuit 121A of FIG. 8, since the negative feedback control loop is configured to cancel the phase error of the sampling timing detected by the phase error detector 62, the code point of the received digital modulation signal Is reproduced and generated by the sampling timing signal generation circuit 64. Since the reproduced timing signal has a timing including the code point of the input digital modulation signal, a correct code point can be obtained.

  By the way, if the baud rate indicated by the control signal output from the baud rate controller 170 to the sampling timing signal generation circuit 64 is adapted to the baud rate of the received digital modulation signal, the phase error detector 62 determines the phase of the clock signal. Since the error can be accurately detected and the negative feedback control loop operates to cancel the phase error, the phase error finally detected by the phase error detector 62 stabilizes to become zero. However, unless the baud rate indicated by the control signal output from the baud rate controller 170 to the sampling timing signal generation circuit 64 does not correspond to the received digital modulation signal, an accurate timing phase error cannot be detected. A state in which the loop does not operate normally and is not stable forever, that is, a state in which the phase error does not become 0 continues.

  In the above-described embodiment, an example has been described in which the control of the demodulation mode is applied to the set-top box 100 that receives a CATV broadcast signal. However, the present invention is not limited to this, and is not limited to wired or wireless. The present invention can be applied to control of a demodulation mode for a digital modulation signal received via a transmission medium.

FIG. 2 is a block diagram showing a configuration of a set-top box 100 and a security card 200 for receiving a CATV broadcast signal according to the embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a QAM demodulator 12, a demodulation mode controller 17, and a synchronization determination circuit 16 of FIG. FIG. 2 is a diagram showing a demodulation mode table stored in a data memory 23m of FIG. 3 is a flowchart illustrating an initial operation process executed by the device controller 23 of FIG. 1. 5 is a flowchart showing a FAT channel transmission information acquisition process (step S2) which is a subroutine of FIG. 5 is a flowchart showing a FAT channel search process (step S3) which is a subroutine of FIG. FIG. 9 is a block diagram illustrating a configuration of a carrier recovery circuit 123A and a synchronization determination circuit 16A according to a first modification of the present invention. FIG. 14 is a block diagram illustrating a configuration of a clock recovery and sampling circuit 121A and a synchronization determination circuit 16B according to a second modification of the present invention. FIG. 2 is a diagram illustrating a channel arrangement used in CATV for the set-top box 100 in FIG. 1.

Explanation of reference numerals

10 RF terminal,
11 ... QAM tuner,
12 ... QAM demodulator,
13 ... QPSK tuner,
14 QPSK demodulator,
15 ... QPSK modulator,
16, 16A, 16B ... synchronization determination circuit,
17 demodulation mode controller,
18. Tuner frequency controller,
20 ... switch,
21 ... MPEG decoder,
22 ... descrambler,
23 ... device controller,
23m ... data memory,
51: complex multiplier,
52 ... phase error detector,
53 ... Low-pass filter (LPF),
54 ... Numerically controlled oscillator (NCO)
61 ... Sampling circuit,
62 ... phase error detector,
63 ... Low-pass filter (LPF),
64 ... Sampling timing signal generation circuit,
65: synchronization determination circuit,
100 ... set-top box,
120 ... input terminal,
121, 121A: Clock recovery and sampling circuit,
122 ... roll-off filter
123 ... Carrier wave reproduction and waveform equalization circuit
123A: carrier wave recovery circuit,
124 ... an error correction circuit;
125 ... output terminal,
170 ... Baud rate controller,
171 ... filter coefficient controller,
172 code point arrangement controller,
173 ... controller,
200 ... security card,
200S slot.

Claims (13)

A security device for storing security information of a broadcaster and extracting transmission information for receiving a broadcast signal modulated in a predetermined modulation mode from a control signal from the broadcaster's device; and the extracted transmission information. In a broadcast signal receiving device configured to separate a receiver for receiving a broadcast signal from the broadcaster device based on the and the security device can be mounted on the receiver,
Tuning means for controlling a frequency of a received broadcast signal to select a predetermined broadcast signal;
In a plurality of demodulation modes corresponding to a modulation mode of a broadcast signal modulation method, it is possible to demodulate a broadcast signal from the broadcaster device, and the demodulation mode is set by the tuning means in the set demodulation mode among the plurality of demodulation modes. Demodulation means for demodulating the selected broadcast signal;
First control means for controlling a demodulation mode of the demodulation means;
Synchronization determining means for determining whether the demodulation means is synchronized with the received broadcast signal and outputting a synchronization determination result signal;
Device detection means for detecting whether or not the security device is mounted on the receiver;
When the device detection unit detects that the security device is not mounted on the receiver, the device controls the channel selection unit, the demodulation unit, and the first control unit to demodulate the broadcast signal. At least one of the mode and the frequency is changed to search for a broadcast channel on which the transmission information of the broadcast signal is transmitted, and the broadcast signal of the searched broadcast channel is received. When it is determined that the broadcast signal is synchronized with the broadcast signal, transmission information of the broadcast channel is extracted from the broadcast signal demodulated by the demodulation means, and a broadcast signal is received based on the extracted broadcast signal transmission information. A broadcast signal receiving device comprising a control unit.   2. A broadcast signal receiving apparatus according to claim 1, wherein said second control means initializes a demodulation mode control process by said first control means immediately after changing a frequency of said tuning means. .   The first control means, based on a synchronization determination result signal from the synchronization determination means, sets a modulation speed, a filter, and a modulation speed respectively set in the demodulation means until the demodulation means synchronizes with the received broadcast signal. 3. The broadcast signal receiving apparatus according to claim 1, wherein at least one of the coefficient and the code point arrangement is controlled. The demodulation means includes a carrier recovery circuit for recovering a carrier of the received broadcast signal,
4. The apparatus according to claim 1, wherein the synchronization determination unit determines whether the demodulation unit is synchronized with a received broadcast signal based on a phase error of a signal reproduced by the carrier reproduction circuit. The broadcast signal receiving device according to any one of the above. The demodulation means includes a clock recovery circuit that recovers a clock signal of the received broadcast signal,
4. The method according to claim 1, wherein the synchronization determination unit determines whether the demodulation unit is synchronized with a received broadcast signal based on a phase error of a clock signal recovered by the clock recovery circuit. 3. The broadcast signal receiving device according to any one of 3. The demodulation means includes an error correction circuit for correcting an error in the received broadcast signal,
The synchronization determination means determines whether the demodulation means has synchronized with the received broadcast signal based on whether a frame synchronization signal output from the error correction circuit can be detected. The broadcast signal receiving device according to any one of claims 1 to 3.   7. The broadcast signal receiving apparatus according to claim 1, wherein the first control unit and the synchronization determination unit are configured by a hardware circuit. A received signal modulated in a predetermined modulation mode can be demodulated in a plurality of demodulation modes corresponding to a modulation mode of a modulation scheme of the received signal, and the received signal is demodulated in a set demodulation mode among the plurality of demodulation modes. Demodulation means for demodulating,
Control means for controlling a demodulation mode of the demodulation means,
Synchronization determination means for determining whether the demodulation means is synchronized with the received broadcast signal and outputting a synchronization determination result signal,
The demodulation mode control device, wherein the control means controls a demodulation mode of the demodulation means based on a synchronization determination result signal from the synchronization determination means until the demodulation means synchronizes with the reception signal.   The control means, based on the synchronization determination result signal from the synchronization determination means, until the demodulation means synchronizes with the reception signal, each set in the demodulation means, a modulation rate, a filter coefficient, a code point 9. The demodulation mode control device according to claim 8, wherein at least one of the arrangement is controlled. The demodulation means includes a carrier recovery circuit for recovering a carrier of the received broadcast signal,
10. The method according to claim 8, wherein the synchronization determination unit determines whether the demodulation unit is synchronized with a received broadcast signal based on a phase error of the signal reproduced by the carrier wave reproduction circuit. The demodulation mode control device according to the above. The demodulation means includes a clock recovery circuit that recovers a clock signal of the received broadcast signal,
9. The method according to claim 8, wherein the synchronization determination unit determines whether the demodulation unit is synchronized with a received broadcast signal based on a phase error of a clock signal recovered by the clock recovery circuit. 10. The demodulation mode control device according to item 9. The demodulation means includes an error correction circuit for correcting an error in the received broadcast signal,
The synchronization determination means determines whether the demodulation means has synchronized with the received broadcast signal based on whether a frame synchronization signal output from the error correction circuit can be detected. The demodulation mode control device according to claim 8. 13. The demodulation mode control device according to claim 8, wherein the control unit and the synchronization determination unit are configured by a hardware circuit.

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