JPH0750697A - Four phases demodulation circuit and phase comparator of four phases demodulation circuit - Google Patents

Abstract

PURPOSE:To obtain stable detection output even if the amplitude of QPSK signals is not constant by digital-processing the A/D-converted QPSK signals by means of ROM tables corresponding to reproduced carriers, multipliers, digital LPF and a phase difference detection circuit so as to demodulate them. CONSTITUTION:The digital QPSK signals passing an A/D converter 24 are multiplied in the multipliers 2 and 3 by Cosomegact and Sinomegact signals which are the outputs of VCO 30 passing a frequency-dividing circuit 31, are read from the ROM tables 25 and 26 and whose phases are precisely different by 90 deg.. They are inputted to the phase difference detection circuit 34 through digital LPF 27 and 28 and a demodulation clock and demodulation data are outputted. Thus, stable detection output can be obtained even if variance does not exist in a circuit parameter and the amplitude of the QPSK signal is not constant by a digital processing using the ROM tables.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a four-phase phase demodulation circuit (hereinafter referred to as a QPSK circuit) for demodulating an audio signal in a satellite broadcast receiver and a phase comparator used in this QPSK circuit. Yes, the phase difference φ between the input QPSK signal and the reproduced carrier wave is ± (1/4) π
And a sawtooth-shaped phase difference signal output whose output becomes 0 at ± (3/4) π.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 5, a satellite broadcast receiver receives broadcast radio waves from a broadcast satellite (52) at an antenna (35) and receives the received broadcast radio waves at 1 GHz by a BS converter (36). It is converted to the intermediate frequency band of the band and sent to the BS tuner (37). In the BS tuner (37), a desired channel is selected by the channel selection circuit (38), FM demodulation is performed by the FM demodulation circuit (39), and then the video-
The audio separation circuit (40) separates and processes the video signal and the audio signal.

Of these signals, the video signal is a de-emphasis circuit (41) and an energy diffusion signal removing circuit (4).
2) The original video signal is reproduced by the TV receiver (4
It is input to the video signal input terminal (44) of 3). Also,
The audio signal is demodulated by the 4-phase phase demodulation circuit (45) and the PCM demodulation circuit (46), and the de-emphasis circuit (4
The original audio signal is reproduced by 7). Then, it is input to the audio signal input terminal (48) of the television receiver (43) to enable reception of satellite broadcasting.

As a QPSK circuit (45) used in the above satellite broadcast receiver, there is one shown in FIG. In the QPSK circuit (45), the QPSK signal input from the input terminal (1) is quantized by the A / D converter (24), and the phase difference detection circuit (49) outputs the VCO (3
0) is phase-compared with the oscillation signal input through the A / D converter (51) and is sent to the signal processing circuit (50).

On the other hand, from the signal processing circuit (50), the clock and demodulated data are sent to the clock output terminal (3).
2) and the data output terminal (33) and, on the other hand, the VCO control signal is sent to the VCO (30) via the D / A converter (29). VCO (30)
Oscillates by the VCO control signal from the signal processing circuit (50) so that the phase difference with the carrier wave on the transmission side of the QPSK signal becomes zero. The QPSK signal input from the input terminal (1) is represented by cos (ωct + ψ), ωc is the angular frequency of the carrier wave, and ψ is an information component representing information of bit data.

Further, as a QPSK circuit (45), as shown in FIG.
There was something shown in. The QPSK circuit (45) multiplies the QPSK signal input from the input terminal (1) by two regenerated carriers having a phase difference of 90 degrees by the multipliers (2) and (3), and outputs the respective signals to the LPF. (6) (7)
Output as a cosine wave Acosφ and a sine wave Asinφ having a phase difference φ between the QPSK signal and the reproduced carrier wave.
Input cosφ and Asinφ to the phase comparator (8) and input Q
A phase difference signal between the PSK signal and the reproduced carrier wave is obtained. A is the amplitude of the cosine wave and the sine wave.

The phase comparator (8) of this QPSK circuit (45) is shown in FIG. 3 depending on whether the phase difference φ between the QPSK signal and the reproduced carrier wave is in the first, second, third or fourth quadrant. Two change-over switches (1
5) and (16) are provided, and the cosine wave input terminal (9)
Is connected to one of the changeover switches (1
5) It is connected to _one switching terminal (15 ₁ ) and is also connected to the other switching terminal (15 ₂ ) of the one switching switch (15) through an inverter (11).

Further, the sine wave input terminal (10) is connected to _one changeover terminal (16 ₁ ) of the other changeover switch (16) through the non-inverter (14) and the inverter (12). ) Is connected to the other switching terminal (16 ₂ ) of the other switching switch (16). The outputs of these two changeover switches (15) and (16) are adders (17).
It is connected to the.

In the phase comparator (8), the changeover switches (15) and (16) are switched depending on whether the phase difference φ is in the first, second, third or fourth quadrant. Specifically, the output of the adder (17) is compared with the phase difference φ.
Is in the first quadrant, Asinφ−Acosφ, in the second quadrant, −Asinφ−Acosφ, in the third quadrant, −Asinφ + Acosφ, and in the fourth quadrant, Asinφ + Acosφ.
Changeover switch (15) (1) so that φ + Acosφ
6) is switched.

[0010]

The former one of the conventional QPSK circuits (45) is detected by the phase comparison circuit (49) unless the input amplitude of the QPSK signal input to the input terminal (1) is constant. There was a problem that the output was not constant. Further, if the carrier ωct of the QPSK signal and the frequency of change of the information component ψ are close to each other, there is a problem that the phase determination becomes difficult.

The amplitude of the output of the phase comparator (8) of the latter QPSK circuit (45) is determined by the input cosine wave Acos.
.phi. and the sine wave Asin.phi. have an amplitude A. When the amplitude A decreases, the amplitude of the phase difference signal output also decreases. For this reason,
When the PLL of the QPSK detector is configured by the phase comparator (8), there is a problem that the pull-in characteristic is affected by the input amplitude A and becomes unstable.

According to the present invention, even if the amplitude of the input QPSK signal is not constant, a stable detection output can be obtained.
A circuit is provided.

[0013]

The present invention has been made to solve the above-mentioned problems. As a first solution, the QPSK signal input terminal is coupled to an A / D converter,
The output of this A / D converter is branched into two and coupled to a phase difference detection circuit for demodulating clock and data via a multiplier and an LPF, respectively, and an oscillator for oscillating a reproduced carrier wave is used as an oscillator for oscillating the reproduced carrier wave. It is coupled to one of the multipliers via a ROM table for conversion into (ωct) and -s
It is connected to the other of the multipliers via a ROM table for converting into in (ωct).

As a second solution, the cosine wave A due to the phase difference φ between the input QPSK signal and the reproduced carrier wave.
An adder that inputs cos φ and a sine wave Asin φ and performs addition and subtraction of the cosine wave and the sine wave, and an amplitude reciprocal number that generates the reciprocal of the amplitude A of the cosine wave or the sine wave based on the cosine wave or the sine wave. It comprises a generation circuit, and a multiplier for multiplying the amplitude reciprocal number generation circuit and the phase difference signal output.

The amplitude reciprocal generator generates a square circuit that squares a cosine wave or a sine wave and a high frequency component of the output of the square circuit, and as a variable, the amplitude A of the cosine wave or the sine wave.
It is composed of an averaging circuit equivalent to a low-pass filter for extracting a signal of a component containing only A, and a 1 / A generating circuit for generating 1 / A from a signal containing only amplitude A as the variable.

[0016]

According to the first solution, the QPSK signal input to the QPSK signal input terminal is quantized by the A / D converter, and the quantized QPSK signal is multiplied by the reproduced carrier wave by the multiplier and input to the LPF. To be done. The LPF removes the carrier component from the multiplied signal and sends it to the phase difference detection circuit. In the phase difference detection circuit, the clock and data output to the PCM demodulator connected to the next stage are demodulated. The reproduced carrier wave output from the oscillator is sent to the ROM table, converted from one ROM table into the reproduced carrier wave cos (ωct) and sent to one of the multipliers, and the other ROM table reproduces the carrier wave -sin ( ωct) and sent to the other of the multipliers.

The second solution is to input the cosine wave Ac.
On the other hand, osφ and sine wave sinφ are added / subtracted by an adder and output as A (± cosφ ± sinφ). On the other hand, either a cosine wave or a sine wave is squared by a squaring circuit. For example, in the case of a cosine wave, A ² cos ² φ = A ² / 2-A ² cos φ / 2, and the high-frequency component A ^{2 of the} second term on the right side cos [phi / 2 is removed by the averaging circuit, only the signal a ^2/2 on the right side first term including only the amplitude a is taken as a variable. Further, the signal A ^2/2 was treated with 1 / A circuit generates a 1 / A, the output A (± cosφ ± sinφ) Toko from the adder 1
/ A is multiplied by a multiplier to eliminate the amplitude A and output.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIG. In FIG. 1, reference numeral (1) is a QPSK signal input terminal, which is branched into two via an A / D converter (24) and connected to the inputs of the digital multipliers (2) and (3). The outputs of (2) and (3) are digital LPF (2
7) It is connected to the phase difference detection circuit (34) via (28).

This phase difference detection circuit (34), on the other hand,
It is connected to the clock output terminal (32) and the data output terminal (33) as an output to the PCM demodulation circuit (46) of the next stage, while the VCO control output is a rectangular wave through the D / A converter (29). It is connected to the VCO (30). The output of the rectangular wave VCO (30) is output via the frequency dividing circuit (31) to c
ROM table (25) to convert to os (ωct) and -s
It is connected to a ROM table (26) for converting into in (ωct), and these ROM tables (25) and (26) are connected to the multipliers (2) and (3), respectively.

In the configuration of the first embodiment described above, the QPS
The QPSK signal input from the K input terminal (1) is co
It is represented by s (ωct + ψ). ωc is the angular frequency of the carrier,
ψ is an information component representing the information of the bit data, and (n
/ 4) π or (n = 1, 3, 5, 7).

The QPSK signal cos (ωct + ψ) inputted to the input terminal (1) is quantized by the A / D converter (24), and the quantized QPSK signal is quantized by the digital multipliers (2) (3). , ROM table (25) (26)
(1) cos (ωct + ψ) × {cos (ωct + ψ) × cos (ωct) = 1/2 {cos (2ωct + ψ) + cosψ} (1) cos (ωct + ψ) × { −sin (ωct)} = ½ {sin (2ωct + ψ) + sinψ} (2)

The signal multiplied by these reproduced carriers is
By the digital LPF (27) (28), the above formula (1)
The carrier wave component of the first term of (2) is removed, resulting in 1/2 (cosψ) ... (3) 1/2 (sinψ) (4), respectively, which are input to the phase difference detection circuit (34).

The phase difference detection circuit (34) uses ψ = arctan (sin ψ / cos ψ) (5) to obtain a constant information component ψ regardless of the amplitude from the data output terminal (33) to the next stage PCM demodulation circuit. Output to (46). In addition, ψ is (n / 4) π, (n =
Since it takes any one of 1, 3, 5, 7), 1/2 (c
os can be determined by the sign (+-) of ψ) and 1/2 (sin ψ). In addition, the speed of phase determination is
The size can be increased according to the width of the pass band of the PF (27) (28). For example, a digital LPF (27) (28) having a wide pass band with an order of about 4 can be phase-judged from four pieces of data.

Further, the phase difference detection circuit (34) is a QPS
The phase of the carrier wave on the transmission side of the K signal and the rectangular wave VCO (3
The VCO control signal that compares the phase difference of the reproduced carrier wave generated by (0) to 0 and makes the difference 0 is converted to analog by the D / A converter (29) and added to the rectangular wave VCO (30). The rectangular wave VCO (30) oscillates at a frequency N times as high as the reproduced carrier wave ωct, and this is divided into 1 / N by the frequency dividing circuit (31) and input to the ROM tables (25) and (26). The output of the rectangular wave VCO (30) is analog,
Since it is a rectangular wave, it is a substantially digital signal.

The ROM table (25) is a rectangular wave VCO.
Cos (ωct) selected according to the signal from (30)
The reproduced carrier of is output and input to the multiplier (2). Further, the ROM table (26) outputs a reproduced carrier of -sin (ωct) that is orthogonal (-90 degrees) to the cos (ωct) and is input to the multiplier (3). The data of the digital multipliers (2) (3) is again converted to the digital LPF (27) (2).
8) via the phase difference detection circuit (34) and D /
The A-converted VCO control signal is added to the rectangular wave VCO (30). This operation is repeated until the phase difference becomes 0, and the clock and demodulated output are output from the respective output terminals (32) (3
3) to the PCM demodulation circuit (46).

In the above embodiment, since the rectangular wave VCO (30) for generating the reproduced carrier wave is of analog type, the output of the phase difference detection circuit (34) is converted into analog by the D / A converter (29) and input. However, the rectangular wave VCO (3
0) is a digital type, a D / A converter (2
9) can be omitted.

Next, a second embodiment of the present invention will be described with reference to FIGS. In FIG. 2, (1) is QP
It is an input terminal of the SK signal and is connected to one input terminal of each of the multiplier (2) and the multiplier (3) via the A / D converter (24). A reproduction carrier from a reproduction carrier generator (4) such as a VCO is input to the other input terminal of one multiplier (2), and the other multiplier (3)
The regenerated carrier wave is input from the regenerated carrier wave generator (4) to the other input terminal via a delay circuit (5) that delays the phase by 90 degrees. The outputs of the multipliers (2) and (3) are connected to the input terminals (9) and (10) of the phase comparator (8) via the low pass filters (6) and (7), respectively.

The phase comparator (8) has two change-over switches (15) which are switched depending on whether the phase difference between the QPSK signal and the reproduced carrier wave is in the first, second, third or fourth quadrant. (16) is provided, the input terminal (9) of the cosine wave is connected to the _one switching terminal (15 ₁ ) of the _one switching switch (15) through the non-inverting device (13), and It is connected to the other switching terminal (15 ₂ ) of the one switching switch (15) through an inverter (11).

The sine wave input terminal (10) is connected via the non-inverting device (14) to one switching terminal (16 ₁ ) of the other switching switch (16) and the inverting device (12). ) Is connected to the other switching terminal (16 ₂ ) of the other switching switch (16). The outputs of these two changeover switches (15) and (16) are adders (17).
The output of the adder (17) is connected to the multiplier (1
8) One of the input terminals is connected. The changeover switches (15) and (16) are composed of gate circuits of digital circuits.

The sine wave input terminal (10) is further provided with a square circuit (20), an averaging circuit (21) equivalent to a low-pass filter, and a 1 / A generating circuit (2 consisting of a ROM table.
2) is connected to the other input of the multiplier (18) via the amplitude reciprocal generation circuit (23), and the multiplier (18) is connected to the output terminal (19).

In the configuration of the second embodiment, the QPSK signal input from the input terminal (1) is quantized by the A / D converter (24) and converted into a digital data signal, and the multiplier ( 2) By (3), two reproduced carrier waves having a phase difference of 90 degrees from the reproduced carrier wave generator (4) are multiplied. Each data signal is LPF
The data signals of the cosine wave Acosφ and the sine wave Asinφ of the phase difference φ between the QPSK signal and the reproduced carrier are input to the input terminals (9) and (10) of the phase comparator (8) via (6) and (7), respectively.

Cosine wave Aco input from the input terminal (9)
sφ is a non-inverting device (13) by a changeover switch (15)
Alternatively, it is input to one input terminal of the adder (17) through either one of the inverter (11) and the input terminal (1
0), the sine wave Asin φ is input to the non-inverter (14) or the invertor (12) by the change-over switch (16).
Is input to the other input terminal of the adder (17).

The change-over switch (15) is provided on the side of the inverter (11) when the phase difference φ between the QPSK signal and the reproduced carrier is in the first and second quadrants as shown in FIG. 4, that is, when Asinφ is positive. To the non-inverter (13) side when in the third and fourth quadrants, that is, when Asin φ is negative. Changeover switch (1
6) is an inverter (12) when the phase difference φ is in the second quadrant and the third quadrant, that is, when Acosφ is negative.
The non-inverter (14) when switched to the side and in the first and fourth quadrants, that is, when Acos φ is positive.
Switched to the side.

Sine wave A input from the input terminal (10)
The cos φ is further input to the squaring circuit (20).
The output of the squaring circuit (20) becomes A ² sin ² φ = A ² ((1-cos2φ) / 2) = A ² / 2-A ² cos φ / 2 (1), and this data signal is averaged. It is input to the circuit (21). Here, since the change of φ is the bit transmission rate of QPSK, the averaging circuit (2
1) A ² cos [phi / 2 of the second term on the right side is cut by, variable amplitude A by only A ^2/2 of the first term on the right side including the 1 / A generator circuit comprising a ROM table as the data signal (22) Entered in.

The 1 / A generation circuit (22) selects 1 / A data corresponding to the input data signal from the ROM table and outputs it as a data signal, and the multiplier (18) outputs the 1 / A data. The data signal and the output (± Acosφ ± Asinφ) from the adder (17) are multiplied and output as a phase difference signal. That is, the amplitude of the phase difference signal output from the output terminal (19) is the cosine input from the input terminals (9) and (10) after the coefficient A (amplitude) of the output signal of the adder (17) is deleted. The output is always a constant amplitude regardless of the amplitude A of the wave Acosφ and the sine wave Asinφ.

In the second embodiment described above, the 1 / A circuit (2
Although the example using the ROM table has been described in 2), the present invention is not limited to this, and a general-purpose divider or a dedicated logic circuit may be used. In the second embodiment described above, As
Non-inverters (13) and (14) are provided corresponding to the inverters (11) and (12) in order to invert and non-invert the signs of inφ and Acosφ. ), The non-inverters (13) and (14) need not be provided.

In the second embodiment described above, the data signal is input to the squaring circuit (20) from the input terminal (10) side of Asinφ. However, the data signal is input from the input terminal (9) side of Acosφ. Is also good. In this case, equation (1) is ^{A 2 cos 2 φ = A 2} ((1-sin2φ) / 2) = A 2/2 + A 2 sin
φ / 2, which is the output of the averaging circuit (21) and A of the second term on the right side.
² sin [phi / 2 results because only A ^2/2 of the first term on the right side is cut remains the same.

[0038]

As described above, according to the present invention, all or part of the QPSK circuit is converted into a digital circuit.
There is no variation in the circuit parameters, the operation is stable, a stable phase difference detection output is obtained regardless of the amplitude of the input QPSK signal, and even if the carrier ωct of the QPSK signal and the change frequency of the information component ψ are close to each other. The phase can be easily determined. Furthermore, the reproduced carrier wave generated by the rectangular wave VCO is set by cos (ωct) and −sin (ω
Since it is converted into ct) and input to the digital multiplier, orthogonal reproduced carrier waves can be digitally generated accurately and there is no phase amount error.

Furthermore, if the amplitude reciprocal number generation circuit is used for the phase comparator, there is an effect that a stable phase difference signal output having a constant amplitude independent of the amplitudes A of the input cosine wave and sine wave can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a four-phase phase demodulation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a four-phase phase demodulation circuit according to a second embodiment of the present invention.

FIG. 3 is a characteristic diagram showing an output of a phase comparator.

FIG. 4 is an explanatory diagram showing a switching state of the switch of FIG.

FIG. 5 is a block diagram of a general satellite broadcast receiver.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a block diagram showing a conventional example.

[Explanation of symbols]

(1) ... QPSK signal input terminal, (2) (3) ... Multiplier, (4) ... Regenerated carrier wave generator, (5) ... Delay circuit,
(6) (7) ... LPF, (8) ... Phase comparator, (9) ...
Cosine wave input terminal, (10) ... Sine wave input terminal, (1
1) (12) ... inverter, (13) (14) ... non-inverter,
(15) (16) ... Changeover switch, (17) ... Adder,
(18) ... Multiplier, (19) ... Output terminal, (20) ... Square circuit, (21) ... Averaging circuit, (22) ... 1 / A generation circuit, (23) ... Amplitude reciprocal generation circuit, (24) )… A / D
Converter, (25) (26) ... ROM table, (27)
(28) ... Digital LPF, (29) ... D / A converter,
(30) ... VCO, (31) ... Frequency divider circuit, (32) ... Clock output terminal, (33) ... Data output terminal, (34)
... Phase difference detection circuit, (35) ... Antenna, (36) ... B
S converter, (37) ... BS tuner, (38) ... Channel selection circuit, (39) ... FM demodulation circuit, (40) ... Video-audio separation circuit, (41) ... De-emphasis circuit, (42)
... energy diffusion signal removal circuit, (43) ... television receiver, (44) ... video signal input terminal, (45) ... four-phase phase demodulation circuit, (46) ... PCM demodulation circuit, (47) ... de-emphasis circuit, (48) ... voice signal input terminal, (5
2) ... Broadcast satellite.

Claims (3)

[Claims] 1. A unit for coupling a QPSK signal input terminal to an A / D converter, branching the output of this A / D converter into two, and demodulating a clock and data through a multiplier and an LPF, respectively. An oscillator that oscillates the regenerated carrier wave is coupled to the phase difference detection circuit
It is coupled to one of the multipliers via a ROM table for converting to (ωct) and is coupled to the other of the multipliers via a ROM table for converting to −sin (ωct). Phase phase demodulation circuit. 2. A cosine wave Acosφ and a sine wave Asin due to a phase difference φ between an input QPSK signal and a reproduced carrier wave.
Inputting φ to perform addition and subtraction of these cosine wave and sine wave, and a phase difference signal output of a sawtooth shape in which the output becomes 0 when the phase difference φ is ± (1/4) π and ± (3/4) π And an amplitude reciprocal generation circuit that generates the reciprocal of the amplitude A of the cosine wave or the sine wave based on the cosine wave or the sine wave.
A phase comparator for a four-phase phase demodulation circuit, comprising a multiplier for multiplying the amplitude reciprocal number generation circuit and the phase difference signal output. 3. A reciprocal amplitude generation circuit removes a high frequency component of the output of the square circuit and a square circuit for squaring a cosine wave or a sine wave, and the amplitude A of the cosine wave or the sine wave is used as a variable.
An averaging circuit equivalent to a low-pass filter for extracting a signal of a component containing only A, and a 1 / A generating circuit for generating 1 / A from a signal containing only the amplitude A as the variable. A phase comparator of the four-phase phase demodulation circuit according to item 2.