JP2987565B2 - Pattern inspection method and pattern inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an inspection method and an inspection apparatus for inspecting a pattern formed on a green sheet or a film carrier.

[0002]

2. Description of the Related Art Conventionally, PGA (Pin Grid Array) has been known as a mounting technique suitable for a demand for increasing the number of pins of ICs and LSIs. In PGA, a ceramic substrate is used as a base of a package for attaching a chip, and wiring is performed to a lead wire extraction position. To make this ceramic substrate, a so-called green sheet made by kneading alumina powder with a liquid binder is used, and a paste containing a high melting point metal is screen-printed on the green sheet. By firing such a sheet, so-called simultaneous firing, in which the green sheet is sintered and the paste is metallized, is performed.

[0003] As another mounting technique, TAB is used.
(Tape Automated Bonding) is known. TAB method is a polyimide film carrier (TAB tape)
The copper foil pattern formed thereon is joined to the electrode of the IC chip to form an external lead. The copper foil pattern is formed by attaching a copper foil to a film with an adhesive and etching this.

In such a green sheet or film carrier, a pattern is visually inspected by a human using a microscope after the pattern is formed. However, visually inspecting a fine pattern requires skill and has a problem of overworking the eyes. Therefore, as an alternative to the visual inspection, a technique has been proposed in which a pattern formed on a film carrier or the like is imaged by a TV camera and automatically inspected (for example, Japanese Patent Application Laid-Open No. 6-27313).
No. 2, JP-A-7-110863). However, JP-A-6-273132, JP-A-7-110
The inspection method disclosed in Japanese Patent No. 863 has a problem that it takes a long time to perform a pattern inspection because a detailed inspection by comparison with a master pattern is repeated over the entire pattern to be measured. Therefore, an inspection method capable of inspecting a pattern for projections, defects, disconnections or short circuits at high speed has been proposed (Japanese Patent Application No. 8-30280).
No. 7).

[0005] In the inspection method disclosed in Japanese Patent Application No. 8-302807, a first master pattern created from CAD data at the time of designing a pattern to be measured or a non-defective product of the pattern to be measured is subjected to a second master pattern. In addition to creating a pattern, a first master pattern is expanded to create a third master pattern. When the logical product of the measured pattern and the second master pattern is calculated, the result of the logical product differs depending on whether the measured pattern has a defect or a disconnection, and the logical product of the measured pattern and the third master pattern is calculated. Then, since the result of the logical product differs depending on whether or not the pattern to be measured has a protrusion or a short circuit, the defect of the pattern to be measured can be inspected at high speed.

However, this inspection method detects a pattern residue (hereinafter, referred to as “scatter”) or a missing pattern (hereinafter, referred to as “pinhole”) in a region not corresponding to the second and third master patterns. There was a problem that it was not possible. That is, as shown in FIG.
Scattered F (pixel “1”) or pinhole H (pixel “0”) exists in the area of the pattern P to be measured that does not correspond to the master pattern M1 and the third master pattern M2 of FIG.
This is because these do not overlap with the master patterns M1 and M2, so that even if the logical product with the master pattern M1 or M2 is taken, they do not appear in the result of the logical product.

[0007]

As described above, the method of inspecting a defect by taking the logical product of the pattern to be measured and the master pattern detects defects such as scattering and pinholes existing in an area not corresponding to the master pattern. There was a problem that it was not possible. The present invention has been made to solve the above-described problem, and has as its object to provide an inspection method and an inspection apparatus capable of detecting defects such as scattering and pinholes quickly and correctly.

[0008]

According to a first aspect of the present invention, a first master pattern serving as a reference for comparison with a pattern to be measured is subjected to shrinkage processing, and a defect, a pinhole or a disconnection is caused. A second master pattern for detection is created, and the first master pattern is expanded to perform projection,
A third master pattern for scattering or short circuit detection is created, and the second master pattern is expanded to obtain a logical product of the pattern to be measured, and the result of the logical product is compared with the second and third master patterns. The fourth master pattern is used as a fourth master pattern for detecting scattering in an uncorresponding area, and the fourth master pattern is expanded to obtain a logical product with the pattern to be measured. The result of this logical product is used as a new fourth master pattern. This is repeated a predetermined number of times, and after calculating the logical inversion of the third master pattern, a contraction process is performed to obtain a logical sum with the pattern to be measured. The result of the logical sum is stored in an area not corresponding to the second and third master patterns. The fifth master pattern for pinhole detection in the above is used as a fifth master pattern, and the fifth master pattern is subjected to contraction processing to obtain a logical sum with the pattern to be measured, and the result of this logical sum is used as a new fifth master pattern. The predetermined pattern is repeated a predetermined number of times, and an exclusive OR of the pattern to be measured and the fourth master pattern and an exclusive OR of the pattern to be measured and the fifth master pattern are obtained. This is to detect a defect. The first master pattern is created from CAD data at the time of designing the pattern to be measured or a non-defective product of the pattern to be measured. The second master pattern is subjected to expansion processing to obtain a logical product with the pattern to be measured, and the result is used as a fourth master pattern.
By performing a logical multiplication with the pattern to be measured by performing the expansion processing on the master pattern of No. 4 and repeating the result as a new fourth master pattern a predetermined number of times, the fourth master pattern is removed except for the scattered portion. It becomes the same as the measurement pattern. Therefore, by taking the exclusive OR of the pattern to be measured and the fourth master pattern, the scattering of the pattern to be measured can be detected. Further, after obtaining the logical inversion of the third master pattern, a contraction process is performed to obtain a logical sum with the pattern to be measured, and the result is set as a fifth master pattern. When the logical sum with the pattern is obtained and the result is used as a new fifth master pattern a predetermined number of times, the fifth master pattern becomes the same as the pattern to be measured except for the pinhole portion. Therefore, the pinhole of the pattern to be measured can be detected by taking the exclusive OR of the pattern to be measured and the fifth master pattern.

According to a second aspect of the present invention, the first master pattern serving as a reference for comparison with the pattern to be measured is subjected to contraction processing, and the second master pattern for detecting defects, pinholes, or disconnections. And a master pattern creating means for expanding the first master pattern to create a third master pattern for detecting protrusions, splatters or short circuits, and expanding and measuring the second master pattern for measurement. Find the logical product of the pattern and the result of this logical product in the second,
The fourth master pattern is used as a fourth master pattern for scattering detection in an area not corresponding to the third master pattern. The fourth master pattern is subjected to expansion processing to obtain a logical product of the fourth master pattern and the measured pattern. 4 is repeated a predetermined number of times, the logical inversion of the third master pattern is obtained, and then contraction processing is performed to obtain the logical sum with the pattern to be measured. The result of this logical sum is calculated in the second and third master patterns. A fifth master pattern for pinhole detection in an area not corresponding to the master pattern is obtained, and the fifth master pattern is subjected to contraction processing to obtain a logical sum with the pattern to be measured. The pattern to be measured and the fourth master pattern are exclusive ORed, and the pattern to be measured and the fifth master pattern are excluded. By taking the logical sum, and has an image processing means for detecting a defect of the pattern to be measured.

According to a third aspect of the present invention, the image processing means includes a first expansion circuit for expanding the second master pattern, and a logical product of an output of the first expansion circuit and a pattern to be measured. A set of a first logical product circuit, a second expander circuit for expanding the input pattern and a second logical circuit for obtaining the logical product of the output of the second expander circuit and the pattern to be measured has a predetermined number of stages. A first logical operation circuit in which the output of the first AND circuit is connected to the input of the second expansion circuit in the first stage, the output of the second AND circuit in the last stage, and the pattern to be measured A first exclusive logical circuit for performing an exclusive OR operation on the third master pattern, and an inverting circuit for performing a logical inversion of the third master pattern.
A first shrinking circuit for shrinking the pattern output from the inverting circuit, a first OR circuit for ORing the output of the first shrinking circuit with the pattern to be measured, and a second shrinking circuit for shrinking the input pattern Is connected in series with a predetermined number of stages, and a first OR circuit is connected in series with a predetermined number of stages, and the first stage is connected to the input of the first stage second contraction circuit. A second logical operation circuit to which the output of the logical OR circuit is connected, and a second exclusive logical circuit for obtaining the exclusive OR of the output of the second logical OR circuit at the final stage and the pattern to be measured. Things.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing a pattern inspection method according to an embodiment of the present invention.
FIG. 2 is a block diagram of a pattern inspection apparatus used in this inspection method. In FIG. 2, 1 is a green sheet, 2 is an XY table on which the green sheet 1 is placed, 3 is a line sensor camera that captures an image of the green sheet 1, 4 is a sensor that detects a defect in the pattern to be measured, and determines the position of the defect. A first image processing device for outputting the address information shown, a second image processing device for obtaining an error between a measured pattern and a master pattern in a predetermined area including a defect based on the address information, and inspecting the measured pattern; , 6 is a host computer for controlling the entire apparatus, and 7 is a display device for displaying inspection results.

First, a master pattern created before inspection will be described. Host computer 6
Reads out, by a magnetic disk device (not shown), design value data (hereinafter referred to as CAD data) of a green sheet created by a CAD (Computer Aided Design) system and written on, for example, a magnetic disk (step 101 in FIG. 1).

Subsequently, pattern edge data is extracted from the read CAD data. The edge data is a set of pixels “1” indicating a pattern edge. Then, the area surrounded by the pixel “1” indicating the pattern edge is defined as “1”.
The pattern painted with the pixel “1” (the background other than the pattern is “0”) is set as a first master pattern to be a reference for inspection (step 102).

It goes without saying that a green sheet 1 is produced based on the CAD data and a pattern is screen-printed on the sheet 1. Next, the host computer 6 generates a second master pattern, a protrusion, and the like for detecting a defect, a pinhole or a disconnection from the first master pattern.
A third master pattern for detecting scattering or short circuit is created as follows (step 103). FIG. 3 is a diagram for explaining a method of creating the second and third master patterns, and shows a part of the first master pattern.

First, as shown in FIG. 3A, the first master pattern is contracted in a direction perpendicular to its center line,
A second master pattern M1 is created. This is because opposing straight lines A1 and A1 indicating both edges of the first master pattern
4 (center line is L1) and the distance between A2 and A3 (center line is L2) are narrowed to narrow the first master pattern.

The accuracy of the defect detection by the second master pattern M1 is determined by how much the first master pattern is contracted. For example, when it is desired to recognize a defect when there is a defect exceeding 1/5 of the width of the first master pattern, the width of the second master pattern M1 is set to 3/5 of the width of the first master pattern. What is necessary is just to reduce it. It goes without saying that the detection accuracy may be determined in pixel units or actual dimensions. Thus, the second master pattern M1 for detecting a defect, a pinhole, or a disconnection is created.

Subsequently, as shown in FIG. 3B, the first master pattern is expanded in a direction perpendicular to the center line of the first master pattern to create a third master pattern M2. This corresponds to the opposite straight line A5 indicating both edges of the first master pattern.
And A8 (center line is L3), A6 and A7 (center line is L
4), A9 and A12 (center line is L5) and A10 and A1
1 (the center line is L6), and the first master pattern can be made thicker by widening the respective intervals.

However, actually, the third master pattern M2
Is a master pattern M composed of straight lines A5 to A8.
a and a region (base portion where no pattern exists) sandwiched between two patterns generated by expanding the master pattern Mb including the straight lines A9 to A12. That is, the result of the expansion processing is logically inverted.

The accuracy of defect detection by the third master pattern M2 is determined by how much the first master pattern is expanded. For example, when it is desired to recognize a defect when there is a defect exceeding 1/5 of the width of the first master pattern, the width of the third master pattern M2 is set to 7/5 of the width of the first master pattern. It should just be expanded as follows. The fact that the detection accuracy may be determined in pixel units or actual dimensions is the same as in the second master pattern. Thus, the third master pattern M2 for detecting protrusions, scattering, or short circuits is created.

In FIG. 3, for the sake of simplicity, the first master pattern is represented only by a straight line representing a pattern edge, and the second master pattern is represented by a straight line representing a pattern edge and a hatched line representing the inside thereof. Although the third master pattern is shown, the actual first to third master patterns are pattern edges and the inside thereof are filled with a pixel “1”. Further, in the present embodiment, since a positioning mark described later is used for positioning, expansion and contraction processing is not performed on the position of the positioning mark.

Next, the inspection of the pattern to be measured will be described. First, the green sheet 1 is imaged by the camera 3. Then, the first image processing device 4 digitizes the grayscale image output from the camera 3 and temporarily stores it in an internal image memory (not shown) (step 10).
4). Since the camera 3 is a line sensor in which pixels are arranged in the X direction, the XY table 2 or the camera 3 is moved in the Y direction (in the present embodiment, the table 2 is moved).
Moves in the Y direction). Two-dimensional image data is stored in the image memory.

Next, the pattern to be measured and the master pattern are aligned (step 105). FIG. 4 is a diagram for explaining this alignment method. First, the first image processing apparatus 4 sets the positioning mark a provided in advance at the time of creating the CAD data in the pattern to be measured P1 stored in the image memory as shown in FIG.
In the second master pattern M1 sent from the host computer 6, the positioning marks b corresponding to these are specified as shown in FIG. 4B.

Then, for each of the pattern to be measured P1 and the master pattern M1, the distances DXp and DXm between the two positioning marks arranged in the X direction are obtained. The distance between marks is the distance between the centers of gravity of two positioning marks.

Subsequently, an enlargement / reduction ratio (DXp / DXm) is calculated from the obtained distance between marks, and the distance between marks of the master pattern is made to match the distance between marks of the pattern to be measured by the enlargement / reduction ratio. , The master pattern M1 is enlarged or reduced in all directions. Next, the pattern to be measured P
The distances DYp and DYm between the two positioning marks arranged in the Y direction are obtained for each of the master pattern M1 ′ and the corrected master pattern M1 ′ as shown in FIGS. 4C and 4D.

The relative speed between the line sensor camera 3 and the green sheet 1 (XY table 2) is adjusted so that the distance between marks of the pattern to be measured matches the distance between marks of the master pattern. Is imaged again.
The image resolution in the Y direction is determined by the pixel size of the camera 3 and the relative speed. Therefore, by changing the moving speed of the XY table 2 or the line sensor camera 3, the image resolution in the Y direction can be adjusted, and the distance between marks can be matched.

Next, the pattern P1 'as shown in FIG. 4 (e) is obtained based on the positioning mark positions of the pattern P1' to be measured and the master pattern M1 'enlarged / reduced and corrected by the imaging as described above. , M
1 ′ is obtained, and the master pattern M1 ′ is rotated so as to eliminate the angle deviation. Finally, the positions of the master pattern M1 ′ and the pattern to be measured P1 ′ are aligned so that the mark positions match each other.

In this manner, the position of the master pattern and the position of the pattern to be measured can be matched, and the position on the pattern to be measured can be associated with the position on the master pattern in the inspection described later. As described above, in the present embodiment, the image resolution in the Y direction is adjusted by changing the capturing speed of the camera 3 with respect to the image resolution in the X direction determined by the number of pixels of the line sensor camera 3, and thereby the vertical ( The ratio of Y) to the width (X) can be 1: 1.

In an actual inspection, the ratio of length and width may not be completely 1: 1. For example, a pattern to be screen-printed on a green sheet may be printed in a state of being elongated depending on a printing direction. Therefore,
In the case of a non-defective pattern in which the elongation within an allowable range with respect to the standard exists, the ratio of length to width is completely 1: 1.
Does not. In the present embodiment, since the distance between marks in the Y direction is made to match by changing the capture speed of the line sensor camera 3, it is possible to match patterns to be measured having different vertical and horizontal scales within the allowable range with the master pattern. In addition, the position of a pattern can be automatically corrected with respect to a change in the pattern position during formation.

The second master pattern M1 and the third master pattern M2 created from the first master pattern
Since the positional relationship between them is known, the master pattern M
1, M2 and the pattern to be measured may be aligned once as described above.

Subsequently, the image processing apparatus 4 binarizes the grayscale image of the pattern to be measured after the position adjustment (Step 106). The density image data of the pattern to be measured includes the pattern and the other background (substrate), but there is a density difference between the pattern and the background. Is set as the threshold value, the pattern is converted to “1”, and the background is converted to “0”. In this way, it is possible to obtain a pattern to be measured in which the pattern edge and the inside thereof are filled with the pixel “1”.

Next, the image processing device 4 compares each of the second and third master patterns and fourth and fifth master patterns, which will be described later, with the binarized pattern to be measured. Are inspected (steps 107 to 110). These inspections are performed simultaneously by hardware described later.

First, the inspection (step 107) by comparison with the second master pattern will be described. FIG. 5 is a diagram for explaining this inspection method. In FIG. 5, the second master pattern M1 is represented by a straight line representing a pattern edge and an oblique line representing the inside thereof, and the pattern to be measured P is represented by a straight line representing a pattern edge and a satin representing the inside thereof. I have.

A logical product circuit (not shown) in the image processing device 4 calculates a logical product of the pattern P to be measured and the second master pattern M1. The result of the logical product differs depending on whether the pattern P to be measured has a defect, a disconnection, or the like. If there is no loss or disconnection in the pattern to be measured P, the master pattern M
All pixels of the pattern P to be measured in an area corresponding to 1 (an area overlapping the pattern M1 in FIG. 5) are “1”.
Therefore, the result of the logical product in the area corresponding to the master pattern M1 is all “1”.

On the other hand, when there is a defect (pixel “0”) in the pattern P to be measured, there is a pixel whose logical product is “0” in the area corresponding to the master pattern M1. . This is the same when a pinhole or a disconnection exists in an area corresponding to the master pattern M1. In this way, it is possible to detect a defect, a pinhole or a disconnection in the pattern to be measured. Then, the image processing device 4 stores the position (the position C in FIG. 5) at which the result of the logical product is “0” and is recognized as a defect.

Next, the inspection (step 108) by comparison with the third master pattern will be described. FIG. 6 is a diagram for explaining this inspection method. In FIG. 6, the third master pattern M2 is represented by a straight line representing a pattern edge and a diagonal line representing the inside thereof, and the pattern P to be measured is represented by a straight line representing a pattern edge and a satin pattern representing the inside thereof. I have.

A logical product circuit (not shown) in the image processing device 4 calculates the logical product of the pattern P to be measured and the third master pattern M2. The result of this logical product differs depending on whether the pattern P to be measured has a protrusion, a short circuit, or the like. If there is no protrusion or short circuit in the pattern P to be measured, the master pattern M
2 (the area overlapping the pattern M2 in FIG. 6), all the pixels of the measured pattern P are “0”.
Therefore, the result of the logical product in the area corresponding to the master pattern M2 is all “0”.

On the other hand, when a protrusion (pixel "1") exists in the pattern P to be measured, a pixel whose logical product is "1" exists in a region corresponding to the master pattern M2. . Similarly, when the two patterns to be measured P are short-circuited, there is a pixel whose logical product is “1” in a region corresponding to the master pattern M2. The same applies to the case where the scattering exists in the area corresponding to the master pattern M2.

In this way, it is possible to detect protrusions, scattering or short-circuits of the pattern to be measured. Then, the image processing device 4 stores the position (the position of D and E in FIG. 6) at which the result of the logical product becomes “1” and is recognized as a defect.

Next, the inspection (step 109) by comparison with the fourth master pattern will be described. FIG. 7 is a diagram for explaining the inspection method, and FIG.
It is a block diagram of the inspection part which performs the inspection by comparing with the 4th master pattern provided in the inside, and performs the inspection by comparing with the 5th master pattern mentioned later.

In the pattern P to be measured shown in FIG. 7 (a), the scatter F between the area corresponding to the second master pattern M1 and the area corresponding to the third master pattern M2.
Is present, the scattering F cannot be detected by the above inspection. Expansion circuits 11-1 to 11-n serving as an inspection unit for performing an inspection for comparison with the fourth master pattern;
2-1 to 12-n and the exclusive OR circuit 13 are for detecting such scattering F.

The first expansion circuit 11-1 expands the second master pattern M1 in a direction perpendicular to the center line L (FIG. 7B). At this time, the expansion circuit 11-1 expands the master pattern M1 by a predetermined number of pixels. The first AND circuit 12-1 calculates the AND of the output of the expansion circuit 11-1 and the pattern P to be measured.

Here, the master pattern M after the expansion process
1 (in FIG. 7B, the pattern M1
Since all the pixels of the pattern P to be measured in the area (overlapping with the pattern) are “1”, the result of the logical product in the area corresponding to the master pattern M1 after the expansion processing is all “1”. Therefore, the result of the logical product is the same as the master pattern M1 after the expansion processing, and this is set as the fourth master pattern M3 (FIG. 7C).

The second expansion circuits 11-2 to 11-n,
In the AND circuits 12-2 to 12-n, one set including an expansion circuit and an AND circuit has a predetermined number of stages (in the present embodiment, n-
1) The fourth master pattern M3, which is connected in series, undergoes expansion processing of the fourth master pattern M3 to obtain a logical product of the fourth master pattern M3 and the pattern P to be measured.
The setting of 3 is repeated a predetermined number of times.

For example, the expansion circuit 11-2 expands the output of the AND circuit 12-1, that is, the fourth master pattern M3 in a direction perpendicular to the center line L (FIG. 7D).
At this time, the expansion circuit 11-2 expands the master pattern M3 by a predetermined number of pixels. And the AND circuit 12-2
Takes the logical product of the output of the expansion circuit 11-2 and the pattern P to be measured.

Here, the master pattern M after the expansion processing is
7 (in FIG. 7D, the pattern M3
Since all the pixels of the pattern P to be measured (the area overlapping with) are “1”, the result of the logical product in the area corresponding to the master pattern M3 after the expansion processing is all “1”. Therefore, the result of this logical product is the same as the master pattern M3 after the expansion processing, and is set as a new fourth master pattern M3 (FIG. 7E).

When such processing is repeated by the subsequent expansion circuit and AND circuit, the size of the fourth master pattern M3 approaches the size of the pattern P to be measured, and finally, as shown in FIG. As shown in (g), the pattern becomes the same as the pattern to be measured P (however, if the scattering F exists in the pattern to be measured P, it is not completely the same). Then, even if the same processing is repeated thereafter, the fourth master pattern M3 does not become larger than the pattern to be measured P.

This is because the pixel outside the edge of the pattern to be measured P is “0”, so that even if the master pattern M4 shown in FIG. Is not "1" as a result of the logical product outside the edge of. Here, the scattering F exists in the pattern to be measured P, but since the scattering F is not connected to the pattern to be measured P, the pixel “1” due to the scattering F does not appear in the fourth master pattern M3.

Next, the first exclusive logic circuit 13 takes the output of the AND circuit 12-n, that is, the exclusive OR of the final fourth master pattern M3 and the pattern P to be measured. The result of the exclusive OR differs depending on whether or not the measured pattern P has scattering. Pattern P to be measured
Is not scattered, the pattern P to be measured and the master pattern M3 are the same, and the exclusive OR results are all "0".

On the other hand, if there is a scattering in the pattern P to be measured, there is a difference between the pattern P to be measured and the master pattern M3, and there is a pixel whose exclusive OR result is "1". Become. In this way, it is possible to detect a splatter present in an area that does not correspond to the second and third master patterns M1 and M2. Then, the image processing device 4 stores the position (the position of F in FIG. 7) at which the result of the exclusive OR is “1” and the defect is recognized.

Next, the inspection (step 110) by comparison with the fifth master pattern will be described. FIG. 9 is a diagram for explaining this inspection method. In the measured pattern P shown in FIG. 9A, the second master pattern M
When the pinhole H exists between the area corresponding to No. 1 and the area corresponding to the third master pattern M2, the above-described inspection cannot detect the pinhole H.

The inverting circuit 14 and the shrinking circuits 15-1 to 15-1 serving as an inspection unit for performing an inspection for comparison with the fifth master pattern
5-n, OR circuits 16-1 to 16-n, and exclusive OR circuit 17 are for detecting such a pinhole H. The inverting circuit 14 has a third master pattern M
2 is logically inverted. As a result, the pixel “1” becomes “0”
Since the pixel “0” becomes “1”, the result of logically inverting the master pattern M2 becomes a pattern M4 in which the pattern edge and the inside thereof are filled with the pixel “1” as shown in FIG. 9B. .

The first contraction circuit 15-1 includes an inversion circuit 14
, That is, the pattern M4 is contracted in a direction perpendicular to the center line L (FIG. 9C). At this time, the contraction circuit 1
Step 5-1 shrinks the pattern M4 by a predetermined number of pixels. Then, the first OR circuit 16-1 is provided with a contraction circuit 15-1.
And the pattern P to be measured is ORed.

The result of the logical sum is the same as the pattern M4 after the contraction processing, and this is added to the fifth master pattern M5.
(FIG. 9D). Second contraction circuits 15-2 to 15-15
-N, the second OR circuits 16-2 to 16-n are formed by connecting a set of a contraction circuit and an OR circuit in a predetermined number of stages (n-1 in the present embodiment) in series. The fifth master pattern M5 is contracted to obtain a logical sum with the pattern P to be measured, and the result of this logical sum is used as a new fifth master pattern M5 a predetermined number of times.

For example, the contraction circuit 15-2 contracts the output of the OR circuit 16-1, that is, the fifth master pattern M5 in a direction perpendicular to the center line L (FIG. 9 (e)).
At this time, the contraction circuit 15-2 contracts the master pattern M5 by a predetermined number of pixels. And the OR circuit 16-2
Takes the logical sum of the output of the contraction circuit 15-2 and the pattern P to be measured.

The result of this OR is the same as the master pattern M5 after the contraction processing, and this is set as a new fifth master pattern M5 (FIG. 9 (f)). When such processing is repeated by the subsequent contraction circuit and OR circuit, the size of the fifth master pattern M5 approaches the size of the pattern P to be measured, and finally, as shown in FIG. It becomes the same as the pattern P to be measured (however, if the pinhole H exists in the pattern P to be measured, it is not completely the same). Then, even if the same processing is repeated thereafter, the fifth master pattern M5 does not become smaller than the pattern P to be measured.

Since the pattern to be measured P is filled with the pixel "1", the master pattern M5 shown in FIG. This is because the result of the logical sum inside the edge never becomes “0”. It should be noted that although the pinhole H exists in the pattern P to be measured,
Is not connected to the edge of the pattern P to be measured,
The pixel “0” due to the pinhole H does not appear in the fifth master pattern M5.

Next, the second exclusive logic circuit 17 takes the output of the OR circuit 16-n, that is, the exclusive OR of the final fifth master pattern M5 and the pattern to be measured P. The result of the exclusive OR differs depending on whether the pattern P to be measured has the pinhole H or not. When there is no pinhole in the pattern to be measured P, the pattern to be measured P and the master pattern M5 are the same, and the exclusive OR results are all “0”.

On the other hand, when the pinhole H exists in the pattern to be measured P, there is a difference between the pattern to be measured P and the master pattern M5, and there is a pixel whose exclusive OR result is "1". Will be. Thus, the second and third
Pinholes H present in areas not corresponding to the master patterns M1 and M2 of FIG. Then, the image processing device 4 stores the position (the position H in FIG. 9) at which the result of the exclusive OR is “1” and the defect is recognized.

After performing the above inspection for the entire pattern to be measured, the image processing device 4 outputs the stored defect position as address information. Second image processing device 5
Compares the pattern to be measured and the first master pattern in a predetermined size centered on the detected defect based on the address information sent from the first image processing device 4 by software processing. Then, an error is obtained, and the pattern to be measured is inspected (step 111).

The comparison inspection between each of the second to fifth master patterns and the pattern to be measured can be realized by hardware.
Only a predetermined area including a detected defect (more precisely, a defect candidate) is inspected by comparing the pattern to be measured, which requires a long processing time, with the first master pattern. Can be inspected. In the present embodiment, the first master pattern is created from the CAD data. However, a pattern to be measured that is determined to be non-defective is imaged, and the first master pattern is created from the pattern to be measured. You may. In this embodiment, each master pattern is contracted and expanded in a direction perpendicular to the center line, but may be contracted and expanded in all directions.

[0061]

According to the present invention, a fourth master pattern is created from a second master pattern for detecting a defect, a pinhole or a disconnection, and a protrusion, scattering or short circuit is detected. A fifth master pattern is created from the third master pattern for use, and an exclusive OR of the measured pattern and the fourth master pattern is calculated, and an exclusive OR of the measured pattern and the fifth master pattern is calculated. By doing so, it is possible to correctly detect defects such as scattering and pinholes existing in areas not corresponding to the second and third master patterns. As a result, the pattern to be measured can be inspected quickly and correctly.

According to the second aspect of the present invention, the pattern inspection apparatus comprises a master pattern creating means and an image processing means, so that the pattern inspection apparatus can inspect the pattern to be measured quickly and correctly. Can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a pattern inspection method according to an embodiment of the present invention.

FIG. 2 is a block diagram of a pattern inspection apparatus.

FIG. 3 is a diagram for explaining a method of creating second and third master patterns.

FIG. 4 is a diagram for explaining a method of aligning a measured pattern and a master pattern.

FIG. 5 is a diagram for explaining an inspection method based on comparison with a second master pattern.

FIG. 6 is a diagram for explaining an inspection method based on comparison with a third master pattern.

FIG. 7 is a diagram for explaining an inspection method based on comparison with a fourth master pattern.

FIG. 8 is a block diagram of an inspection unit that performs inspection by comparison with fourth and fifth master patterns.

FIG. 9 is a diagram for explaining an inspection method based on comparison with a fifth master pattern.

FIG. 10 is a diagram for explaining a conventional inspection method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Green sheet, 2 ... XY table, 3 ... Line sensor camera, 4 ... First image processing apparatus, 5 ... Second image processing apparatus, 6 ... Host computer, 7 ... Display device.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06T 7/00 G01N 21/88 G01B 11/24 H01L 21/66

Claims (3)

(57) [Claims] 1. A first master pattern, which is a reference for comparison with a pattern to be measured, is contracted to create a second master pattern for detecting a defect, a pinhole or a disconnection, and to generate a first master pattern. The pattern is expanded to create a third master pattern for detecting protrusions, splatters or short circuits, and the second master pattern is expanded to obtain a logical product with the pattern to be measured. The fourth master pattern is used as a fourth master pattern for scatter detection in an area not corresponding to the second and third master patterns. The fourth master pattern is subjected to expansion processing to obtain a logical product with the pattern to be measured. A new fourth master pattern is repeated a predetermined number of times, a logical inversion of the third master pattern is obtained, and then contraction processing is performed to obtain a logical sum with the pattern to be measured. The result of the sum is used as a fifth master pattern for pinhole detection in an area not corresponding to the second and third master patterns, and the fifth master pattern is subjected to contraction processing to obtain a logical sum with the pattern to be measured. The result of the OR operation is repeated a predetermined number of times as a new fifth master pattern. The exclusive OR operation of the measured pattern and the fourth master pattern is performed, and the exclusive logical operation of the measured pattern and the fifth master pattern is performed. A pattern inspection method characterized by detecting a defect of a pattern to be measured by taking a sum. 2. A first master pattern, which is a reference for comparison with a pattern to be measured, is contracted to create a second master pattern for detecting a defect, a pinhole or a disconnection, and a first master pattern. A master pattern creating means for creating a third master pattern for detecting protrusions, splatters or short circuits by expanding the pattern, and obtaining a logical product of the second master pattern and the pattern to be measured by expanding the pattern. The result of the logical product is defined as a fourth master pattern for scattering detection in an area not corresponding to the second and third master patterns, and the fourth master pattern is subjected to expansion processing to obtain a logical product with the pattern to be measured. The result of the AND operation is repeated a predetermined number of times as a new fourth master pattern. The result of the logical sum is used as a fifth master pattern for pinhole detection in an area not corresponding to the second and third master patterns, and the fifth master pattern is subjected to a contraction process to perform the pattern measurement. The result of the logical sum is used as a new fifth master pattern a predetermined number of times. The exclusive OR of the measured pattern and the fourth master pattern is calculated, and the measured pattern and the fourth master pattern are calculated. 5. A pattern inspection apparatus, comprising: an image processing means for detecting a defect of a pattern to be measured by taking an exclusive OR of the master pattern of (5). 3. The pattern inspection apparatus according to claim 2, wherein said image processing means includes a first expansion circuit for performing expansion processing of said second master pattern, and an output of said first expansion circuit and a pattern to be measured. A first AND circuit for performing a logical product operation, a second expansion circuit for performing an expansion process on an input pattern, and a second
AND of the output of the expansion circuit and the pattern to be measured
Are connected in series by a predetermined number of stages, and
A first logical operation circuit in which the output of the first AND circuit is connected to the input of the second expansion circuit in the first stage, and an exclusive OR of the output of the second AND circuit in the last stage and the pattern to be measured A first exclusive logic circuit, an inverting circuit for logically inverting a third master pattern, a first shrinking circuit for shrinking a pattern output from the inverting circuit, and an output of the first shrinking circuit. A first OR circuit for calculating a logical sum of the pattern to be measured, a second contraction circuit for contracting the input pattern, and a second contraction circuit
Of the output of the contraction circuit and the pattern to be measured
Are connected in series by a predetermined number of stages, and
A second logical operation circuit in which the output of the first OR circuit is connected to the input of the second contraction circuit in the first stage; and the exclusive OR of the output of the second OR circuit in the last stage and the pattern to be measured And a second exclusive logic circuit that takes the form of: