JP2977946B2 - Dielectric-based transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor,
In particular, the present invention relates to a dielectric base transistor using a dielectric as a base region instead of a semiconductor.

2. Description of the Related Art In the field of electronic devices for information processing represented by computers, transistors for amplifying or switching electric signals play an important role. Transistors can be made not only with conventional semiconductor materials, but also with other materials such as metals, derivatives, oxides,
If it can be configured using a metal superconductor, an oxide superconductor, or the like, the range of application of the transistor is expanded,
It is considered useful in industry.

[0003]

2. Description of the Related Art The present inventor has proposed a dielectric base transistor as a transistor using a dielectric. The dielectric base transistor is a general term for a transistor using a dielectric in a base region.

In one form of a dielectric base transistor, an emitter electrode and a collector electrode are in contact with a high dielectric constant dielectric base region via a thin tunnel barrier layer. A base electrode is in direct contact with the base region having a high dielectric constant, and the potential applied to the electrode controls the potential of the dielectric base region. When the potential of the dielectric base region changes,
Carriers tunnel from the source electrode to the dielectric base region via the thin tunnel barrier layer. The tunneled carriers travel through the dielectric base region and are extracted from the collector electrode through a thin tunnel barrier layer.
When the potential of the dielectric base region changes, the amount of carriers injected by tunneling the tunnel barrier layer from the source electrode to the dielectric base region changes, so that the transistor current is controlled.

FIG. 2 shows an example of a conventional planar dielectric base transistor. The planar type refers to a structure in which the emitter electrode and the collector electrode are in contact with the surface on the same side of the dielectric base region. FIG. 2A shows the configuration,
FIG. 2B shows the IV characteristics.

In FIG. 2A, a dielectric base region 21 is constituted by an SrTiO ₃ substrate. In addition,
Dielectric base region 21 has a thickness of, for example, about 500 μm. SrTiO ₃ has a relative dielectric constant of about 250 at room temperature and a relative dielectric constant of about 20,000 at 4.2K. On one surface of the dielectric base region 21, an emitter tunnel barrier layer 22 and a collector tunnel barrier layer 25 made of, for example, a Si layer having a thickness of about 6 nm are arranged. On these emitter tunnel barrier layer 22 and collector tunnel barrier layer 25, an emitter electrode 23 and a collector electrode 26 formed of, for example, an Nb film are arranged. The emitter electrode 23 and the collector electrode 26 each have a size of, for example, 20 μm × 40 μm, and are arranged with a gap of about 2 μm therebetween. The emitter electrode 23 and the collector electrode 26 are covered with an insulating layer 28 made of SiO ₂ or the like, and an opening is formed in the insulating layer 28 to expose a contact region between the emitter electrode 23 and the collector electrode 26. For example, N
b, emitter lead 24 and collector lead 2
7 contact and extend over the insulating layer 28. On another surface of dielectric base region 21, base electrode 30 formed of, for example, Pt paste is formed.

When the emitter electrode of the dielectric base transistor shown in FIG. 2A is grounded and a proper bias voltage is applied to the base electrode and the collector electrode, the emitter electrode 23
, A current flows to the collector electrode 26.

FIG. 2B shows an IV characteristic of a change in the collector current Ic with respect to a change in the collector voltage Vc, using the base voltage Vb as a parameter. For example, the base voltage V
When b = 1V, as the collector voltage Vc increases, the collector current Ic gradually increases as Vc increases.
As the base voltage Vb increases, the collector current Ic flows more.

The dielectric base region 21 has an insulating band structure and hardly allows a current to flow, so that the base current is negligibly small. For this reason, the current amplification factor of the dielectric base transistor as shown in FIG.

When the collector electrode Ic is fixed, the change in the collector voltage Vc caused by the change in the base voltage Vb is about 2-3 times. That is, a value of about 2 to 3 is obtained as the voltage gain.

[0011]

The dielectric base transistor shown in FIG. 2 has a problem that the voltage gain is low.

An object of the present invention is to provide a dielectric base transistor having a novel structure.

Another object of the present invention is to provide a dielectric base transistor capable of increasing a voltage gain.

[0014]

A dielectric base transistor according to the present invention has a dielectric base region formed of a dielectric having an insulating band structure and a large dielectric constant, and a dielectric base region formed on the dielectric base region. An insulating film having an opening, an emitter tunnel barrier layer and a collector tunnel barrier layer that are disposed on the insulating film, extend over the dielectric base region at the opening, and have a thickness that allows carriers to tunnel. An emitter electrode disposed on the emitter tunnel barrier layer and extending into the opening, formed of a conductive material; and an emitter electrode disposed on the collector tunnel barrier layer and extending into the opening, the conductive material And a base electrode disposed on the dielectric base region and formed of a conductive material.

[0015]

An insulating film having an opening is arranged on the dielectric base region, and the effective area of the collector electrode is limited by the opening. Therefore, it is easy to obtain a high voltage gain. When placing the emitter and collector electrodes in a single opening,
Since the emitter electrode and the collector electrode can be arranged close to each other and the effective area of the collector electrode can be easily limited, a dielectric base transistor which can operate at high speed and has a high voltage gain can be manufactured.

[0016]

First, referring to FIG. 3, the performance of a conventional dielectric-based transistor will be analyzed.

FIG. 3A is a schematic structural diagram in which main components of a planar dielectric base transistor are extracted. A stack of an emitter tunnel barrier layer 22 and an emitter electrode 23 is formed on the dielectric base region 21, and a stack of a collector tunnel barrier layer 25 and a collector electrode 26 is formed at a predetermined distance on the same surface. The base electrode 30 is in contact with the other surface of the dielectric base region 21. In this configuration, the main current is
Reaches the dielectric base region 21 via the emitter tunnel barrier layer 22, travels through the dielectric base region 21, and passes through the collector tunnel barrier layer 25 to the collector electrode 26.
Drawn to. FIG. 3B shows a potential profile along this current path.

In FIG. 3B, the emitter tunnel barrier layer 22 forms a potential barrier for carriers in the emitter electrode 23. The potential barrier has such a thickness that carriers can be tunneled. Dielectric base region 2
The potential of 1 is capacitively controlled by the base electrode applied to the base electrode 30. When the potential of the dielectric base region 21 decreases, the emitter electrode 23
Carriers inside are tunneled through the potential barrier of the emitter tunnel barrier layer 22 and injected into the dielectric base region 21. The dielectric base region 21 itself has an insulating band structure and does not have free carriers. However, if carriers are injected, the carriers can be transported. A collector tunnel barrier layer 25 is arranged between the dielectric base region 21 and the collector electrode 26, and the dielectric base region 2
1 forms a potential barrier for the carriers in 1. The barrier height of the potential barrier can be controlled by the collector voltage applied to the collector electrode 26. When the amount of carriers injected from the emitter electrode 23 into the dielectric base region 21 increases, the carriers are accumulated in the dielectric base region 21 and eventually flow to the collector electrode 26. In such a configuration, the amount of carriers injected from the emitter electrode 23 into the dielectric base region 21 is controlled by
This is the potential of the dielectric base region 21. How the potential of the dielectric base region 21 is controlled will be analyzed with reference to FIG.

The emitter tunnel barrier layer 22, the dielectric base region 21, and the collector tunnel barrier layer 25 have an insulator or an insulating band structure, and have almost no free carriers. The potential in the dielectric base region 21 is determined by the emitter electrode 23, the collector electrode 26,
It can be considered that it is determined by capacitive coupling to the base electrode 30. Therefore, in order to consider the mechanism for determining the potential in the dielectric base region of the dielectric base transistor, consider an equivalent circuit as shown in FIG. The dielectric base region 21 has a very large relative permittivity, for example, 100 or more, while the tunnel barrier layers 22, 25
Usually has a relative dielectric constant of about 10, so that the potential in that region is almost constant. A point P in the dielectric base region 21 is capacitively coupled to the emitter electrode E, the collector electrode C, and the base electrode B by capacitances Ce, Cc, and Cb.

Assume that the emitter tunnel barrier layer 22 and the collector tunnel barrier layer 25 are formed of layers having a thickness d and a relative dielectric constant ε1, and their effective areas are SE and SC, respectively. Then, the capacitance Ce between the point P in the dielectric base region 21 and the emitter electrode E is Ce = (ε1 / d)
SE and the capacitance Cc between the point P and the collector electrode C
Can be approximated as Cc = (ε1 / d) SC. When the emitter electrode and the collector electrode can be approximated together by a circle having a diameter of about R, the capacitance Cb between the point P in the dielectric base region 21 and the base electrode B can be approximated as Cb = 2Rε ₂ .
Here, ε ₂ is the relative dielectric constant of the dielectric base region 21. At this time, the area SE and SC is proportional to R ^2.

Assuming that the voltages of the emitter electrode E, the collector electrode C, and the base electrode B are VE, VC, and VB, respectively, the voltage amplification factor μ is the ratio of the change in the collector voltage to the change in the base voltage when the collector current is constant. And can be expressed as μ = ∂VC / ∂VB. When the point P in the dielectric base region 21 is set at the center of the emitter electrode and the collector electrode, and the potential is represented by V, μ = XB / XC, XB = ∂V / ∂VB, and XC = ∂V / ∂VC. be able to. To increase the voltage gain μ, XB may be increased and XC may be decreased. XB is
The degree to which the potential V at the point P in the dielectric base region changes due to the change in the potential VB of the base electrode B is proportional to Cb. XC represents the degree of change in the potential V at the point P in the dielectric base region due to the change in the potential VC of the collector electrode C, and is proportional to Cc. Since Cb in simplified model described above is proportional to R, Cc is proportional to R ^2, the mu 1
/ R.

From another viewpoint, when the base capacitance Cb is increased and the collector capacitance Cc is decreased, μ increases.
In order to increase the base capacitance Cb, it is effective in the above-described model to increase the one-dimensional size (diameter) of the emitter electrode and the collector electrode or to increase the relative dielectric constant ε2. The relative permittivity ε2 is determined by the type of the dielectric. When the collector electrode is enlarged, the area becomes larger than the diameter. In order to reduce the value of the collector capacitance Cc,
It is effective to reduce the relative permittivity ε1 of the collector tunnel barrier layer 25 and increase the thickness d, or to reduce the effective area SC of the collector electrode 26. The relative permittivity ε1 is determined by the material of the collector tunnel barrier layer. The thickness d is limited by the thickness of the collector tunnel barrier layer and cannot be too large to allow tunneling. Possibility of remaining is the effective area SC of the collector electrode 26.
Is to reduce the Therefore, the conclusion obtained is the same: to make the collector electrode 26 smaller.

FIG. 1 is a sectional view showing the structure of a dielectric base transistor according to an embodiment of the present invention. FIG. 1 (A),
(B) shows different forms.

In FIG. 1A, a dielectric base region 1
Has a relative dielectric constant of 100 or more, preferably as high as possible. For example, it is formed of an oxide dielectric such as SrTiO ₃ or a material in which Ti acid is replaced with acids of Ta, Sn, Zr, and Nb, a material in which Sr is replaced with K, or a combination thereof. On the surface of dielectric base region 1, an insulating film 2 formed of, for example, a SiO ₂ film having a thickness of about 200 nm is arranged. Openings 3a and 3b are formed in the insulating film 2, and the dielectric base region 1 is exposed in the openings. Opening 3
a and 3b each are, for example, about 2 μm × 2 μm,
The width of the insulating film 2a disposed between the openings 3a and 3b is, for example, about 2 μm. On the insulating film 2 having the openings 3a and 3b, an emitter tunnel barrier layer 6, a collector tunnel barrier layer 9 formed of, for example, a SiO ₂ film having a thickness of about 2 nm, and an emitter electrode formed thereon and formed of a Ta layer. 5, a stack of collector electrodes 8 is arranged. On the lower surface of the dielectric base region 1, a base electrode 7 formed of a Ta layer is formed.

According to the configuration shown in FIG. 1A, the effective areas of the emitter electrode 5 and the collector electrode 8 can be substantially determined by the areas of the openings 3a and 3b of the insulating film 2. By limiting the area of the opening 3b for the collector electrode 8, the parasitic capacitance Cc of the collector electrode 8 can be reduced, and the voltage gain can be increased.

In the configuration shown in FIG. 1A, the effective portion of the emitter electrode 5 and the effective portion of the collector electrode 8 are separated by the central region 2a of the insulating film 2. Therefore, the effective length of the current path 10 from the emitter electrode 5 to the collector electrode 8 cannot be shorter than the width of the central portion 2a of the insulating film 2. The width of the central portion 2a of the insulating film 2 must have a value necessary for forming the emitter electrode 5 and the collector electrode 8 thereon and electrically separating them.

To improve the performance of a transistor,
It is considered primarily important in improving the performance of the information processing apparatus. In particular, an improvement in the switching speed of the transistor directly leads to an improvement in the processing speed of the information processing device. There are various methods to increase the speed of transistors,
One of the important factors is miniaturization and miniaturization of element dimensions.
If the element size is reduced, the capacitance and inductance are reduced accordingly, which is effective for speeding up. In addition, higher speed can be expected by reducing the traveling distance of carriers in the transistor.

FIG. 1B shows an example of a structure which is effective by downsizing the transistor. In this configuration, the insulating film 2 has only a single opening 3c. A stack of the emitter tunnel barrier layer 6 and the emitter electrode 5 and a stack of the collector tunnel barrier layer 9 and the collector electrode 8 are formed so as to be in contact with the dielectric base region 1 in the opening 3c. In this case, the gap size between the emitter electrode 5 and the collector electrode 8 is limited by the minimum lithography size.

According to the structure shown in FIG. 1B, it is easy to arrange the emitter electrode 5 and the collector electrode 8 closer to each other. For example, emitter electrode 5 and collector electrode 8 are arranged with a gap of about 0.5 μm. The area of the opening 3c is, for example, about 2 μm × 2 μm. The other points are the same as the structure shown in FIG.

In the example of the configuration shown in FIG. 1B, compared to the voltage gain of the conventional configuration shown in FIG.
A voltage gain of 0 times can be obtained.

When the area of the collector electrode is sufficiently reduced in such a configuration, a transistor having a voltage gain can be obtained without providing a collector tunnel barrier layer. In a transistor without a collector tunnel barrier layer, carriers are more quickly transported from the emitter to the collector.

FIG. 4 shows a dielectric base transistor according to another embodiment of the present invention. 4A to 4C show examples of different embodiments.

In FIG. 4A, the dielectric base region 1c is formed of a SrTiO ₃ : Nb substrate in which about 0.001% of Sr atoms have been replaced with Nb atoms. When the Sr atom is replaced with Nb, the replaced Nb atom functions as a donor. Donna emits electrons,
It is positively charged.

The dielectric base region 1c has a thickness of about 25 at room temperature.
At 0 ° C., the potential in the dielectric base region 1c is substantially constant because of a large relative dielectric constant of 0 or more at low temperatures.
Therefore, the donor in the dielectric base region 1c has a function of lowering the potential of the entire dielectric base region 1c for electrons. For this reason, even when the potential applied to the gate electrode 7 is near 0, the potential of the surface portion of the dielectric base region 1c constituting the channel can be set to a low value of several meV to several tens meV suitable for tunneling. . Therefore, the dielectric base transistor can be operated even when the gate electrode is near zero bias. Other points are the same as those of the embodiment shown in FIG.

In the structure shown in FIG. 4B, the dielectric base region is constituted by a region 1c doped with dona and a region 1d not doped with dona. For example,
A dielectric base region 1d close to the emitter electrode 5 and the collector electrode 8 is formed by an SrTiO ₃ single crystal region not doped with an impurity such as a donor, and a deeper region is formed by an SrTiO ₃ region doped with Nb as a donor. .

When the dielectric base region 1d near the emitter electrode 5 and the collector electrode 8 is formed of a region not doped with a donor impurity, impurity scattering is suppressed and high carrier mobility can be obtained. Also, if the concentration of the donor impurity is excessively increased, carriers that contribute to normal conduction may be generated, and normal operation as a tunnel transistor may not be performed.However, doping of the channel portion with the donor impurity should not be performed. This alleviates such a problem. The potential of the dielectric base region 1d is controlled by the dielectric base region 1c doped with a donor impurity, similarly to the embodiment shown in FIG.

SiO ₂ as a collector tunnel barrier layer
Has been described, but it is sufficient that the collector tunnel barrier layer can flow a sufficient current and has a small capacity per unit area. For this purpose, a material having a small dielectric constant and a low barrier height is preferable. In addition to SiO ₂ , for example, semiconductors such as Si, Ge, and InSb can be used. It is also considered that oxides such as Al ₂ O ₃ and MgO can be used.

In these configurations, the emitter electrode, the collector electrode, and the base electrode are each formed of a high-temperature oxide superconductor, YBa ₂ Cu ₃ Ox (YBCO), and the emitter tunnel barrier layer and the collector tunnel barrier layer are formed. It can also be formed of YAlO ₃ . The use of a superconductor for the electrode has the advantage that the electrode resistance becomes zero. Further, better transistor sensitivity can be obtained due to the nature of the state density of the superconductor. Further, instead of the oxide high-temperature superconductor, a metal-based superconductor such as Nb or Pb alloy can be used.

Although the description has been given of the case where a material containing SrTiO ₃ as a main component is used as a channel material for forming the dielectric base region, another dielectric having a high dielectric constant may be used. For example, as a channel material, KTa _1-x Nb _X O
₃ can also be used. In this case, the temperature at which the dielectric constant becomes maximum can be adjusted by changing the ratio x of Nb. For example, when the composition x is adjusted so that the dielectric constant becomes maximum at the liquid nitrogen temperature, a dielectric base transistor having good characteristics at the liquid nitrogen temperature can be designed. To maximize the dielectric constant at liquid nitrogen temperature,
The composition x may be set to about 0.05. At this time, KTa _1-x
The relative dielectric constant of Nb _X O ₃ is tens of thousands.

When the dielectric base region is a substrate, the potential in the substrate becomes substantially constant. To configure an integrated circuit, it is necessary that the potential of the dielectric base region can be independently controlled in each transistor.

FIG. 4C shows a structure of a dielectric base transistor suitable for forming an integrated circuit. A substrate 12 made of MgO is used, and a dielectric base transistor structure is formed thereon. On the MgO substrate 12, Y
Base electrode 7 formed of BCO (YBa ₂ Cu ₃ Ox)
Is deposited, and an SrTiO ₃ film 1b is formed thereon by, for example, high frequency (rf) magnetron sputtering.
The dielectric film 1b forms a dielectric base region. After patterning the dielectric base region 1b and the base electrode 7, an insulating film 2 formed of SiO ₂ or the like is deposited,
An opening 3c is formed on the dielectric base region 1b. Thereafter, as in the above-described embodiment, an emitter tunnel barrier layer 6, a collector tunnel barrier layer 9 that contacts the dielectric base region 1b within the opening, and an emitter electrode 5 and a collector electrode 8 disposed thereon are formed.

According to the structure shown in FIG. 4C, even when a plurality of dielectric base transistor structures are formed on the substrate 12, it is possible to prevent the potentials in the respective transistor structures from interfering with each other. it can. Therefore, a large number of transistors can be integrated over the same substrate.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
The electrode material, insulating film material, tunnel barrier layer material, dielectric material and the like are not limited to those described above. Other various changes,
It will be obvious to those skilled in the art that improvements, combinations, and the like are possible.

[0044]

As described above, according to the present invention,
A novel configuration of a dielectric base transistor is provided.

Since it is easy to limit the effective area of the collector electrode to a small value, a dielectric base transistor having a high voltage gain can be provided.

Since it is easy to reduce the distance between the effective regions of the emitter electrode and the collector electrode, a dielectric base transistor that operates at high speed can be provided.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1 (A), (B)
FIG. 3 is a cross-sectional view showing a dielectric base transistor of a different mode.

FIG. 2 shows a conventional technique. FIG. 2A is a cross-sectional view illustrating the configuration, and FIG. 2B is a graph illustrating IV characteristics.

FIG. 3 is a diagram for analyzing characteristics of a dielectric base transistor. FIG. 3A is a schematic cross-sectional view showing the structure,
FIG. 3B is a graph showing a potential profile,
FIG. 3C is a diagram showing an equivalent circuit.

FIG. 4 shows another embodiment of the present invention. FIG. 4 (A),
(B), (C) is a schematic sectional view showing a dielectric base transistor of a different form, respectively.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 dielectric base region 2 insulating film 3 opening 5 emitter electrode 6 emitter tunnel barrier layer 7 base electrode 8 collector electrode 9 collector tunnel barrier layer 10 current path 21 dielectric base region 22 emitter tunnel barrier layer 23 emitter electrode 24 emitter lead 25 collector Tunnel barrier layer 26 Collector electrode 27 Collector lead 28 Insulating layer 30 Base electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/68-29/737 H01L 39/22-39/24 H01L 49/00

Claims (6)

(57) [Claims] A dielectric base region formed of a dielectric having an insulating band structure and a large dielectric constant; and an insulating film formed on the dielectric base region and having an opening. (2) an emitter tunnel disposed on the insulating film, extending over the dielectric base region at the opening, having a thickness allowing tunneling of carriers, and having a dielectric constant smaller than the large dielectric constant; Barrier layer (6)
An emitter electrode (5) disposed on the emitter tunnel barrier layer and extending into the opening and formed of a conductive material; and an emitter electrode (5) extending into the opening and electrically connected to the dielectric base region. A dielectric base transistor having a collector electrode (8) formed of a conductive material and a base electrode (7) formed of a conductive material disposed on the dielectric base region. 2. The dielectric base transistor according to claim 1, wherein said dielectric base region contains an impurity for providing a fixed charge. 3. The dielectric base transistor according to claim 2, wherein said impurity for giving said fixed charge is selectively doped in a region apart from a region connecting said emitter electrode and said collector electrode. 4. The method according to claim 1, wherein the emitter electrode, the collector electrode,
4. The dielectric base transistor according to claim 1, wherein at least one of said base electrodes is formed of a material having superconductivity. 5. The method according to claim 1, wherein the dielectric is S
The dielectric-based transistor according to any one of claims 1 to 4, wherein the oxide is an oxide containing any of r, Ti, K, Ta, Sn, Zr, and Nb. 6. The dielectric base transistor according to claim 1, wherein said dielectric base region is formed of a film deposited on a substrate having a dielectric constant smaller than said large dielectric constant.