JP2002009254A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device, capable of using an advantageous semiconductor process in respect of manufacturing cost and mass productivity as the base, and which is low power consumption type where various kinds of single electronic transistors are used for a readout circuit, moreover, where refinement and large scale integration are possible and storage system can be selected easily. SOLUTION: A high conductivity layer 113 is disposed on a semiconductor substrate 111, a carrier accumulation layer 114 is disposed on the high conductivity layer, and a single electronic transistor 120 capable of detecting electrical charges captured in the carrier accumulation layer 114 is disposed on the of it. The write/erase operation of a memory is performed by potential change in the layer 113. The layer 113 formed on the substrate 111 where electrostatic capacity between the transistor 120 and an island 123 is constant, performs the write/erase operation. The layer 114 formed in lamination us used for a storage medium. The transistor 120 formed on the upper side, performs reading. Thus, there is achieved the architecture of a semiconductor storage circuit enabling low power consumption and high integration, and having high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a layered structure in which a carrier injection control is performed in a vertical direction of a substrate, and a single electron transistor as a charge detecting element having low power consumption is disposed on the semiconductor memory device. The present invention relates to a low power consumption semiconductor memory device having a small cell size and high integration that has a structure.

[0002]

2. Description of the Related Art As a first conventional example of a conventional semiconductor memory device, a nonvolatile memory element using a single-electron transistor in a read circuit is given. It is a known fact about the operating principle of single-electron transistors, such as the IEEE Trans
actions on Magnetics, Vol.MAG-23, No. 2, 1142 (19
87) (by KK Likharev). A single-electron transistor is a highly sensitive charge meter that can detect even a small change in charge, that is, a change of 10 ⁻⁶ in terms of the number of electrons, so that the number of charges stored in a storage medium is small. . This is because the Coulomb blockade oscillation characteristic, which is a characteristic of a single-electron transistor, is sensitively changed by electric charges stored in a memory node located near the single-electron transistor. Using this principle, the ON / OFF state of a single-electron transistor changes depending on the presence or absence of charge stored in a memory node,
A semiconductor memory device with low power consumption can be formed. Non-volatile memory elements using a single-electron transistor for a readout circuit, which have been reported so far, are mainly manufactured based on a metal-based material. For example, Physical Review Letter
s, Vol. 72, 904 (1994) (by Dresselhaus et al.) is a typical example.

Next, as a second conventional example, reference
An example is the single-electron memory reported in the Fall Meeting of the Japan Society of Applied Physics, 17a-ZK-7. This will be described with reference to the element structure diagram of FIG. 7 and the principle diagram of the read operation of FIG.

(Element structure) In FIG. 7, (a) is a plan view, (b) is a sectional view taken along the line aa ′, and the semiconductor memory device 210 is mounted on a semiconductor substrate 212 such as silicon, which is opposite to the substrate. A drain 213 and a source 214 which are heavily doped in the mold are formed. An element isolation film 215 is formed so as to cover them. An element active region 220 is opened in the element isolation film 215 so that only a part of the surface of the substrate 212 and the drain 213 and the source 214 is exposed. Further, the device isolation film 21
5 through the hole provided in the drain 213 and the source 21.
4, a drain electrode 227 and a source electrode 228 are formed. The element insulating region 220 is covered with a first insulating layer 216 made of a silicon oxide film. On the first insulating layer 216, a second insulating layer 21 made of a silicon nitride film having a carrier trapping center is formed.
7 is coated, and a third insulating layer 218 is coated on the second insulating layer 217. A single-electron transistor 219 is formed on the three insulating multilayer structures formed on the device active region 220. The single-electron transistor 219 includes two tunnel barriers 222 and 224, and these tunnel barriers 222 and 22.
4, an island 223 electrically insulated from the drain 221 and the source 225, and the gate electrode 22.
Consists of six.

(Programming Operation) The programming operation of the electrically variable semiconductor memory device 210 will be described. Here, it is assumed that carriers used for storage are electrons. At this time, the semiconductor substrate 212 used for the storage device 210 is a p-type semi-insulating substrate, and the drain 213 and the source 214 are doped n-type. When the carrier used for storage is a hole, the voltage applied to each electrode has the opposite sign. When programming the storage device 210, a positive voltage Vd is applied to the drain electrode 227 and the source electrode 228 is grounded. As a result, a positive voltage of Vd is applied to the drain 213 of the storage device 210, and the source 214 is grounded. In this state, all of the electrodes connected to the single-electron transistor 219, that is, the drain 221, the source 225, and the gate 226 are applied to a positive voltage of Vg. Then, a channel layer is induced on the surface of the substrate 212 by the principle of the field effect transistor, and
Electrons flow toward 3 and the so-called field-effect transistor is turned on. In this state, all the electrodes connected to the single-electron transistor 219 and the electrons present in the channel layer induced on the surface of the substrate 212 by the electric field generated between the semiconductor substrate 212 and the first insulating film Injected into the second insulating film 217 by a tunnel process through 216. The injected electrons are converted into the second insulating film 2
The electrons are induced in the 17 conduction band, and some of the electrons are trapped in the trapping center. As described above, the capture center in the second insulating film 217 is negatively charged, and the programming operation is performed. The third insulating layer 218 prevents electrons from penetrating from the second insulating film 217 to the single electron transistor 219 side, so that the electrons are efficiently captured at the capture center. In addition, since injection of holes from the gate electrode side can be prevented, captured electrons are prevented from being neutralized.

(Erase Operation) The erase operation of the electrically variable semiconductor memory device 210 will be described. here,
It is assumed that carriers used for storage are electrons. In the case of a hole, the voltage applied to each electrode has the opposite sign. When erasing the storage contents of the storage device 210, all the electrodes connected to the single-electron transistor 219, that is, the drain 221, the source 225, and the gate 226 are connected to -V.
g, and the semiconductor substrate 212 is set to the ground potential. The electric field generated between all the electrodes connected to the single-electron transistor 219 and the semiconductor substrate 212 causes
The electrons captured by the capture center in the second insulating film 217 are
By a tunnel process through the first insulating film 216,
It is injected into the substrate 212. Thereby, the second insulating film 2
There is no electron at the capture center 17. The third insulating layer 218 is formed from the single electron transistor 219 side by the nitride film 2.
17 can be prevented from being injected with electrons, and electrons can be efficiently extracted from the capture center.

(Read Operation) In the read operation for detecting the programming operation and the erasing operation, the single electron transistor 219 is used. The operating principle of the single-electron transistor 219 is a known fact as described in the first conventional example of the prior art. When the voltage VW is applied to the gate 226 of the single-electron transistor 219, the source 225 is grounded, and VD is applied to the drain 221, the current I flowing to the drain 221 is as shown in FIG. This current oscillation is known as Coulomb blockade oscillation, and is due to the Coulomb blockade effect, which reflects a change in the charge amount Q induced in the island 223 by the voltage VW applied to the gate 226. On the other hand, the amount of charge QT stored in the capture center changes due to writing and erasing operations in the semiconductor memory device. Due to this charge amount QT, the island 2
Charge is induced in the capacitor between 23 and the capture center. Due to the induced charges, the value of the gate voltage VW at which the current I flowing through the drain 221 of the single-electron transistor 219 becomes maximum changes as compared with the case where there is no charge. This state is shown as voltages V1 and V2 in FIG. The reading operation is performed by utilizing the phenomenon that the value of VW at which the current I becomes maximum changes due to the above-described accumulated charge QT. For example, if the maximum charge of the current I is shifted by half a cycle, the charge
By erasing, an on state in which a current flows and an off state in which a current does not flow are changed, and this may be detected by a differential amplifier circuit or the like.

[0008]

In the first prior art semiconductor memory device, low power consumption operation has been enabled by using a single electron transistor. It is complicatedly formed in the same plane, and has a disadvantageous structure from the viewpoint of integration. Also, it has been difficult to control the capacitance between the island of the single electron transistor formed in the plane and the memory node. In this regard, in the second conventional example, by combining a single-electron transistor with a carrier trapping center in an insulating film formed in a layer on a semiconductor substrate, a semiconductor nonvolatile memory that can be highly integrated with low power consumption is provided. Sex storage devices can now be formed. In addition, by providing a tunnel oxide film with high film thickness controllability,
The erasing characteristics can be controlled uniformly on the semiconductor substrate.

However, in the second conventional example,
There were the following issues. Specifically, there are a problem of a substrate gate for controlling a writing / erasing operation and a problem of a complicated element structure due to the use of a field effect transistor. These two points will be described below. Regarding the first problem, in the second conventional example, writing / writing is performed using an electric field applied between the semiconductor substrate and the single-electron transistor.
Although erasing is taking place, this electric field also affects the characteristics of the single-electron transistor due to the capacitance between the semiconductor substrate and the island of the single-electron transistor. In addition, due to effects such as formation of a channel layer, the capacitance between the semiconductor substrate and the island of the single-electron transistor may change due to an electric field in the device. Furthermore, this effect can also be caused by a change in element temperature. This change in capacitance between the semiconductor substrate and the island of the single-electron transistor results in a change in the effective distance between the semiconductor substrate and the island of the single-electron transistor. That is, at the time of the programming / erasing operation, not only the programming / erasing operation but also other field effects are detected by the single electron transistor. For the above reasons, an element structure for maintaining a constant capacitance between the semiconductor substrate and the island of the single-electron transistor is required. The second problem is that the element structure becomes complicated due to the use of the field-effect transistor. Is also a problem. This leads to an increase in the element area while increasing the number of steps in the element manufacturing process. A field-effect transistor-type element structure requires the formation of a region into which an element of the opposite type to the ions mixed into the semiconductor substrate is implanted. The single-electron element has a large element area and is advantageous for miniaturization. There is a possibility that the advantage of using a transistor cannot be used.

An object of the present invention is to use a semiconductor process which is advantageous in terms of manufacturing cost and mass productivity as a base, and to use a single-electron transistor of various kinds in a read circuit for a low power consumption type and miniaturization. Another object of the present invention is to provide a highly reliable semiconductor memory device capable of large-scale integration.

[0011]

A semiconductor device memory device according to the present invention comprises a semiconductor substrate, a high conductivity layer formed on the semiconductor substrate, and a carrier accumulation layer formed on the high conductivity layer. And a single-electron transistor formed on the carrier accumulation layer. That is, the single electron transistor formed on the carrier storage layer detects the charge trapped in the carrier storage layer, and the writing / erasing operation of the memory is performed by the potential change of the high conductivity layer. In the present invention, writing / writing is performed using a high-conductivity layer formed on a semiconductor substrate having a constant capacitance between the island of a single-electron transistor.
By performing erasing, using a carrier storage layer formed in a layered form as a storage medium, and performing reading with a single-electron transistor formed on the storage medium, low power consumption and high integration are possible. Thus, a semiconductor memory circuit having high reliability can be configured.

Further, the semiconductor memory device of the present invention can be configured as follows. A first insulating layer exists between the semiconductor substrate and the high conductivity layer. Further, the high conductivity layer exists only below the memory cell region defined by the single electron transistor and the peripheral region. In this case, a second insulating layer exists between the high conductivity layer and the carrier accumulation layer. Further, in this case, a third insulating layer exists between the carrier accumulation layer and the single electron transistor.

The high-conductivity layer comprises one of a heavily doped silicon-on-insulator layer, a heavily doped polysilicon layer, and a metal layer. Further, the semiconductor substrate is made of silicon, and the carrier accumulation layer is made of a multilayer structure of silicon nitride and a silicon oxide film, or a multilayer structure of particles made of silicon and a silicon oxide film.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below together with specific data. [First Embodiment] FIGS. 1A and 1B are a plan view and a sectional view taken along line aa 'of a first embodiment of a semiconductor memory device according to the present invention. In this semiconductor memory device 110, a high conductivity layer 113 and a carrier accumulation layer 114 are stacked on a semiconductor substrate 111 such as silicon. The high conductivity layer 113
May be, for example, semiconductor silicon or metal aluminum, and in the case of silicon, a p-type or n-type is 1 × 10 ¹⁹ / c
It is desirable to dope from m ³ to about 1 × 10 ²¹ / cm ³ . The high conductivity layer 113 has a thickness of 30 to
A thickness of about 500 nm is desirable. The carrier accumulation layer 114 can hold carriers, and may be, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, particles made of silicon such as polysilicon particles, and a multilayer film made of these, A thickness of about 5 nm to 50 nm is desirable.

Further, a single electron transistor 120 is formed on the carrier accumulation layer 114. This single-electron transistor 120 has two tunnel barriers 122 and 124 and a drain 1
21, an island 123 electrically insulated from the source 125, and a gate electrode 126. The drain 121 and the source 125 of the single electron transistor 120,
Although the material of the island 123 and the gate 126 is not limited, for example, an aluminum layer can be used. The thickness of the aluminum layer may be about 10 nm to 100 nm. The width and depth of the island 123 are, for example, 50 nm or less, respectively. Tunnel barriers 122, 124
Is a barrier for conduction electrons or holes, and the height of the barrier is desirably 1 eV or more.

A specific example of the formation of the semiconductor memory device 110 will be described with reference to FIGS. In FIG. 2, (a1) to (e1) are cross-sectional views, and (a2) to (e2) are plan views. First, (a
As shown in 1) and (a2), a silicon substrate 111 having a plane orientation of (100) is prepared. The substrate has a phosphorus concentration of 1 × 1
Ion implantation is performed so as to be about 0 ¹⁹ / cm ³ to about 1 × 10 ²¹ / cm ³ . The thickness of the ion-implanted silicon may be about 30 nm to 500 nm. Thus, the high conductivity layer 113 is formed. On this structure, (b
As in 1) and (b2), a carrier accumulation layer 114 having a thickness of 5 nm to 50 nm is grown by a normal semiconductor process technique. This layer may be, for example, a silicon nitride film grown by a plasma vapor deposition method or a low pressure vapor deposition method. In this way, a carrier accumulation layer serving as a memory node is formed.

Next, as shown in (c1) and (c2), a positive photoresist (not shown) is applied on the carrier accumulation layer 114, and a region to be a contact hole is exposed using a conventional ultraviolet exposure. Then, development is performed. Using this positive photoresist as a mask, the carrier accumulation layer 114 is etched to form a contact hole 151. In the etching, an etchant used in a conventional semiconductor manufacturing process, for example, buffered hydrofluoric acid is used. Again, a positive photoresist (not shown) is applied, and a wiring pattern for connecting the device to the outside is exposed using conventional ultraviolet exposure, and development is performed. Then, a metal such as aluminum is deposited in a thickness of 100 nm to 300 nm, and the metal on the photoresist is removed by a lift-off method.
1) and (d2), the single-electron transistor 120
152 and high conductivity layer 113 for making connection to
The electrode 153 is formed.

On the substrate thus formed, (e1),
As shown in (e2), the single electron transistor 120 is formed. The single-electron transistor 120 is formed by, for example, a conventional lift-off method using a three-layer resist. For example, referring to FIG. 6, first, PMMA / G
A three-layer resist of e / PMMA is formed, and a resist pattern having a width of several nm to several hundred nm and a length of several nm to several μm is formed on the upper layer PMMA using electron beam irradiation, and Ge is used as a mask by using this as a mask. Dry-etch. Furthermore, Ge
Is used as a mask to dry-etch the lower layer of PMMA vertically and rotationally to form side-etched cavities.
At this time, the PMMA in the upper layer is removed by etching, and the resist layer is in the state shown in FIG. Then, aluminum is vapor-deposited in the vertical direction (1) by the resist pattern composed of the remaining two layers of Ge / PMMA resist, and an island 12 is formed on the surface of the carrier accumulation layer 114.
Form 3 Next, the surface of the island 123 is oxidized to form a tunnel barrier 12 made of aluminum oxide.
2, 124 are formed. Further, this time, aluminum is obliquely deposited on the three-layer resist pattern (2),
By performing (3), a drain 121, a source 125, and a gate 126 are formed. Thereafter, the aluminum-based single electron transistor 1 is lifted off.
20 are formed. In FIG. 3B, the stippling region is a portion formed by vertical vapor deposition (1), and the hatched region is a portion formed by oblique vapor deposition (2) and (3).

The operation principle of the semiconductor memory device 110 formed as described above will be described. (Programming Operation) A programming operation of the semiconductor memory device 110 will be described. Here, it is assumed that carriers used for storage are electrons, and electrons are exchanged between the high-conductivity layer 113 and the carrier accumulation layer 114.
When programming the storage device 110, a negative voltage of −Vg is applied to the high conductivity layer 113. Since all the electrodes connected to the single-electron transistor 120, that is, the drain 121, the source 125, and the island 123 have almost a ground potential, the electric field generated between them and the high-conductivity layer 113 causes The electrons present therein are injected into the carrier storage layer 114 by a tunnel process. Thus, the carrier accumulation layer 114 is negatively charged, and the programming operation is performed.

(Erase Operation) The erase operation of the semiconductor memory device 110 will be described. Here, it is assumed that carriers used for storage are electrons. When erasing the storage content of the storage device 110, a positive voltage of Vg is applied to the high conductivity layer 113. Since all of the electrodes connected to the single-electron transistor 120, that is, the drain 121, the source 125, and the island 123 have a substantially ground potential, the electric field generated between the single-electron transistor 120 and the high-conductivity layer 113 causes the carrier storage layer 114 Are injected into the high conductivity layer 113 by a tunnel process. As a result, there is no electron in the carrier accumulation layer 114.

(Read Operation) In the read operation for detecting the programming operation and the erase operation, the single electron transistor 120 is used. The operating principle of the single-electron transistor 120 is a known fact as described in the prior art. When the voltage VW is applied to the gate 126 of the single-electron transistor 120, the source 125 is grounded, and the drain 1 is applied when VD is applied to the drain 121.
The current I flowing through 21 is as shown in FIG. This current oscillation is known as Coulomb oscillation, which is due to the Coulomb blockade effect, which reflects a change in the amount of charge Q induced in the island 123 by the voltage VW applied to the gate 126. In the present semiconductor memory device, the charge amount QT stored at the capture center
Is changed by writing and erasing operations in the semiconductor memory device. With this charge amount QT, the island 123
A charge is induced in a capacitor between the capacitor and the carrier storage layer 114. FIG. 8 (b)
As shown in (1), the value of the gate voltage VW at which the current I flowing through the drain 121 of the single-electron transistor 120 becomes maximum changes as compared with the case where there is no charge. The reading operation is performed by utilizing the phenomenon that the value of VW at which the current I becomes maximum changes due to the above-described accumulated charge QT.

Here, in the present memory device, writing / erasing is controlled by a potential change of the high conductivity layer 113. On the other hand, at the time of writing / erasing, as described in the second conventional example of the prior art, the potential of the high-conductivity layer 113 causes the island 123
The amount of charge induced by the change. Since the capacitance between the high-conductivity layer 113 and the island 123 of the single-electron transistor 120 does not change due to the electric field inside the device and the device temperature, the change in the amount of charge can be easily determined. By simultaneously applying an appropriate potential of the opposite sign to the gate 126 of the gate 120, this change in the charge amount can be canceled. For how to counter this,
For example, Applied Physics Letters, Vol. 71, 2038 (19
97) (by CD Chen et al.). Thus, only the transfer of electrons into and out of the carrier storage layer 114 can be caused to appear as a change in the current I. The read operation is performed by observing the change of the current I by an external amplifier circuit or the like.

The semiconductor memory device 11 thus formed
0 means that the element area is 10 by using a high conductivity layer.
It was possible to reduce the size to about 0 nm × 100 nm. In addition, the manufactured single electron transistor 120 has a temperature of 7
Show clear Coulomb blockade oscillation at 7K,
It was confirmed that high-temperature operation was possible. Further, the capacitance between the high-conductivity layer 113 and the single-electron transistor 120 becomes constant with respect to an electric field and a temperature change due to the use of the high-conductivity layer 113, and is easily caused by a change in the thickness of the carrier accumulation layer 114. It became controllable. Further, a desired history phenomenon was confirmed, and it was confirmed that the present storage device was usable as a semiconductor storage device.

[Second Embodiment] FIGS. 3A and 3B are a plan view and a sectional view taken along the line aa 'of FIG. 3 showing a second embodiment of the present invention. 1 is an example of an electrically variable semiconductor memory device having a configuration in which a high-conductivity layer is electrically separated from a semiconductor substrate by a first insulating layer. This semiconductor storage device 110A differs from the structure of the first embodiment in the following points. The high conductivity layer 113 described in the first embodiment is different from the first insulating layer 1 in the first embodiment.
12 electrically separate from the semiconductor substrate 111. That is, the first insulating layer 112 is coated on the semiconductor substrate 111. The first insulating layer 112 is, for example, a silicon oxide film formed by thermal oxidation or a buried oxide film of a silicon-on-insulator substrate, and has a thickness of about 30 nm to 500 nm.
A high conductivity layer 113 is coated on the first insulating layer 112. The high conductivity layer 113 has a phosphorus concentration of 1
A polysilicon film or a silicon-on-insulator layer or a metal aluminum layer, which has been ion-implanted or phosphorus-diffused so as to have a density of about × 10 ¹⁹ / cm ³ to about 1 × 10 ²¹ / cm ³ , and a thickness of about 30 to 500 nm; Is desirable. A carrier accumulation layer 114 is formed on the high conductivity layer 113. The carrier animal stack 11
Reference numeral 4 denotes particles made of silicon such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and polysilicon particles, and a multilayer film made of these, and
A thickness of about 50 nm is desirable. A single electron transistor 120 is formed on the carrier storage layer 114. Since the single-electron transistor 120 is the same as that of the first embodiment, the description is omitted here.

The semiconductor memory device 11 formed as described above
In the case of 0A, by using the high conductivity layer 113, the element area could be reduced to about 100 nm × 100 nm. In addition, the fabricated single electron transistor 120
Showed clear Coulomb blockade vibration at a temperature of 77 K, and it was confirmed that the device could be operated at a high temperature. In addition, the capacitance between the high conductivity layer 113 and the single electron transistor 120 becomes constant with respect to electric field and temperature change due to the use of the high conductivity layer 113, and can be easily controlled by changing the thickness of the carrier layer. It has become possible. Further, a desired hysteresis phenomenon was confirmed, and it was confirmed that the present device was usable as a semiconductor memory device. Further, in this example, the first insulating layer 112 made of a silicon oxide film is
3 is effective for electrically separating the semiconductor substrate 111 from the semiconductor substrate 111. The semiconductor substrate 111 and the storage element such as the single electron transistor 120 formed on the semiconductor substrate 111 can be separated from each other. It has become possible to form a semiconductor memory device at high density within a substrate.

[Third Embodiment] FIGS. 4A and 4B are a plan view and a sectional view taken along line aa 'of FIG. 4 showing a third embodiment of the present invention. This is an example of an electrically tunable semiconductor memory device having a miniaturized configuration in which a high conductivity layer formed with an insulating layer interposed therebetween is present only below a memory cell. This semiconductor storage device 110B
Is different from that described in the second embodiment in the following point. That is, the high-conductivity layer 113 described in the second embodiment is provided only in the lower part of the memory cell, specifically, only in the region of the main part such as the source 125, the drain 121, the island 123, and the gate 126 of the single-electron transistor 120. It is formed to exist. In this example, the plane of the high conductivity layer 113 has a width of about 50 nm.

That is, on the semiconductor substrate 111, the first
Of the insulating layer 112 is covered. First insulating layer 112
Is, for example, a silicon oxide film formed by thermal oxidation or a buried oxide film of a silicon on insulator substrate,
Its thickness is about 30 to 500 nm. A high conductivity layer 113 is coated on the first insulating layer 112. The high conductivity layer 113 has a phosphorus concentration of 1 × 10
A polysilicon film, a silicon-on-insulator layer, or a metal aluminum layer, which is ion-implanted or phosphorus-diffused so as to have a density of about ¹⁹ / cm ³ to about 1 × 10 ²¹ / cm ³ , and has a thickness of about 30 to 500 nm. Something is desirable. The high-conductivity layer is miniaturized to a width of about 50 nm. For the formation, a resist pattern having a width of 50 nm is formed on the resist by using electron beam irradiation, and is used as a mask for dry etching. After fine processing by dry etching, the resist is peeled off to form a fine high conductivity layer. Above the high conductivity layer 113,
A carrier accumulation layer 114 is formed. The carrier storage layer 114 may be, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a particle made of silicon such as polysilicon particles and a multilayer film made of these,
A thickness of about 5 nm to 50 nm is desirable. On the carrier accumulation layer 114, a single-electron transistor 120 is manufactured as in the above embodiments.

It has been confirmed that the semiconductor memory element 110B can be miniaturized to an element area of about 50 nm × 50 nm. In addition, the manufactured single-electron transistor exhibited clear Coulomb blockade oscillation at a temperature of 77 K, and it was confirmed that the single-electron transistor was operable at a high temperature. In addition, the capacitance between the high conductivity layer 113 and the single electron transistor 120 becomes constant with respect to an electric field and a temperature change due to the use of the high conductivity layer 113, and the carrier accumulation layer 114
Can be easily controlled by changing the film thickness. Further, a desired hysteresis phenomenon was confirmed, and it was confirmed that the present device was usable as a semiconductor memory device. Further, in this example, at the same time as the high conductivity layer 113 is electrically separated from the semiconductor substrate 111, each element in the same semiconductor substrate is independently controlled with miniaturization due to being formed only in the lower part of the memory cell. What you can do is now possible. In addition, the high conductivity layer 113
, The coupling capacitance between the island 123 of the single-electron transistor 120 and the high-conductivity layer 113 is increased.
26, the voltage applied to the gate 126 during the memory operation described in the first embodiment could be reduced.

[Fourth Embodiment] FIGS. 5A and 5B are a plan view and a sectional view taken along line aa 'of FIG. 5 showing a fourth embodiment of the present invention. The high-conductivity layer formed with the layers interposed therebetween is miniaturized so as to exist only below the memory cell, a second insulating layer is disposed thereon, and a carrier accumulation layer is disposed thereon, This is an example of an electrically variable semiconductor memory device having a structure in which a third insulating layer is further provided. This semiconductor memory device 110C is different from that described in the third embodiment in the following point. Third
Carrier storage layer 114 described in the embodiment.
Is sandwiched between the second insulating layer 115 and the third insulating layer 116. These second insulating layers 11
The fifth and third insulating layers have a larger band gap than the carrier storage layer 114 and serve as a barrier. However,
Either the second insulating layer 115 or the third insulating layer 116 functions as a tunnel barrier as thin as 1 to 15 nm,
The other is as thick as 20 to 200 nm and has the effect of preventing carrier from coming off.

That is, on the semiconductor substrate 111, the first
Of the insulating layer 112 is covered. First insulating layer 112
Is, for example, a silicon oxide film formed by thermal oxidation or a buried oxide film of a silicon on insulator substrate,
Its thickness is about 30 to 500 nm. A high conductivity layer 113 is coated on the first insulating layer 112. The high conductivity layer 113 has a phosphorus concentration of 1 × 10
A polysilicon film or a silicon-on-insulator layer or a metal aluminum layer, which is ion-implanted or phosphorus-diffused so as to have a thickness of about ¹⁹ / cm ³ to about 1 × 10 ²¹ / cm ³ , and has a thickness of about 30 to 500 nm. Things are desirable. The high-conductivity layer is miniaturized to a width of about 50 nm. For the formation, a resist pattern having a width of 50 nm is formed on the resist by using electron beam irradiation, and is used as a mask for dry etching. After fine processing by dry etching, the resist is peeled off, and a fine high conductivity layer 113 is formed. On the high conductivity layer 113, a second insulating layer 115 is formed. The second insulating layer 115 may be, for example, a silicon oxide film formed by thermal oxidation. A carrier accumulation layer 114 is formed thereon. The carrier layer 114 may be, for example, a particle made of silicon such as a silicon nitride film, a silicon oxynitride film, or a polysilicon particle, and preferably has a thickness of about 5 to 50 nm. A third insulating layer 116 is formed on the carrier accumulation layer 114. Third insulating layer 1
Reference numeral 16 may be, for example, a silicon oxide film formed by thermal oxidation. The second insulating layer 115 and the third insulating layer 1
The thickness of 16 is as thin as 1 to 15 nm on one side and 20 on one side.
It is desirable that the thickness be 200 nm. The third insulating layer 1
The single-electron transistor 120 is fabricated on the same as in the above embodiments.

It has been confirmed that the semiconductor memory device 110C can be miniaturized to an element area of about 50 nm × 50 nm. In addition, it was confirmed that the manufactured single-electron transistor 120 exhibited clear Coulomb blockade oscillation at a temperature of 77 K, and was capable of operating at a high temperature. The high conductivity layer 113 and the single electron transistor 1
20 is constant with respect to electric field and temperature change because the high conductivity layer 113 is used, and the carrier accumulation layer 114, the second insulating layer 115, and the third insulating layer 1
It became possible to control easily by the film thickness change of 16. Further, a desired hysteresis phenomenon was confirmed, and it was confirmed that the present device was usable as a semiconductor memory device. Further, in this example, the high conductivity layer 113 was electrically separated from the semiconductor substrate 111, and each element in the same semiconductor substrate could be controlled independently, and the voltage applied to the gate 126 during the memory operation could be reduced. In addition, the carrier accumulation layer 114 is
By interposing the insulating layer 115 and the third insulating layer 116, the carrier holding characteristics can be improved. Further, of the second insulating layer 115 and the third insulating layer 116, the thinner insulating layer acts as a tunnel barrier having high film thickness controllability, and the carrier writing / erasing mode can be easily controlled by the film thickness control. You can now choose.

[0032]

According to the present invention described above, by using a single electron transistor as a sensing element, a high conductivity layer can be arranged with low power consumption and under a carrier storage layer. It is possible to configure a semiconductor memory device that has high density, high integration, and high reliability by using it for controlling the operation of the storage device, and that can easily design elements by controlling the film thickness by using a layered structure. Become.

[Brief description of the drawings]

FIGS. 1A and 1B show a semiconductor memory device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line aa ′.

FIG. 2 is a diagram illustrating a manufacturing process step in the first embodiment.

FIGS. 3A and 3B show a semiconductor memory device according to a second embodiment of the present invention, wherein FIG. 3A is a plan view and FIG. 3B is a cross-sectional view taken along line aa ′.

FIGS. 4A and 4B show a semiconductor memory device according to a third embodiment of the present invention, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along line aa ′.

FIGS. 5A and 5B show a semiconductor memory device according to a fourth embodiment of the present invention, wherein FIG. 5A is a plan view and FIG. 5B is a sectional view taken along line aa ′.

FIG. 6 is a conceptual diagram for explaining a method for manufacturing a single-electron transistor.

7A and 7B show a semiconductor nonvolatile memory device described in a second conventional example of the related art, FIG. 7A is a plan view, and FIG. 7B is aa ′.
The line is a cross-sectional view.

FIG. 8 is a diagram showing Coulomb oscillation and fluctuation of a gate voltage VW in a single-electron transistor.

[Explanation of symbols]

 Reference Signs List 110 semiconductor storage device 111 semiconductor substrate 112 first insulating layer 113 high conductivity layer 114 carrier accumulation layer 115 second insulating layer 116 third insulating layer 120 single electron transistor 121 drain 122,124 tunnel barrier 123 island 125 source 126 Gate 210 Semiconductor storage device 212 Semiconductor substrate 213 Drain of field effect transistor 214 Source of field effect transistor 215 Element isolation film 216 First insulating layer 217 Second insulating layer 218 Third insulating layer 219 Single electron transistor 220 Active Region 221 Single-electron transistor drain 222,224 Tunnel barrier 223 Island 225 Single-electron transistor source 226 Gate 227 Field-effect transistor drain electrode 228 Field effect The source electrode of the transistor

Claims (9)

[Claims] 1. A semiconductor substrate, a high conductivity layer formed on the semiconductor substrate, a carrier storage layer formed on the high conductivity layer, and a single storage layer formed on the carrier storage layer. A semiconductor memory device comprising a one-electron transistor. 2. The semiconductor memory device according to claim 1, wherein a first insulating layer exists between said semiconductor substrate and said high conductivity layer. 3. The semiconductor memory device according to claim 2, wherein said first insulating film layer is a silicon oxide film. 4. The semiconductor device according to claim 1, wherein the high-conductivity layer exists only below a memory cell region defined by the single-electron transistor and a peripheral region thereof.
The semiconductor memory device according to any one of the above. 5. The semiconductor device according to claim 1, wherein the high-conductivity layer is formed just below the region of the micro-junction including the island of the single-electron transistor and has a size similar to that of the region of the micro-junction. The semiconductor memory device according to claim 4. 6. The semiconductor memory device according to claim 4, wherein a second insulating layer exists between said high conductivity layer and said carrier storage layer. 7. The semiconductor memory device according to claim 6, wherein a third insulating layer exists between said carrier accumulation layer and said single electron transistor. 8. The semiconductor device according to claim 1, wherein the high-conductivity layer comprises one of a heavily doped silicon-on-insulator layer, a heavily doped polysilicon layer, and a metal layer. 8. The semiconductor memory device according to any one of items 1 to 7. 9. The semiconductor substrate is made of silicon, and the carrier storage layer is made of a multilayer structure of silicon nitride and a silicon oxide film. Alternatively, the carrier storage layer is made of silicon-based particles and a multilayer of silicon oxide film. 9. The semiconductor memory device according to claim 1, wherein said semiconductor memory device has a structure.