JPH06151878A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To provide a nonvolatile semiconductor memory which enables high integration. CONSTITUTION:The device is provided with a second conductivity type diffusion layer 4 which constitutes a drain region which becomes a bit line formed in one direction successively in a first conductivity type semiconductor substrate 1, and a gate electrode 6 which intersects with the bit line and becomes a word line formed in a part of the drain region through an insulation film 5. Information is read based on a gate induction drain leak current value in the drain region 4. The gate insulation film 5 has a trap level of charge and is made to correspond to '1', '0' of information depending on whether or not charge is trapped to the level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor suitable for high integration.

[0002]

2. Description of the Related Art Conventionally, a flash type EEPROM is known as a highly integrated nonvolatile semiconductor memory device capable of electrically writing and erasing information.

FIG. 4 shows the conventional flash type EE described above.
1 shows an example of a PROM. In FIG. 4, 1 is a p-type silicon substrate, 4 is an n ⁺ diffusion layer, 5 is a gate insulating film, 6 is a floating gate, 7 is a dielectric film, 8 is a gate electrode to be a word line, 9 is an insulating film, 10 Is a bit line.

Flash type EE configured as described above
In the PROM, writing is performed by injecting hot electrons into the floating gate 6. Erasing is performed by applying a high voltage to the source so that electrons are emitted from the floating gate 6. Reading of information is performed by the difference in the current flowing between the source and the drain due to the change in the threshold voltage of the transistor of the memory cell.

On the other hand, as disclosed in Japanese Patent Laid-Open No. 3-112167, a semiconductor substrate has a diffusion region (drain) of the opposite conductivity type to this substrate, and a part of this diffusion region overlaps with an insulating film. As described above, in a semiconductor device having a gate electrode, it is shown that a non-volatile semiconductor memory device is constructed by using a gate-induced drain leak current in the diffusion region.

FIG. 5 illustrates an example of a non-volatile semiconductor memory device using the above gate-induced drain leak current. In FIG. 5, 1 is a silicon substrate, 3 is an isolation region, 4 is an n ⁺ diffusion layer, 5 is a gate insulating film, 6 is a gate electrode, 7 is an insulating film, 8 is a bit line contact, and 9 is a word line contact. .

In the non-volatile semiconductor memory device configured as described above, when a voltage higher than a specific voltage difference is applied between the drain region 4 and the gate electrode 6, a gate-induced drain leak current due to band-to-band tunneling occurs. , The current flowing through the drain and the substrate. By trapping some of the holes of this current in the trap level of the gate insulating film, the value of the gate-induced drain leakage current changes. This change is used to read information from the memory cell.

[0008]

However, in the structure such as the conventional flash type EEPROM described above, since the information is read out by the change of the threshold voltage of the transistor, the miniaturization effect of the transistor is reduced as the miniaturization is advanced. Becomes a problem, and high integration is difficult.

Further, in the semiconductor device using the above gate-induced drain leakage current, there is no influence of the short channel effect of the transistor, and since the source region is unnecessary, miniaturization is easy. However, since it is necessary to make contact with the drain and gate electrodes of each memory cell and to provide an isolation region for each memory cell, it is difficult to promote high integration. Was.

In view of the above problems, the present invention provides a highly integrated nonvolatile semiconductor memory device.

[0011]

In order to solve the above problems, a nonvolatile semiconductor memory device according to the present invention has a drain, which is a bit line continuously formed in one direction on a semiconductor substrate of a first conductivity type. A second conductive type diffusion layer forming a region; and a gate electrode which intersects the bit line and serves as a word line formed through a part of the drain region and a gate insulating film. Information is read based on the gate-induced drain leakage current value.

Further, in the above-mentioned nonvolatile semiconductor memory device, a first word line made of the first-layer conductor film and a second-layer conductor film formed between the first word lines are formed. And a second word line.

The gate insulating film has a charge trapping level, and corresponds to information "1" or "0" depending on whether or not the level traps the charge.

A floating gate electrode is provided in the gate insulating film, and information "1" or "0" is determined depending on whether or not the floating gate electrode traps charges.
May correspond to.

[0015]

With the above structure, the memory cell is composed of the semiconductor substrate, the drain region, and the three terminals of the gate electrode. Further, the bit line is composed of a diffusion layer serving as a drain region, and it is not necessary to make contact with the bit line for each memory cell. When a voltage equal to or higher than a specific voltage difference is applied between the drain region and the gate electrode, a gate-induced drain leak current due to band-to-band tunneling occurs. Information is read from the change in the gate-induced drain leakage current value depending on the presence or absence of charge of the trap level in the gate insulating film.

Further, since the second word line made of the conductor film of the second layer is formed between the first word lines made of the conductor film of the first layer, the first word line is formed. Not only the memory cell is formed by the diffusion layer serving as the bit line below and the memory cell is also formed by the second word line and the diffusion layer below the second word line. Therefore, higher integration can be achieved.

The gate insulating film has a charge trapping level, and the trapped charge is not released even when the power is turned off, and thus information can be stored in a non-volatile state. Depending on whether or not charges are trapped in the trap level, a difference occurs in the gate-induced drain leakage current value due to band-to-band tunneling in the drain region, and the stored information can be read.

Similarly, when the floating gate electrode is provided in the insulating film, the electric charge trapped in the floating gate electrode is not released even when the power is turned off, and information can be stored in a non-volatile state. Depending on whether or not the floating gate electrode captures charges, the gate-induced drain leakage current value due to band-to-band tunneling in the drain region varies, and the stored information can be read.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A non-volatile semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a structure of a nonvolatile semiconductor memory device as a first embodiment of the present invention. 1 (a) is a plan view, and FIG. 1 (b) is A- in FIG. 1 (a).
A cross-sectional view taken along the line A ′, and FIG.
It is sectional drawing which followed the B'line.

First, an isolation insulating film 3 having a P-type channel stopper 2 underneath is formed in a portion of the P-type silicon substrate 1 which will be an element isolation region. Next, the n ⁺ diffusion layer 4 in the drain region, which will be the bit line, is formed with an acceleration energy of
It is formed by As ion implantation with V and a dose amount of 6.0 × 10 ¹⁵ cm ⁻² . And the gate insulating film 5 made of SiO2
To form. Here, the thickness of the gate insulating film 5 is 5 to 12
It may be about nm. Here, it is set to 7 nm. Then, n ⁺ polysilicon 6 of the gate electrode to be the word line is formed. Here, the gate insulating film 5 and the gate electrode 6 are provided in contact with the PN junction between the drain region 4 and the channel stopper 2.

Since the memory cell has no source electrode, it is composed of three terminals, that is, the semiconductor substrate 1, the drain electrode 4 and the gate electrode 6. The gate insulating film 5 captures charges and stores information in a nonvolatile state. Further, since the bit line is composed of the diffusion layer 4 and it is not necessary to make contact with the bit line for each memory cell, every few bits (for example, every 32 bits).
Just contact us.

Next, the operation as a memory cell in the above structure will be described. In this structure, when a voltage higher than a specific voltage difference is applied between the drain region 4 and the gate electrode 6, a gate-induced drain leak current due to band-to-band tunneling occurs near the interface of the gate insulating film 5 in the drain region 4. . The electric field in the drain region changes due to the charges trapped in the gate insulating film 5, and the information can be read from the difference in the current value.

In the structure shown in this embodiment, for example, if the gate voltage Vg is −3V, the substrate voltage Vsub is 0V, and the drain voltage Vd is 5V, a band is formed near the interface of the gate insulating film 5 in the drain region 4. Bending over the band gap and tunneling between the bands generate electrons and holes. Information is written by capturing the holes in the gate insulating film 5.

FIG. 2 shows the drain voltage dependence of the gate-induced drain leakage current Id due to the band-to-band tunneling before and after trapping holes (Vg = -3V, Vsub).
= 0V, but the gate width is 20um). The trapped holes reduce the gate-induced drain leakage current. Here, when the gate voltage Vg is 0V or the drain voltage is 0V among the above voltage conditions, trapping of holes is not observed. Therefore, writing can be performed in a specific memory cell by selecting the word line and the bit line and applying a potential.

The holes captured by writing to the memory cell can be easily released. For example, when the gate voltage Vg is 8 V, the substrate voltage Vsub is 0 V, and the drain voltage Vd is 0 V, a high electric field is applied to the gate insulating film from the gate electrode in the semiconductor substrate direction, and trapped holes are emitted, and before capture. Return to the state of. That is, it can be erased.

In FIG. 2, Vd is 2 before and after the hole is captured.
At V, there is a current difference of about 10 ² . Information can be read out from this current difference. For example, the gate voltage Vg is −3 V and the substrate voltage Vsub is 0.
If V and the drain voltage Vd are 2 V, the current value is about 2 × 10 ⁻⁸ A before trapping the holes and about 2 × 10 ⁻¹⁰ A after trapping. Under this bias condition, there is no writing or erasing of information in the memory cell (hole capture or emission),
You can read the stored information.

As described above, according to the above-described embodiment, the semiconductor substrate, the diffusion layer serving as the drain region formed on the substrate, and the three terminals of the gate electrode are the only terminals and function as a memory cell. Therefore, as compared with a memory cell using a MOS transistor, there is no influence of the short channel effect and there is no source region, so that it is possible to achieve a large miniaturization. With the same design rule, it can occupy less than half the area of conventional flash EEPROM memory cells, and if bit lines and word lines can be formed even with further miniaturization, it will function as a memory cell. To do.

Further, since the diffusion layer to be the drain region is continuously formed in one direction, it is not necessary to make a bit line contact for each memory cell and it is not necessary to provide an isolation region in the word line direction. High integration is possible. For example, if the word line pitch is 1.0 μm and the bit line pitch is 1.0 μm, the occupied area of one memory cell is 1.0 μm ² . Further, in order to reduce the resistance of the bit line, it is possible to easily form a wiring lined with the diffusion layer of the bit line.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows the structure of a nonvolatile semiconductor memory device according to the second embodiment of the present invention. 3A is a plan view, FIG. 3B is a sectional view taken along the line AA ′ in FIG. 3A, and FIG. 3C is a sectional view taken along the line BB ′ in FIG. Is.

In the figure, 1 is a P-type silicon substrate, 2 is
Is a P-type channel stopper, 3 is an isolation insulating film 3, 4 is an n ⁺ diffusion layer of a drain region which becomes a bit line, 5 is a gate insulating film, and 6 is n ⁺ polysilicon of a gate electrode which becomes a first word line. is there. The above is the same as the configuration of FIG. The difference from FIG. 1 is that the second word line 10 is provided between the first word lines 6.

As a method of forming this device, as in the first embodiment, n ^{+ of the} gate electrode to be the first word line is formed.
Up to the polysilicon 6 is formed. Here, the first word line is patterned after the insulating film 7 is deposited on the polysilicon 6. Then, the entire surface is formed by the CVD method with SiO 2.
Two films are deposited and anisotropically etched by RIE (reactive ion etching) to form an insulating film 8 on the side wall of the first word line 6. Gate insulating film 9 made of SiO2
And then n of the gate electrode to become the second word line.
⁺ Polysilicon 10 is formed.

As described above, by providing the second word line between the first word lines, the word line pitch can be reduced to about half with the same design rule as in the first embodiment. It is possible to double the integration density.
For example, both the first word line and the second word line are 1.
If they are formed with a pitch of 0 μm, the occupied area of one memory cell is 0.5 μm ² .

In the first and second embodiments, information is stored by trapping holes in the gate insulating film made of a SiO2 film. However, a floating gate electrode is provided in the gate insulating film and the floating gate electrode is charged. The function of the memory cell can be similarly realized by capturing the. As a result, the durability of the insulating film can be improved.

[0036]

As described above, the nonvolatile semiconductor memory device of the present invention is composed of only the semiconductor substrate, the diffusion layer serving as the drain region formed on the substrate, and the three terminals of the gate electrode, and can be manufactured by an easy process. You can Further, since there is no influence of the short channel effect and there is no source region, it is possible to greatly miniaturize. Further, since the diffusion layer to be the drain region is continuously formed in one direction, it is not necessary to make a bit line contact for each memory cell and it is not necessary to provide an isolation region in the word line direction, so that high integration is achieved. Can be converted.

[Brief description of drawings]

1A is a plan view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, FIG. 1B is a sectional view of the same, and FIG. 1C is a sectional view of the same.

FIG. 2 is a characteristic diagram showing the voltage dependence of a gate-induced drain leakage current for explaining the operation in the embodiment.

3A is a plan view of a nonvolatile semiconductor memory device according to a second embodiment of the present invention, FIG. 3B is the same sectional structure view, and FIG.

FIG. 4 is a schematic diagram of a flash type EEPROM of a conventional nonvolatile semiconductor memory device.

FIG. 5 is a schematic diagram of a conventional nonvolatile semiconductor memory device using a gate-induced drain leakage current.

[Explanation of symbols]

1 P-type semiconductor substrate 2 P-type channel stopper 3 Isolation insulating film 4 n ⁺ diffusion layer (bit line) 5 Gate insulating film 6 n ⁺ polysilicon (word line)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naru Okuda 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A second-conductivity-type diffusion layer forming a drain region, which is a bit line continuously formed in one direction on a first-conductivity-type semiconductor substrate, and the drain region intersecting the bit line. And a gate electrode serving as a word line formed through an insulating film, and reading information based on a gate-induced drain leakage current value in the drain region. Storage device. 2. The word line according to claim 1, comprising a first word line made of a conductor film of a first layer and a conductor film of a second layer formed between the first word lines. A non-volatile semiconductor memory device comprising a second word line. 3. The insulating film according to claim 1 or 2 has a charge trapping level, and is made to correspond to "1" or "0" of information depending on whether or not the level traps the charge. A non-volatile semiconductor memory device characterized by the above. 4. A floating gate electrode is provided in the insulating film according to claim 1 or 2, and information is stored according to whether or not the floating gate electrode traps charges.
A nonvolatile semiconductor memory device characterized in that it corresponds to 1 "and" 0 ".