JPS6393160A - Ultra-high speed semiconductor device - Google Patents
Ultra-high speed semiconductor deviceInfo
- Publication number
- JPS6393160A JPS6393160A JP23849386A JP23849386A JPS6393160A JP S6393160 A JPS6393160 A JP S6393160A JP 23849386 A JP23849386 A JP 23849386A JP 23849386 A JP23849386 A JP 23849386A JP S6393160 A JPS6393160 A JP S6393160A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- charge storage
- quantum well
- ultra
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000003860 storage Methods 0.000 claims abstract description 23
- 238000005036 potential barrier Methods 0.000 claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 5
- 230000005428 wave function Effects 0.000 claims abstract description 3
- 230000005641 tunneling Effects 0.000 claims description 9
- 239000000969 carrier Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- LZZYPRNAOMGNLH-UHFFFAOYSA-M Cetrimonium bromide Chemical compound [Br-].CCCCCCCCCCCCCCCC[N+](C)(C)C LZZYPRNAOMGNLH-UHFFFAOYSA-M 0.000 description 1
- 101100130497 Drosophila melanogaster Mical gene Proteins 0.000 description 1
- 101100345589 Mus musculus Mical1 gene Proteins 0.000 description 1
- 101150101918 TSC22D3 gene Proteins 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は超高速半導体装置、特に半導体超薄膜構造によ
る共鳴トンネル効果を利用した電界効果トランジスタ（
ＦＥＴ）を基本構成とする超高速半導体装置に関わる。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an ultra-high-speed semiconductor device, particularly a field effect transistor (
It is concerned with ultra-high-speed semiconductor devices whose basic structure is FET).
本発明は、電荷Ｍ積層と量子井戸チャンネル層と、これ
ら間に配され、これら間に共鳴トンネル効果を生ぜしめ
得る厚さの中間電位障壁層とが配された半導体超薄膜構
造を有して成り、電荷蓄積層と量子井戸チャンネルとに
第１及び第２の電極を設け、電荷蓄積層にゲート部を設
けて成るものであり、共鳴トンネル効果の利用によって
高速ＦＥＴ動作をなさしめるものである。The present invention has a semiconductor ultra-thin film structure including a charge M stack, a quantum well channel layer, and an intermediate potential barrier layer disposed between them and having a thickness capable of producing a resonant tunneling effect between them. The first and second electrodes are provided in the charge storage layer and the quantum well channel, and the gate portion is provided in the charge storage layer, and high-speed FET operation is achieved by utilizing the resonant tunneling effect. .
近時益々高速動作によるＦＥＴの実用化の要求が高まっ
ている。Recently, there has been an increasing demand for practical use of FETs that operate at higher speeds.
通常一般のＦＥＴ、例えばショットキーゲート型のＦＥ
Ｔ、接合ゲート型ＦＥＴ等における動作速度は、そのゲ
ート容量、ソース抵抗、ないしはチャンネル抵抗の積で
決まってしまうものである。Usually a general FET, such as a Schottky gate type FE
The operating speed of a junction gate type FET or the like is determined by the product of its gate capacitance, source resistance, or channel resistance.
つまり、この種のＦＥＴでは、ゲート電位の変化によっ
てゲート容量を変化させ、これに応じたキャリア例えば
電子の、ソース抵抗ないしはチャンネル抵抗を通じての
充放電動作であることから、その動作速度は、ゲート容
量とチャンネル抵抗とによって決まる。したがってその
動作速度はチャンネル長に依存する。このチャンネル長
は、通常その製造技術、すなわちゲート加工精度上の制
約から０．５μｍ前後となることから、キャリアの走行
時間の短縮化、すなわち高速動作には実際上、制約があ
り、充分な高速性が得られない。In other words, in this type of FET, the gate capacitance changes depending on the change in gate potential, and carriers, such as electrons, are charged and discharged through the source resistance or channel resistance accordingly, so the operating speed depends on the gate capacitance. and channel resistance. Its operating speed therefore depends on the channel length. This channel length is usually around 0.5 μm due to constraints on manufacturing technology, that is, gate processing accuracy. Therefore, there are practical restrictions on shortening carrier travel time, that is, high-speed operation, and sufficient high-speed operation is required. I can't get sex.
本発明は、上述したゲート加工精度によるキャリア走行
距離の制約の問題の解決をはかる。The present invention aims to solve the above-mentioned problem of restrictions on carrier travel distance due to gate processing accuracy.
〔問題点を解決するための手段〕
本発明においては、半導体超薄膜構造を採り、キャリア
の走行時間を、キャリアが電位１１６２層を共鳴トンネ
ルするに要する時間のみで設定する構造を採る。[Means for Solving the Problems] In the present invention, a semiconductor ultra-thin film structure is adopted, and a structure is adopted in which the traveling time of carriers is set only by the time required for carriers to resonantly tunnel through the potential 1162 layer.
すなわち、本発明においては、第１図に示すように、電
荷蓄積層（１）と、量子井戸チャンネル層（２）と、こ
れら電荷蓄積Ｆｊ （１）及び量子井戸チャンネル層（
２）間に介在される中間電位障壁層（３）とを有する半
導体超薄膜構造を有して成る。That is, in the present invention, as shown in FIG.
2) It has an ultra-thin semiconductor film structure having an intermediate potential barrier layer (3) interposed therebetween.
電荷Ｍ８１層（１）には第１の電極（４）すなわちソー
ス電極がオーミックに被着され、量子井戸チャンネルＮ
（２）には第２の電極（５）すなわちドレイン電極がオ
ーミックに被着される。A first electrode (4), ie, a source electrode, is ohmically deposited on the charge M81 layer (1), and a quantum well channel N
A second electrode (5), ie, a drain electrode, is ohmically attached to (2).
また、電荷蓄積層＋１）にゲート部（６）例えばシコフ
トキーゲートを、第１及び第２の電極（４）及び（５）
間に相当する部分上に形成する。In addition, the charge storage layer +1) is provided with a gate portion (6), for example, a Schikoftsky gate, and the first and second electrodes (4) and (5) are connected to each other.
It is formed on the part corresponding to the area in between.
中間電位障壁ｆｆ１ （３１の厚さＬＢは、第１の電極
（４）、第２の電極（５）、及びゲート部（６）への印
加電圧の選定によって電荷蓄積層（１）と量子井戸チャ
ンネル層（２）との間に波動関数の重なりによって共鳴
トンネク電流を生ぜしめ得る厚さ具体的にはＬｌ≦３０
０人、例えば２５人〜５０人とする０図において、Ｓ、
Ｄ及びＧは、ソース、ドレイン及びゲートの各端子を示
す。The thickness LB of the intermediate potential barrier ff1 (31) is determined by selecting the voltages applied to the first electrode (4), the second electrode (5), and the gate part (6). The thickness that can generate a resonant tunnel current due to the overlap of wave functions between the channel layer (2), specifically, Ll≦30
In the 0 diagram with 0 people, for example 25 to 50 people, S,
D and G indicate source, drain, and gate terminals.
本発明構成では、ソース及びドレインＳ及び０間に所要
の電圧ＶＤＳを印加し、且つゲートＧに所要の電圧を印
加させることによって電荷蓄積層（１）からの電荷を電
子井戸チャンネルＮ （２）に、ゲート部（６）下にお
ける中間電位障壁層（３）の厚さＬＢを貫通する共鳴ト
ンネル作用によって移動させるものであり、このように
したことによって電荷の走行時間は、電荷が極薄の中間
電位障壁Ｎ（３）をトンネルするに要するだけの極めて
短い時間となる。In the configuration of the present invention, the charge from the charge storage layer (1) is transferred to the electron well channel N (2) by applying a required voltage VDS between the source and drain S and 0, and applying a required voltage to the gate G. In addition, the charge is moved by a resonant tunneling effect that penetrates the thickness LB of the intermediate potential barrier layer (3) under the gate part (6). The time required for tunneling through the intermediate potential barrier N(3) is extremely short.
更に第１図を参照して本発明の一実施例を説明する。こ
の例においては、信号キャリアが電子でり、第２図Ａ〜
Ｃにその伝導帯底部のバンドモデル図を示すように、２
つの量子井戸Ｗ１及びＷ２を有する構造とした場合であ
る。つまり一方の量子井戸Ｗ１は、量子井戸チャンネル
層（２）によるものであり、他方の量子井戸Ｗ２は電荷
Ｍ積層［１１によるものである。Further, an embodiment of the present invention will be described with reference to FIG. In this example, the signal carrier is an electron, and FIG.
As shown in the band model diagram of the bottom of the conduction band in C, 2
This is a case of a structure having two quantum wells W1 and W2. That is, one quantum well W1 is formed by the quantum well channel layer (2), and the other quantum well W2 is formed by the charge M stack [11].
この場合例えば半絶縁性のＧａＡｓ単結晶基板（１１）
を設け、これの−主面上に分子線エピタキシー法いわゆ
るＭ Ｂ Ｅ （Ｍｏ１ｅｃｕｌａｒ Ｂｅａｖａ
Ｅｐｉｔａｘｙ）法、或いは有機金属気相成長法いわ
ゆるＭＯＣＶＤ（Ｍｅｔａｌｏｒｇａｎｉｃ Ｃｈｅ
ｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ
）法によって順次連続的に下層電位障壁層（７）と、量
子井戸チャンネル層（２）と、共鳴トンネル作用の生じ
得る中間電位障壁Ｎ（３）と電荷蓄積層（ｌｌと、上層
電位障壁Ｎ（８）とをエピタキシャル成長させる。In this case, for example, a semi-insulating GaAs single crystal substrate (11)
A molecular beam epitaxy method, so-called MBE, is applied to the main surface of this.
Epitaxy method, or metal organic chemical vapor deposition method (MOCVD)
Mical Vapor Deposition
) method, the lower potential barrier layer (7), the quantum well channel layer (2), the intermediate potential barrier N (3) where resonant tunneling can occur, the charge storage layer (ll), and the upper potential barrier N (8) and are epitaxially grown.
量子井戸チャンネル層（２）と電荷蓄積層（１１は例え
ばｎ型ＧａＡｓより成り電位障壁層（７）、（３）及び
（８）はノンドープのＡｊｔＧａＡｓにより構成する。The quantum well channel layer (2) and the charge storage layer (11 are made of n-type GaAs, for example), and the potential barrier layers (7), (3) and (8) are made of non-doped AjtGaAs.
すなわち電位障壁層（７１、（３１及び（８）は電荷蓄
積層（１１及び量子井戸チャンネルｊｉｉ ｔ２）に比
べてそのバンドギャップが大で伝導帯の底のレベルが高
く、且つ価電子帯の頂が低い半導体層によって構成する
。That is, the potential barrier layer (71, (31 and (8)) has a larger band gap than the charge storage layer (11 and quantum well channel 2), has a higher conduction band bottom level, and has a higher valence band top level. It is made up of a semiconductor layer with a low resistance.
電荷蓄積Ｎ （１）及び量子井戸チャンネル層（２）と
これら間の中間電位障壁ｒｒＩ（３）の厚さは、各量子
井戸に電子の閉じ込めを行うことができ、しかも各部に
所要の電圧を外部から印加したときに共鳴トンネル作用
が生じ得る各厚さ、例えば中間電位障壁層（３）におい
ては３００Å以下とし、各層（１１〜（３）の厚さは２
５人〜５０人に選定し得る。The thickness of the charge storage N (1), the quantum well channel layer (2), and the intermediate potential barrier rrI (3) between them is such that electrons can be confined in each quantum well, and the required voltage can be applied to each part. The thickness of each layer where resonant tunneling can occur when applied externally, for example, the intermediate potential barrier layer (3), is 300 Å or less, and the thickness of each layer (11 to (3)) is 2
The number can be selected from 5 to 50 people.
また、電荷蓄積１ｉｉｉ（１１’の不純物濃度は１０１
１１ｃｔａ−３オーダーに選定すれば良い。In addition, the impurity concentration of charge accumulation 1iii (11' is 101
It is sufficient to select the order of 11cta-3.
上層の電位障壁層（８）上には、これに対してショット
キー接合を形成するショットキー金属の例えば＾ｌ又は
Ａｕより成るゲート電極（９）を被着してゲート部（６
）を構成する。そして、このゲート部を挾んでその一例
に、電荷蓄積層（１１に至る深さにアロイした第１の電
極、すなわちソース電極（４）を設け、他側に、電位障
壁層（８）と電荷蓄ｍｊｉｉ（１１の各一部をエツチン
グ除去して量子井戸チャンネル層（２）に到る深さにア
ロイした第２の電極、すなわちドレイン電極（５）を設
ける。On the upper potential barrier layer (8), a gate electrode (9) made of a Schottky metal such as Au or ^l or Au is deposited to form a Schottky junction to form a gate portion (6).
). Then, a first electrode, that is, a source electrode (4), which is alloyed to a depth reaching the charge storage layer (11), is provided on the other side, and a potential barrier layer (8) and a charge storage layer (11) are provided on the other side. A second electrode, ie, a drain electrode (5), is provided by etching away a portion of each of the deposits mjii (11) and depositing the layer to a depth that reaches the quantum well channel layer (2).
このような構成によれば、ソースＳ及び１１４７０間に
所要の電圧ｖｏｓを与えた状態で、ゲートＧに所要の負
の電圧を印加することによって電荷（２）へと向わせる
ことができ、ソースＳ及び１１４７０間のオン動作を行
うことができることになる。According to such a configuration, by applying a required negative voltage to the gate G while applying a required voltage vos between the source S and the 11470, it is possible to direct the charge to the charge (2), This means that an on operation between source S and 11470 can be performed.
これについて、第２図Ａ〜Ｃのバンドモデル図を荷蓄積
層（１１による各量子井戸Ｗ１及びＷ２における電子の
基底準位、及びｎ＝１．２・・・・の各エネルギー準位
を示す。第２図Ａは、各端子Ｓ、Ｄ及びＧに外部から電
位を印加しない状態を示し、この時雨量子井戸間、すな
わち中間電位障壁（３）には共鳴トンネルが生じないで
、各井戸に電子（キャリア）が局在するようになされて
いる。この構成においてドレインＤにソースＳに対し正
の電圧を印加すると、中間電位障壁層（３）にはポテン
シャルの傾きが生じるが、このソースＳ及び１１４７０
間の電圧ＶＤＳは、ゲートＧに例えば外部電圧を印加し
ないオフ電圧状態で、第２図Ｂにそのバンドモデル図を
示すように、依然として電位障壁（３）に共鳴トンネル
作用が生じない状態にあるように選定される。そして、
この電圧ＶＯＳに選定した状態で、ゲートＧに所要の負
のオン電圧を印加することによって、第２図Ｃにそのバ
ンドモデル図を示すように、電荷蓄積層（１〕の量子井
戸Ｗ２における基底レベルＥＣが量子井戸チャンネルＮ
（２）における量子井戸Ｗ１の量子準位の例えばＥ□と
重なり、同図Ｃに破線で示す結合及び反結合状態の共鳴
準位が生じ、両量子井戸Ｗ２及びＷ１間には矢印ａで示
すように電位障壁層（３）を突き貫ける電子の移動、す
なわち共鳴トンネル電流が発生し、ソースＳ及び１１４
７０間はオン状態となる。このトンネル電流の発生はス
パイク状に生じるので、そのオン・オフ動作は極めて早
く、ｒ Ｔ ＝ １０００ＧＩｌｚにも達し得る。Regarding this, the band model diagrams in FIGS. 2A to 2C show the ground level of electrons in each quantum well W1 and W2 by the charge storage layer (11) and each energy level of n=1.2... 2A shows a state in which no external potential is applied to each terminal S, D, and G, and no resonant tunnel is generated between the quantum wells, that is, the intermediate potential barrier (3), and each well is Electrons (carriers) are localized.In this configuration, when a positive voltage is applied to the drain D with respect to the source S, a potential gradient occurs in the intermediate potential barrier layer (3); and 11470
The voltage VDS between is in an off-voltage state where no external voltage is applied to the gate G, and as shown in the band model diagram in FIG. 2B, there is still no resonant tunneling effect in the potential barrier (3). are selected as follows. and,
By applying a required negative on-voltage to the gate G with this voltage VOS selected, the base in the quantum well W2 of the charge storage layer (1) is Level EC is quantum well channel N
For example, the quantum level of quantum well W1 in (2) overlaps with E As shown in FIG.
It remains on for 70 minutes. Since this tunnel current occurs in the form of a spike, its on/off operation is extremely fast and can reach r T = 1000 GIlz.
またこの時のトンネル電荷は、電荷蓄積ｊｉｉ （１１
の不純物濃度を１０” ｃ＋ｗ’オーダーとすれば、１
０１７ｃｔａ−’オーダーとなる。Moreover, the tunnel charge at this time is the charge accumulation jii (11
If the impurity concentration of is on the order of 10"c+w', then 1
017cta-' order.
このように本発明装置によれば、ソースＳ及び１１４７
０間の電圧ＶＯＳを所要の電圧に選定することにより、
ゲートＧへの微小電圧でオン・オフ動作を超高速をもっ
て行うことができる。In this way, according to the device of the present invention, the sources S and 1147
By selecting the voltage VOS between 0 to the required voltage,
On/off operations can be performed at extremely high speed by applying a minute voltage to the gate G.
尚、上述の例では、２つの量子井戸Ｗ１及びＷ２を有す
る構成とした場合であるが、量子井戸チャンネル層（２
）による井戸Ｗ１のみを有し、電荷蓄積層（１１は、電
荷の供給を行うことのできる比較的高不純物濃度の層と
し、これに例えばショットキーゲートによるゲート部（
６）を設けた構成とすることもできる。In the above example, the configuration has two quantum wells W1 and W2, but the quantum well channel layer (2
), the charge storage layer (11 is a layer with a relatively high impurity concentration that can supply charges), and a gate part (11) made of, for example, a Schottky gate.
6) may also be provided.
また、上述した例は移動キャリアが電子である場合につ
いて説明したがホールを移動キャリアとする場合に通用
することができ、この場合においては各部の導電型を前
述とは逆に選定すれば良い。Furthermore, although the above-mentioned example has been described for the case where the mobile carriers are electrons, it can also be applied to the case where the mobile carriers are holes, and in this case, the conductivity type of each part may be selected in the opposite manner to that described above.
また上述した例では極薄半導体構造をＧａＡｓとＡｊ！
ＧａＡｓとの組合せ構造とした場合であるが、ＩｎＡ
ｓとＩｎＳとの組合せ構造とすることもできる。Furthermore, in the above example, the ultra-thin semiconductor structure is made of GaAs and Aj!
In the case of a combination structure with GaAs, InA
It is also possible to have a combination structure of S and InS.
また、上述した例に限らず、量子井戸チャンネル層（２
）を複数個配列した構造とすることもできるなど種々の
変型構造を採ることができる。In addition, the quantum well channel layer (2
) can be arranged in a variety of different structures.
上述したように本発明装置においては、キャリアの移動
が、超薄膜半導体構造における共鳴トンネル現象を利用
したゲート部、すなわち制御電極を有するＦＥＴ構成と
したので、従前の各種ＦＥＴに比し格段に超高速動作が
可能となるものである。As mentioned above, in the device of the present invention, the movement of carriers is significantly improved compared to various conventional FETs because the FET structure has a gate section, that is, a control electrode, that utilizes the resonant tunneling phenomenon in an ultra-thin semiconductor structure. This enables high-speed operation.
第１図は本発明による超高速半導体装置の一例の路線的
拡大断面図、第２図Ａ−Ｃは本発明装置の動作の説明に
供するバンドモデル図である。
（１１は電で蓄積層、（２）は量子井戸チャンネル層、
（３）は電位障壁層、（４）及び（５）は第１及び第２
の電極、（６）はゲート部である。FIG. 1 is an enlarged linear cross-sectional view of an example of an ultrahigh-speed semiconductor device according to the present invention, and FIGS. 2A to 2C are band model diagrams for explaining the operation of the device according to the present invention. (11 is an electric storage layer, (2) is a quantum well channel layer,
(3) is the potential barrier layer, (4) and (5) are the first and second
(6) is the gate part.
Claims (1)
の間に介在する中間電位障壁層とを有する半導体超薄膜
構造を有し、 （ｄ）上記電荷蓄積層に第１の電極が設けられ、（ｅ）
上記量子井戸チャンネル層に第２の電極が設けられ、 （ｆ）上記電荷蓄積層の、上記第１の電極と上記第２の
電極との間に相当する位置にゲート部が設けられ、 （ｇ）上記中間電位障壁層の厚さは、上記第１の電極、
第２の電極、及びゲート部への印加電圧の選定によって
上記電荷蓄積層と上記量子井戸チャンネル層との間に波
動関数の重なりによって共鳴トンネル電流を生ぜしめ得
る厚さに選定されて成ることを特徴とする超高速半導体
装置。[Claims] Comprising: (a) a charge storage layer; (b) a quantum well channel layer; and (c) an intermediate potential barrier layer interposed between the charge storage layer and the quantum well channel layer. has a semiconductor ultra-thin film structure, (d) the charge storage layer is provided with a first electrode, and (e)
a second electrode is provided in the quantum well channel layer; (f) a gate portion is provided in the charge storage layer at a position corresponding to between the first electrode and the second electrode; (g ) The thickness of the intermediate potential barrier layer is the same as that of the first electrode;
By selecting the voltage applied to the second electrode and the gate portion, the thickness is selected to be such that a resonant tunneling current can be generated between the charge storage layer and the quantum well channel layer by the overlap of wave functions. Features of ultra-high-speed semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23849386A JPH0783111B2 (en) | 1986-10-07 | 1986-10-07 | Ultra high speed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23849386A JPH0783111B2 (en) | 1986-10-07 | 1986-10-07 | Ultra high speed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6393160A true JPS6393160A (en) | 1988-04-23 |
| JPH0783111B2 JPH0783111B2 (en) | 1995-09-06 |
Family
ID=17031067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23849386A Expired - Fee Related JPH0783111B2 (en) | 1986-10-07 | 1986-10-07 | Ultra high speed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783111B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5414274A (en) * | 1993-07-26 | 1995-05-09 | Motorola, Inc. | Quantum multifunction transistor with gated tunneling region |
| US5416040A (en) * | 1993-11-15 | 1995-05-16 | Texas Instruments Incorporated | Method of making an integrated field effect transistor and resonant tunneling diode |
| JPH08186271A (en) * | 1994-12-28 | 1996-07-16 | Nec Corp | Manufacturing method for tunnel transistor |
| WO2005117127A1 (en) * | 2004-05-31 | 2005-12-08 | International Business Machines Corporation | Quantum device, quantum logic device, method of driving quantum logic device, and logic circuit by quantum logic device |
-
1986
- 1986-10-07 JP JP23849386A patent/JPH0783111B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5414274A (en) * | 1993-07-26 | 1995-05-09 | Motorola, Inc. | Quantum multifunction transistor with gated tunneling region |
| US5416040A (en) * | 1993-11-15 | 1995-05-16 | Texas Instruments Incorporated | Method of making an integrated field effect transistor and resonant tunneling diode |
| JPH08186271A (en) * | 1994-12-28 | 1996-07-16 | Nec Corp | Manufacturing method for tunnel transistor |
| WO2005117127A1 (en) * | 2004-05-31 | 2005-12-08 | International Business Machines Corporation | Quantum device, quantum logic device, method of driving quantum logic device, and logic circuit by quantum logic device |
| KR100843492B1 (en) | 2004-05-31 | 2008-07-04 | 인터내셔널 비지네스 머신즈 코포레이션 | Quantum device, quantum logic device, method of driving quantum logic device, and logic circuit by quantum logic device |
| JPWO2005117127A1 (en) * | 2004-05-31 | 2008-07-31 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation | Quantum device, quantum logic device, method of driving quantum logic device, and logic circuit by quantum logic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0783111B2 (en) | 1995-09-06 |
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