JP2975630B2 - AD conversion method - Google Patents

Description

The present invention relates to an AD conversion method for converting an analog voltage to a digital signal, and more particularly, to an AD conversion method comprising a capacitor and an inverter.
The so-called AD converter using a chopper type comparator
Regarding the conversion method.

(B) Conventional technology Generally, an AD conversion circuit using a chopper type comparator is configured as shown in FIG.

The output of the chopper type comparator (1) for inputting the analog voltage V _IN and the reference voltage V _REF is applied to the control circuit (2), and the control circuit (2) outputs the counter (3) by the output of the chopper type comparator (1). Controls counting. The output of the counter (3) is converted into a voltage by the DA conversion circuit (4) and supplied to the chopper comparator (1) as a reference voltage _VREF .

The chopper type comparator (1) includes a switch S1 to which an analog voltage V _IN to be converted is applied, a switch S2 to which a reference voltage V _REF is applied, and switches S2 and S3, which convert the analog voltage V _IN and the reference voltage V _REF. It comprises a capacitor C selectively applied to the terminal a, an inverter INV having an input connected to the terminal b of the capacitor C, and a switch S3 connected between the input and output of the inverter INV.

The analog voltage V obtained by the AD conversion circuit shown in FIG.
A method of converting _IN to digital is shown in FIG. 4 and will be described with reference to FIG.

First, in FIG. 4A, the control circuit (2) closes the switch S3 and connects the input / output of the inverter INV to the inverter INV.
Threshold voltage, ie, after fixing to 1/2 of the power supply voltage V _DD, is applied to an analog voltage V _IN to the capacitor C closes switch S1. In this state, V _DD / 2
The voltage at −V _IN is charged.

In FIG. 4B, the control circuit (2) sets the counter (3) to a reference value, for example, "0", and generates a reference voltage V _REF of V _DD / 2 from the DA conversion circuit (4). . Then, the switch S1 and the switch S3 are opened, and the switch S2 is closed. In this state, the input voltage of the inverter INV is a voltage _{V DD / 2-V IN +} V DD / 2 obtained by superimposing voltage charged in the capacitor C to the reference voltage V _REF of the V _DD / 2. Therefore, if the analog voltage V _IN is smaller than V _DD / 2, the output of the inverter INV becomes L level, and if it is larger, the output becomes H level. That is, the comparison between the reference voltage V _REF = V _DD / 2 and the analog voltage V _IN is performed.

In FIG. 4 (c), the comparison result is H in FIG. 4 (b).
, The control circuit (2) sets the counter (3) to の of the positive maximum count value, and generates 3V _DD / 4 as the reference voltage V _REF . Then, only the switch S2 is closed. In this state, the input voltage of the inverter INV is a voltage obtained by superposing the voltage V _DD / 2−V _IN charged in the capacitor C on the reference voltage 3V _DD / 4. That is, the analog voltage V _IN is compared with the reference voltage 3V _DD / 4, and the analog voltage V _IN is
If it is smaller than _DD / 4, the output of the inverter INV becomes L, and if it is larger, it becomes H.

In FIG. 4D, the comparison result of FIG.
Of time, the control circuit (2) sets the counter (3) into 3/4 positive maximum count, for generating a reference voltage V _REF of 7V _DD / 8. Then, only the switch S2 is closed. In this state, the input voltage of the inverter INV is a voltage obtained by superposing the voltage V _DD / 2−V _IN charged in the capacitor C on the reference voltage 7V _DD / 8. That is, the analog voltage V _IN is compared with the reference voltage 7V _DD / 8. When the analog voltage V _IN is lower than the reference voltage 7V _DD / 8, the output becomes L, and when the analog voltage V _IN is higher, the output becomes H.

Thereafter, similarly, the count value of the counter (3) is output as a converted digital value by changing and comparing the reference voltage V _{REF in} steps of V _DD / 2 ⁿ .

(C) Problems to be Solved by the Invention However, according to the AD conversion methods shown in FIGS. 2 and 4, the threshold voltage of the inverter INV of the chopper type comparator (1) formed in the integrated circuit varies. The inconvenience that accurate AD conversion cannot be performed has occurred.

The cause is the voltage V _DD / 2−V charged in the capacitor C.
_IN was leaking during the conversion operation.

As shown in FIG. 3, a chopper type comparator (1)
Is constituted by a C-MOS inverter (5), and the switch S3 is constituted by a P-MOS (6). In this circuit, when the P-MPS (6) is turned on and off, the gate voltage changes due to the capacitance between the drain / source and the gate.
An N-MOS (7) having the same size as that of is connected to the gate.
Further, an N-MOS (8) for lowering the input / output voltage of the inverter INV to the ground voltage at one end is connected in series with the N-MOS (7). That is, before turning on the P-MOS (6), the N-MOSs (7) and (8) are turned on and the C-MOS (5) is turned on.
After lowering the gate voltage of
Turn off (8). Then, a control signal phi ₁ is applied to the gates of the N-MOS (7) of the P-MOS (6) φ
₂ are in opposite phases to each other to control ON and OFF of the P-MOS (6).

In such a circuit, the power supply _VDD and the _CM are provided by the P-type semiconductor region constituting the drain and source of the P-MOS (6).
Diode (9) shown by broken line between gates of OS (5)
Exists. Similarly, there is a diode (10) indicated by a broken line between the gate and the ground due to the N-type semiconductor region of the N-MOS (7).

Therefore, when the threshold voltage of the C-MOS (5) is lower than V _DD / 2 due to variations, for example, when the analog voltage V _IN is at the V _DD level, the capacitor C is charged with a voltage higher than V _DD / 2. Is done. Then, the terminal a of the capacitor C
When the reference voltage V _DD / 2 is applied, the gate voltage of the C-MOS (5) becomes negative, the diode (10) is forward biased, and the voltage charged in the capacitor C leaks. It will be.

(D) Means for Solving the Problems The present invention has been created in view of the above points,
A first switching element to which an analog voltage to be converted into digital is applied, a second switching element to which a plurality of types of reference voltages are applied, and the analog voltage or the reference voltage via the first or second switching element. A capacitor to which a voltage is switched and applied; an inverter to which the other terminal of the capacitor is connected; a third switching element connected between the input and output of the inverter; and an output of the inverter to generate the reference voltage A control circuit for closing the first and third switching elements, applying an analog voltage to the capacitor to charge the capacitor, and changing a voltage across the capacitor to a power supply voltage. A first step of superimposing an analog voltage on the intermediate voltage of
Closing a switching element, applying a predetermined reference voltage to the capacitor, obtaining an output from the inverter according to the voltage across the capacitor at this time, closing the first and third switching elements, A third step of applying an analog voltage to the capacitor to recharge the capacitor, setting the voltage across the capacitor to a state in which the analog voltage is superimposed on an intermediate voltage of the power supply voltage, and closing the second switching element; A fourth step of applying a reference voltage generated based on an output result of the inverter in the two steps to the capacitor, and obtaining an output from the inverter according to a voltage across the capacitor at this time; and a second switching element. Is closed, and the reference generated based on the output result of the inverter in the previous step. Applying a voltage to the capacitor, and repeating an operation of obtaining an output from the inverter according to the voltage across the capacitor at this time a predetermined number of times, by converting the analog voltage to digital by a method including: This is to eliminate a conversion error due to a variation in the threshold voltage of the inverter INV.

(E) Operation According to the above-described means, when the voltage charged in the capacitor is superimposed on the reference voltage V _DD / 2 and the comparison operation is performed, even if a leak occurs, the switch means is closed again in the next operation. By charging the capacitor with the difference between the gate voltage of the inverter and the analog voltage V _{IN in} a state in which the voltage is leaked, the leaked voltage can be compensated, and accurate comparison can be performed in the subsequent comparison operation.

(F) Embodiment The AD conversion circuit used in the AD conversion method of the present invention is the same circuit as the conventional one shown in FIG.

FIG. 2 is a diagram of a circuit state for illustrating the AD conversion method of the present invention, and shows a switch state of the chopper comparator (1) of FIG.

First, in FIG. 1A, the control circuit (2) closes the switch S3 and connects the input / output of the inverter INV to the inverter INV.
Threshold voltage, ie, after fixing to 1/2 of the power supply voltage V _DD, is applied to an analog voltage V _IN to the capacitor C closes switch S1. In this state, V _DD / 2
The voltage at −V _IN is charged. At this time, the threshold voltage of the inverter INV varies, and it is not necessary to fix the threshold voltage to V _DD / 2 accurately.

In FIG. 1 (b), the control circuit (2) sets a counter (3) to a reference value, for example, "0", and generates a reference voltage V _REF of V _DD / 2 from the DA conversion circuit (4). . Then, the switch S1 and the switch S3 are opened, and the switch S2 is closed. In this state, the input voltage of the inverter INV is a voltage _{V DD / 2-V IN +} V DD / 2 obtained by superimposing voltage charged in the capacitor C to the reference voltage V _REF of the V _DD / 2. Therefore, if the analog voltage V _IN is smaller than V _DD / 2, the output of the inverter INV becomes L level, and if it is larger, the output becomes H level. That is, the comparison between the reference voltage V _REF = V _DD / 2 and the analog voltage V _IN is performed.
At this time, even if the gate voltage of the inverter INV becomes a negative voltage or the power supply voltage V _DD or more and the voltage charged in the capacitor C leaks, the output of the inverter INV is not affected. Specifically, when the threshold voltage of the inverter INV is lower than V _DD / 2 and the analog voltage V _IN is the power supply voltage V _DD or a voltage very close to this voltage, the gate voltage of the inverter INV becomes a negative voltage. , The voltage charged in the capacitor C leaks.

In FIG. 1 (c), the control circuit (2) stores the output of H level in the embodiment as a result of the comparison of FIG. 1 (b), and stores the reference voltage V without changing the state of the counter (3). Generates _DD / 2. Then, switch S3 is closed and inverter INV
Is fixed to the threshold voltage V _DD / 2, the switch S1 is closed and the voltage V _DD / 2−V _IN is charged into the capacitor C again. Thereby, the charging voltage of the capacitor C leaked in FIG. 1B is compensated.

In FIG. 1 (d), the control circuit (2) sets the counter (3) to の of the positive maximum count value based on the stored comparison result H level in FIG. 1 (b), 3V _DD / 4 is generated as the reference voltage V _REF . Then, only the switch S2 is closed. In this state, the input voltage of the inverter INV is obtained by comparing the voltage V _DD / 2−V _IN charged in the capacitor C with the reference voltage 3V _DD / 4.
Is superimposed on the voltage. That is, the analog voltage V _IN is compared with the reference voltage 3V _DD / 4, and the analog voltage V _{IN
If IN} is smaller than the reference voltage 3V _DD / 4, the output of the inverter INV becomes L, and if it is larger, it becomes H. At this time, the reference voltage V _REF becomes
Since it is 3V _DD / 4, as shown in FIG.
The gate voltage of INV does not become negative. Therefore, the voltage charged in the capacitor C is maintained in the original state.

In FIG. 1A, the comparison result of FIG.
Of time, the control circuit (2) sets the counter (3) into 3/4 positive maximum count, for generating a reference voltage V _REF of 7V _DD / 8. Then, only the switch S2 is closed. In this state, the input voltage of the inverter INV is a voltage obtained by superposing the voltage V _DD / 2−V _IN charged in the capacitor C on the reference voltage 7V _DD / 8. That is, the analog voltage V _IN is compared with the reference voltage 7V _DD / 8. When the analog voltage V _IN is lower than the reference voltage 7V _DD / 8, the output becomes L, and when the analog voltage V _IN is higher, the output becomes H. It is H in the embodiment.

Thereafter, similarly, the count value of the counter (3) is output as a converted digital value by changing and comparing the reference voltage V _{REF in} steps of V _DD / 2 ⁿ .

(G) Effect of the Invention As described above, according to the present invention, the leakage of the charging voltage of the capacitor C in the first comparison operation is compensated by the next charging operation, so that the subsequent comparison operation is accurate. Becomes Therefore, there is an advantage that accurate AD conversion can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an operation state of a circuit for explaining an embodiment of the present invention, FIG. 2 is a circuit diagram of an AD conversion circuit using a chopper type comparator, and FIG. FIG. 4 is a circuit diagram showing a conventional AD conversion method. (1) Chopper type comparator, (2) Control circuit, (3) Counter, (4) DA conversion circuit, S1,
S2, S3: Switch, INV: Inverter, C: Capacitor

Continuation of front page (56) References JP-A-63-144617 (JP, A) JP-A-1-321728 (JP, A) JP-A-57-13813 (JP, A) (58) Fields studied (Int .Cl. ⁶ , DB name) H03K 5/08 H03M 1/34-1/48

Claims (1)

(57) [Claims] A first switching element to which an analog voltage to be converted into a digital signal is applied; a second switching element to which a plurality of types of reference voltages are applied; and the first or second switching element. A capacitor to which an analog voltage or the reference voltage is switched and applied, an inverter to which the other terminal of the capacitor is connected, a third switching element connected between the input and output of the inverter, and an output of the inverter. An AD conversion method for an AD conversion circuit, comprising: a control circuit that generates the reference voltage; closing the first and third switching elements; applying an analog voltage to the capacitor to charge the capacitor; A first step of setting a voltage between both ends to a state in which an analog voltage is superimposed on an intermediate voltage of a power supply voltage; Closing the switching element, applying a predetermined reference voltage to the capacitor, obtaining an output from the inverter according to the voltage across the capacitor at this time, closing the first and third switching elements, A third step of applying an analog voltage to the capacitor to recharge the capacitor, setting a voltage across the capacitor to a state in which the analog voltage is superimposed on an intermediate voltage of a power supply voltage, and closing the second switching element, A fourth step of applying a reference voltage generated based on an output result of the inverter in two steps to the capacitor, and obtaining an output from the inverter according to a voltage across the capacitor at this time; and a second switching element. Is closed, and the reference voltage generated based on the output result of the inverter in the previous step is closed. Was applied to the capacitor, AD conversion method for converting an operation to obtain an output corresponding to the voltage across the capacitor when the from the inverter and a fifth step of repeating a predetermined number of times, by an analog voltage to a digital voltage.