JPH05119859A - Reference voltage generating circuit - Google Patents

Abstract

PURPOSE:To provide the reference voltage generating circuit which is integrated into an integrated circuit, and in which a power supply voltage dependency and a temperature dependency do not exist, a reference voltage can be generated stably, and also, this reference voltage can be set freely on a user side. CONSTITUTION:This circuit is constituted of an operational amplifier 4 to which a negative feedback is applied by providing two MOS transistors Q1, Q2 as a pair in a difference input means, and connecting an output terminal to a negative input terminal. At least one of a pair of MOS transistors Q1, Q2 used for this difference input means consists of a MOS transistor structure having a floating gate 20. Also, in accordance with the charge quantity injected to the floating gate, a threshold voltage is varied, and a difference of the threshold voltages of a pair of MOS transistors is generated as an offset voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit, and more particularly to an improvement of a reference voltage generating circuit which uses an offset voltage of an operational amplifier having a pair of MOS transistors in a differential input stage as a reference voltage source.

[0002]

2. Description of the Related Art As a circuit for generating a reference voltage inside an IC (integrated circuit), a circuit shown in FIG. 5A and a circuit shown in FIG. 5B are known. FIG. 5A shows a resistance division type reference voltage generating circuit that obtains a reference voltage Vr by dividing a power supply voltage using a plurality of resistors R1 and R2, and FIG. 5B shows a pn junction diode. A reference voltage generation circuit of a type that obtains a reference voltage Vr from a forward breakdown voltage of D1 and D2 is shown.

By the way, the resistance division type reference voltage generating circuit shown in FIG. 5A has a power supply voltage dependency that the reference voltage fluctuates in accordance with the fluctuation of the power supply voltage. On the other hand, the reference voltage generating circuit shown in FIG. 1B does not have power supply voltage dependency, but has a drawback that the forward voltage of the pn junction fluctuates with temperature and thus has large temperature dependency.

Therefore, as disclosed in Japanese Patent Laid-Open No. 3-54614, a reference voltage generating circuit has been developed in which an offset voltage of a MOS transistor type operational amplifier is forcibly generated and the offset voltage is used as a reference voltage source. .. According to this reference voltage generation circuit, it is possible to obtain a reference voltage having almost no power supply voltage dependency and temperature dependency.

[0005]

However, in this reference voltage generating circuit, the difference between the threshold voltages of the pair of MOS transistors forming the differential input stage is used as the offset voltage,
Although used as a reference voltage, this reference voltage is fixed and cannot be freely set by the user.

The present invention has been made in view of the above circumstances, is incorporated in an integrated circuit, has no power supply voltage dependency and temperature dependency, and can stably generate a reference voltage. An object of the present invention is to provide a reference voltage generating circuit that allows a user to freely set the voltage.

[0007]

In order to achieve the above object, a reference voltage generating circuit of the present invention has two MOS transistors as a pair in a differential input stage and connects an output terminal to a negative input terminal. A negative-feedback operational amplifier, and at least one of a pair of MOS transistors used in the differential input stage has a MOS transistor structure having a floating gate, and charges injected into the floating gate. It is characterized in that the threshold voltage is made variable according to the amount and a difference between the threshold voltages of the pair of MOS transistors is generated as an offset voltage.

[0008]

In the reference voltage generating circuit of the present invention, the pair of MOS transistors used as the differential input section of the operational amplifier are composed of transistors having different threshold voltages. The difference between the threshold voltages of the MOS transistors is extremely stable because it is not affected by the power supply voltage or the temperature. Since the output terminal of the operational amplifier is connected to the negative input terminal for negative feedback and the operational amplifier has a source follower configuration, the difference in the threshold voltage appears as an offset voltage forcibly. In the operational amplifier, it is desirable that the offset voltage be close to zero.
In the present invention, by forcibly generating the offset voltage and using the offset voltage as the reference voltage, it is possible to obtain the reference voltage having almost no power supply voltage dependency or temperature dependency. Moreover, in the present invention, at least one of a pair of MOS transistors that generate such an offset voltage has a MOS transistor structure having a floating gate, and a threshold value is set according to the amount of charge injected into the floating gate. The voltage is variable. As a result, the difference in threshold voltage between the pair of MOS transistors changes according to the amount of charge injected into the floating gate, and the user can arbitrarily set the reference voltage appearing as the difference in threshold voltage. become.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A reference voltage generating circuit according to an embodiment of the present invention will be described in detail below with reference to the drawings. 1 is a schematic diagram of a reference voltage generating circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the switching circuit shown in FIG. 1, and FIG. 3 is FIG.
FIG. 4 is a schematic sectional view of a MOS transistor forming the differential input stage shown in FIG. 4, and FIG. 4 is a circuit diagram showing the circuit shown in FIG. 1 in a simplified manner.

As shown in FIG. 1, a reference voltage generating circuit 2 according to an embodiment of the present invention includes a pair of MOS transistors Q.
It is composed of an operational amplifier 4 having 1 and Q2 as input stages. In the figure, Q3 and Q4 are a pair of load transistors, which are, for example, P-channel MOS transistors and constitute a current mirror circuit. Q5 is a constant current source composed of, for example, an N-channel MOS transistor. A differential amplifier circuit is configured by these MOS transistors Q1 to Q5.

Q6 and Q7 are Ms constituting a level shift stage.
It is an OS transistor, and Q6 is, for example, a P-channel M
It is composed of an OS transistor, and Q7 is composed of, for example, an N-channel MOS transistor. The output signal of the differential amplifier circuit is output to the outside through this level shift stage. Also, the MOS transistor Q
The gate electrode of 1 is the negative input terminal, and the MOS transistor Q
The second gate electrode serves as a positive input terminal.

In the present embodiment, as shown in FIG. 4, the output terminal of the operational amplifier 4 having such a configuration is connected to the negative input terminal for negative feedback, and the positive input terminal is connected to the ground level. It has a source follower configuration grounded at. The positive input terminal is not necessarily grounded to the ground level and may be grounded to another reference potential.

In the present embodiment, the MOS transistor Q, which is at least one of the pair of MOS transistors forming the input stage of the operational amplifier 4 as described above.
2 has a structure having a floating gate, and is configured so that a difference in threshold voltage is generated and the difference is variable with respect to the other MOS transistor Q1. Normally, a pair of transistors forming a differential input stage in an operational amplifier are formed in the same size, structure and material so as to have the same characteristics. This is because it is desired to set the offset voltage to 0V.

However, in this embodiment, a difference is provided in the threshold voltage, and the difference is forcibly expressed as an offset voltage. That is, in the operational amplifier, if the threshold voltages of the pair of input MOS transistors Q1 and Q2 are Vth1 and Vth2, the offset voltage Vos is expressed by the following equation. Absolute value of Vos = absolute value of (Vth1-Vth2) Then, when the operational amplifier 4 has a source follower configuration, this offset voltage Vos is output with reference to the ground level ground voltage connected to the positive input terminal. The reference voltage Vout is output from the terminal.

In this embodiment, the MOS transistors Q1,
The threshold potentials of Q2 are not simply different, but at least one of the MOS transistors Q2 has a structure having a floating gate. Generally, a MOS transistor structure having a floating gate is, for example, EPROM or E ² PRO.
It is used as a memory cell such as M. Therefore, the MOS transistor Q2 of the present embodiment can be manufactured by the same process as in manufacturing these memory cells.

M of this embodiment used as a differential input stage
An example in which the OS transistors Q1 and Q2 are formed on a semiconductor substrate is shown in FIG. As shown in FIG. 3, a P-well 12 which is a P-type diffusion region is formed on the surface of a semiconductor substrate made of, for example, an N-type silicon substrate, and the surface of the P-well 12 is selected as an element isolation region. The oxide region 14 and the gate insulating film 16 are formed. In the MOS transistor Q1, the gate electrode layer 18 is formed on the gate insulating film 16, and in the MOS transistor Q2, the floating gate 20, the intermediate insulating film 24, and the control gate 22 are laminated in this order. On the surface of the P well 12 located on both sides of each gate, a source / drain region 26 composed of, for example, an N-type diffusion layer is formed by means such as an ion implantation method. In this embodiment, both MOS transistors Q1 and Q2 are N-channel transistors,
It may be configured to be a P-channel transistor.

Charge is injected into the floating gate 20 of the MOS transistor Q2 from the substrate 10 side by the hot electron effect or tunnel effect. The threshold voltage of the MOS transistor Q2 varies according to the amount of charge injected into the floating gate 20. If the threshold voltage of the MOS transistor Q2 fluctuates, the difference in threshold voltage between the MOS transistors Q1 and Q2 also fluctuates, and the offset voltage of the operational amplifier 4 shown in FIG. The reference voltage Vout output from the output terminal also changes. Therefore, by controlling the amount of charges injected into the floating gate 20, it is possible to arbitrarily change the reference voltage output from the output terminal of the operational amplifier 4.

As described above, the operational amplifier 4 shown in FIG.
MOS transistor Q2 that constitutes the differential input stage of
Is a structure having a floating gate,
In order to inject charges into the floating gate 20 which constitutes a part of the MOS transistor Q2, as shown in FIG. 1, the peripheral connection terminals of the MOS transistor Q2 are provided with reference voltage setting switching circuits 30, 32 and 34. Is preferred. These switching circuits 30, 32,
Reference numeral 34 is a circuit for switching between a reference voltage setting mode in which charges are injected into the floating gate 20 of the MOS transistor Q2 and a normal mode in which a normal operational amplifier operation is performed. Details of these switching circuits are shown in FIG.

Each switching circuit 30, 32, 34 has
Although not particularly limited, for example, each is composed of a pair of MOS transistors 36, 38, 40, 42, 44, 46. Then, one of the transistors 36, 40, 44 is
Connected to the transistor Q4, the transistor Q5, and the positive input terminal Vin so that the operation of a normal operational amplifier is performed. Also, the other transistors 38 and 4
Reference numerals 2 and 46 are connected to a circuit for injecting a predetermined amount of charges into the floating gate 20 so as to change the threshold voltage of the MOS transistor Q2. Switching of the connection of these circuits is performed by one of the MOS transistors 3
The threshold voltage of 6, 40, 44 is Va, and the other MO
Set the threshold voltage of the S transistors 38, 42 and 44 to Vb
By applying the respective threshold voltages to the gate electrode, the operation mode is switched between the normal operational amplifier operation mode and the reference voltage setting mode.

One M for setting the reference voltage setting mode
The OS transistors 38, 42 and 46 are further connected to monitoring switching circuits 48, 50 and 52, respectively. Each switching circuit 48, 50, 52
Are not particularly limited, for example, a pair of MOSs, respectively.
It is composed of transistors 54, 56, 58, 60, 62 and 64. Then, one of the transistors 54, 58, 6
Reference numerals 2 are connected to power supply circuits for injecting charges into the floating gates 20, respectively. Further, the other transistors 56, 60, 64 are connected to a monitoring circuit for detecting how much the threshold voltage of the MOS transistor Q2 has changed due to the charges injected into the floating gate 20. Switching of the connection of these circuits is performed by switching one of the MOS transistors 54, 58,
The threshold voltage of 62 is Vc, the threshold voltages of the other MOS transistors 56, 60 and 64 are Vd, and the respective threshold voltages are applied to the gate electrode, whereby the charge injection mode and the threshold voltage are set. Switch to the value voltage monitoring mode.

In the reference voltage setting mode, the MO shown in FIG.
The threshold voltage Vb is applied to the S-transistors 38, 42 and 46, and the switching circuits 48, 50 and 52 for monitoring are switched at minute time intervals to switch between the charge injection mode and the threshold voltage monitoring mode. That is, the MOS transistor Q2 is monitored while monitoring the change in the threshold voltage of the MOS transistor Q2.
The stress voltage is applied to the source part, the drain part, and the gate part of No. 2, and charges are injected into the floating gate 20 to set the threshold voltage of the MOS transistor Q2 to a predetermined value. When injecting charges into the floating gate 20, the MOS transistor Q
The voltage VS applied to the source part of 2 is 0 volt, the voltage VD applied to the drain part is 10 to 15 volt, and the voltage VG applied to the gate part is 10 to 1 volt.
It is about 5 volts. If these voltages are applied with a minimum pulse width of about 0.1 μs while monitoring the stress voltage while controlling the number of pulses, the threshold voltage Vth2 of the MOS transistor Q2 can be set within a wide range of 0 to several volts. It can be controlled accurately. The threshold voltage Vth
2 is a set voltage Vo of the reference voltage to be output with respect to the threshold voltage Vth1 of the MOS transistor Q1 shown in FIG.
A stress voltage is applied to the MOS transistor Q2 while monitoring so that the voltage becomes a value obtained by adding ut. That is, the stress voltage is applied so as to satisfy the relationship of the following equation. Absolute value of (Vth2-Vth1) = Absolute value of Vout

In order to change the threshold voltage of the MOS transistor Q2 again, the charge injected into the floating gate 20 of the MOS transistor Q2 may be extracted before the above-mentioned operation is performed. In the reference voltage generation circuit 2 of the present embodiment, a pair of MOS transistors Q1 used as a differential input section in the operational amplifier 4
Q2 is composed of transistors having mutually different threshold voltages. Since the difference in threshold voltage between the MOS transistors Q1 and Q2 is not affected by the power supply voltage or temperature,
It is extremely stable. Then, since the output terminal of the operational amplifier 4 is connected to the negative input terminal for negative feedback and the operational amplifier 4 has the source follower configuration, the difference in the threshold voltage appears as an offset voltage forcibly and appears. Can be obtained as a stable reference voltage.

Moreover, in this embodiment, at least one of the pair of MOS transistors Q2 for generating such an offset voltage has a MOS transistor structure having the floating gate 20 and is injected into the floating gate 20. The threshold voltage is variable according to the amount of electric charge that is generated. As a result, the difference in threshold voltage between the pair of MOS transistors Q1 and Q2 changes according to the amount of charge injected into the floating gate 20, and the user arbitrarily sets the reference voltage appearing as the difference in threshold voltage. It becomes possible to do.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, in the above-described embodiment, one MOS transistor Q2 forming the input stage of the operational amplifier 4 is used.
Has a structure having the floating gate 20,
The other MOS transistor is connected to the floating gate 2
The structure having 0 may be adopted, or both the MOS transistors Q1 and Q2 may have the structure having floating gates. In order to ensure the symmetry of the circuit and improve the temperature characteristics, both MOS transistors Q
It is desirable that 1 and Q2 have a structure having a floating gate. From this point of view, the switching circuits 30, 32, and 34 as described above are connected to both MOS transistors.
It is desirable to attach it to the peripheral connection terminals of the transistors Q1 and Q2.

Further, in the present invention, the specific configuration of the above-mentioned switching circuits 30, 32, 34, 48, 50 and 52 is not particularly limited, and for example, complementary switching circuits may be used. Further, in the present invention, the operational amplifier 4 is used without using the switching circuit as described above.
A stress voltage for setting the threshold voltage of the MOS transistor Q2 may be applied to the power supply voltage terminals Vdd and Vss and the input terminal Vin.

[0026]

As described above, according to the reference voltage generating circuit of the present invention, the output terminal of the operational amplifier is connected to the negative input terminal for negative feedback and is used as a differential input section in the operational amplifier. MOS transistor of
It is composed of transistors with different threshold voltages, and the difference between the threshold voltages is forcibly generated as an offset voltage and used as a reference voltage, so a reference voltage that is not significantly affected by power supply voltage or temperature is obtained. be able to.

Moreover, in the present invention, at least one of the pair of MOS transistors for generating such an offset voltage has an M having a floating gate.
The OS transistor structure is used, and the threshold voltage is variable according to the amount of charges injected into the floating gate. As a result, the difference in threshold voltage between the pair of MOS transistors changes according to the amount of charge injected into the floating gate, and the user sets the reference voltage appearing as a difference in threshold voltage to about 0 to several volts. It can be set arbitrarily within a wide voltage range.

Further, since such a reference voltage generating circuit has a structure in which MOS transistors having a floating gate are combined, it can be easily formed on a semiconductor substrate and is easily incorporated in an integrated circuit. It is possible to

[Brief description of drawings]

FIG. 1 is a schematic diagram of a reference voltage generating circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a switching circuit shown in FIG.

3 is a schematic cross-sectional view of a MOS transistor forming the differential input stage shown in FIG.

FIG. 4 is a circuit diagram showing the circuit shown in FIG. 1 in a simplified manner.

FIG. 5 is a reference voltage generation circuit according to a conventional example.

[Explanation of symbols]

 2 ... Reference voltage generating circuit 4 ... Operational amplifier 20 ... Floating gate 30, 32, 34 ... Switching circuit for setting reference voltage 48, 50, 52 ... Switching circuit for monitoring Q1-Q7 ... MOS transistors

Claims (2)

[Claims] 1. A pair of two MOS transistors in a differential input stage having a pair of output terminals connected to an output terminal of a negative input terminal for negative feedback and used for the differential input stage. At least one of the MOS transistors is an MO having a floating gate.
With an S-transistor structure, the threshold voltage is variable according to the amount of charge injected into the floating gate,
A reference voltage generation circuit that generates a difference in threshold voltage between a pair of MOS transistors as an offset voltage. 2. An MO having the floating gate.
The peripheral connection terminal of the S transistor is provided with a switching circuit for switching between a normal operational amplifier operation mode and a reference voltage setting mode for injecting charges into the floating gate to change the threshold voltage. The reference voltage generating circuit according to claim 1, wherein the reference voltage generating circuit is provided.