JPS6217191B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a voltage detection circuit.

More specifically, the present invention relates to a voltage detection circuit with a novel configuration that allows detection of various voltages in electronic equipment to be performed easily and by arbitrary adjustment.

Conventionally, voltage detection circuits adjust the set voltage at which the detected voltage is to be detected using a variable resistor or an appropriate selection resistor, and not only is the adjustment process complicated, but the cost of adjusting the set voltage is The more precise the process, the more the cost increases, making it difficult to maintain cost and performance.
In particular, this was caused by variations in the passive active elements used in the voltage detection circuit, and was therefore inversely related to the yield of the elements. In general, in electronic devices, the passive and active elements that operate and function the electronic device, including the voltage detection circuit, are integrated into one or several chips as an integrated circuit (IC), so the yield of the voltage detection circuit itself is low. Since this directly affects the yield of ICs, there has been a long-awaited circuit configuration that can easily or not adjust the set voltage even if the characteristics of these elements vary, and that can also improve the yield of integrated circuits. .

A first object of the present invention is to provide a voltage detection circuit whose set voltage can be easily adjusted.

A second object of the present invention is to further achieve the first object and improve the yield of the voltage detection circuit itself, while accepting variations in each element constituting the voltage detection circuit.

A third object of the present invention is derived from the second object, and is to improve the yield of the entire integrated circuit including the voltage detection circuit.

In order to achieve the above objective, it is necessary to ensure that variations in the characteristics of the passive and active elements that make up the voltage detection circuit do not result in variations in the voltage detection circuit as a whole.In other words, ideally the set voltage value of the voltage detection circuit should be The circuit configuration must be uniquely determined.

The configuration of a voltage detection circuit according to the present invention that satisfies the above requirements is shown in a block diagram in FIG. 1 is a reference voltage circuit, which generates a reference voltage Vst that weakly depends on or does not depend on the voltage to be detected; This is a circuit that directly generates a set voltage or generates a reference voltage that is strongly dependent on the set voltage. Reference numeral 2 denotes a detected voltage conversion circuit, which is either the detected voltage itself or a circuit that is strongly dependent on the detected voltage. 3 is a comparison circuit which compares the reference voltage 1 and the converted voltage Vd of the two detected voltages. The set voltage is exactly the voltage at which this reference voltage and the converted voltage, that is, the comparison voltage input to the comparator circuit, match.In other words, an appropriate reference voltage and converted voltage of the detected voltage are selected from the desired set voltage. It is. Of course, depending on how strict the set voltage is required, adjustment may be necessary due to the slight dependence of the set voltage on actual device characteristics. Reference numeral 4 is an adjustment circuit including this adjustment means, and there are two types: one for adjusting 1 and the other for adjusting 2. In other words, it is a circuit that adjusts either or both of the reference voltage serving as a comparison voltage and the converted voltage of the detected voltage. Furthermore, 1 up to the above,
In circuits 2, 3, and 4, the power to operate them, that is, the current consumption, is constantly flowing, so for example, in portable electronic devices that are powered by batteries with limited power, this voltage The detection circuit is driven by sampling to minimize current consumption. 5 is a pulse generation circuit that generates pulses φ ₃ (φ ₅ , φ ₆ , φ ₇ , φ ₈ ) necessary for this sampling drive, and each circuit 1, 2, 3, 4,
Alternatively, some of the circuits may be sampled.
Pulses are sent and each circuit operates by sampling. However, the output of the comparator circuit 3 is often required at all times, and therefore a hold circuit is required to hold the output of the comparator circuit when sampling is not being performed. 6 is this hold circuit, and pulses necessary for this hold circuit are sent from 5 in the same way as for sampling. In this overall voltage detection circuit, the core parts are 1, 2, and 3, and in the present invention, the set voltage is determined almost uniquely without depending on the characteristics of each individual element. ing.

A specific example of the present invention is shown in FIG.
Each block surrounded by a dash-dotted line corresponds to each block in FIG. The active element used is an insulated gate field effect transistor (hereinafter referred to as MOS).

First, the pulse generation circuit 5 will be explained. The pulse generating circuit 5 is composed of a shift register 7 and a NAND circuit 8. When the signals shown in Fig. 7-a are input to φ ₁ and φ ₂ , φ ₂ is shifted by half the clock of φ ₁ by the shift register (flip-flop) 7, and the signal φ ₂ is output to Q, so that 8 A differential pulse as shown in Fig. 7-a is output from the output _φ3 . For example, if φ ₁ is 64 Hz and φ ₂ is 1/2 Hz, the low level at φ ₃ is 1/128 seconds and the high level is (2-1/128) seconds, so the so-called low level width is extremely small. A pulse (differential pulse) will be generated.
With such a differential pulse, 1, 2, 3, 4,
6, each circuit is activated.

Further, the shift register (flip-flop) 7 mentioned above is constructed as shown in FIG. Inverter 93
Since the CL signal is in opposite phase, the switching transistors N-channel transistor (hereinafter referred to as NT) 94 and P-channel transistor (hereinafter referred to as PT) 95 are turned on when CL is high.
W by an inverter consisting of NT96 and PT97
Invert and write. Therefore, at that time Q
= is. NT102 and PT103 are inverters that invert Q so that =W. At that time
NT98 and PT99 are off. NT98 and PT99 turn on only when CL goes low, so
This =W is inverted by the inverter consisting of NT100 and PT101, and Q===, so
The Q output will be held. At this time NT
94 and PT95 are off. In other words, even if CL is low and W changes, Q does not change, and only when CL goes high is the change in W transmitted to Q. Therefore, the signal shifted by W by half a clock of CL becomes The shifted and inverted signal of W will appear on Q. In this sense, a shift register (flip-flop) is formed as shown in FIG.

Now, the current in each circuit 1, 2, 3, and 4 flows only when _φ3 is low, and each circuit performs its original intended operation, so from the above example, the current consumption of each circuit is on average. It can be made at 1/256 and low power can be achieved. The first feature of the present invention is that the voltage detection circuit is operated by this differential pulse.

Next, reference voltage circuit 1 will be explained. When _φ3 is low, NT10 is off, PT11 is inverter 9
Since ₃ becomes high, it is off, so the static characteristics at 1 are unrelated to 10 and 11 at this time. Regarding 16, as shown in Figure 3-a, NT42 and PT54 are off, so 42 and 5
4 is unrelated. Conversely, when _φ3 is high, PT1
2 is off and NT10 is on, so the drain potential of 10 is low, NT14 is off, and PT1
1 is turned on, so no current flows through each conductive path at this time. Also in 16, PT43 is off, NT
42 is on, and therefore NT, 44, 45, and 50 are off, so no current flows. At the same time, PT54 is on, and therefore PT51 is off, so resistor 1
No current flows through 7 and 18 either. The first of the characteristics is taken into account.

The reference voltage generated when φ ₃ is low must have a configuration that is almost independent of the voltage to be detected and the power supply voltage (V _DD ), and has almost no temperature characteristics. Therefore, in this specific example, the difference between the threshold voltages of the MOS is used as the reference voltage. In order to create different threshold voltages for MOS, it is preferable to make the threshold voltages different by doping the gate channel by ion implantation. Due to differences in gate film thickness or substrate concentration, the threshold voltage that characterizes MOS,
This is because the temperature characteristics of the conductance coefficient (α mobility) are considerably different between MOSs having different threshold values.
Also, in doping the channel below the gate, doping donor ions with PT or acceptor ions with NT has a strong influence on the concentration characteristics, just as changing the base concentration. Ultimately, it is best to do channel doping by doping acceptor ions with PT or donor ions with NT. The threshold shift voltage lowered by doping is given by qNnetτox where the elementary charge is q, the relative permittivity of the gate insulating film is εox, the permittivity of vacuum is εo, the thickness of the gate insulating film is τox, and the net implantation amount is Nnet. This is because it can be said that the shift amount itself has no temperature characteristics. Furthermore, variations in the absolute value of the conductance coefficient (α mobility) in the same geometric dimensions can be corrected experimentally, and variations in the temperature characteristics are also much smaller than in the other cases mentioned above. An example of an acceptor ion for doping with PT is ¹¹ B ⁺ , and an example of a donor ion for doping with NT is ³¹ P ⁺ . In the figures from FIG. 2 onwards, transistors having threshold voltages shifted by such channel doping are indicated by dashed lines under the gates. In this example, only PT is doped, so NT is doped.
The substrate concentration is determined to match the threshold voltage of PT. To explain with reference to FIG. 4-a, in a normal complementary MOS (hereinafter referred to as C-MOS) IC, a P ^- well 56 is formed on an N ^- silicon substrate 55, and the source 57 and drain 58 of the PT. Together with or separately, an isolation layer 63 of NT is formed by a P-type diffusion layer or ion implantation.
together with the source 60 and drain 61 or separately
A PT isolation layer 62 is formed by an N-type diffusion layer or ion implantation. 59 is a clean gate insulating layer, 64 is a field insulating film,
65 is a metal used for the gate electrode, substrate, source, drain electrode, or wiring, such as aluminum. After 59 is formed, use a resist mask to cover channels other than those to be doped, and dope ions into the desired channel from above the gate insulating film to create a transistor with the low threshold voltage mentioned above. There is no change.
Of course, this channel doping may first be applied to all channels of transistors of the same polarity, and then applied only to desired transistors. All we want is a difference in threshold voltage.

In order to determine the threshold value of NT according to such a low threshold PT, it is sufficient to lower the concentration appropriately when forming the P ^- well 56, or even if the concentration of NT 56 is relatively high, all NTs may be Donor ions may be doped into the channel after forming the gate insulating film. In any case, the advantage of using the difference in threshold voltage due to channel doping as the reference voltage is stability against temperature fluctuations and power fluctuations.
As long as the stability of the voltage is guaranteed, it is possible to obtain a uniform voltage as the reference voltage during the manufacturing process.

The second feature of the present invention is a reference voltage that is stable against such temperature fluctuations, power supply fluctuations, and manufacturing process fluctuations. Next, the circuit will be explained.

Conductance coefficient of PT12 = mobility ×
εoεox/τox×channel width/channel length and PT15
The ratio of the conductance coefficient of NT13 to the conductance coefficient of NT
If the ratio of the conductance coefficients of PT12 and NT14 is equal to the ratio of the conductance coefficients of PT14, and if NT13 and NT14 are placed close to each other on the IC chip and the threshold values are made to have extremely good matching, the difference between the threshold voltage VTP of PT12 and the threshold voltage VGTP of PT15 will be
VTP - VGTP = Vst is obtained in the positive direction with respect to the ground potential. For example, the ratio of the conductance coefficients can be set to 1. Also of course 12,
The channel lengths in 15, 13, and 14 are made equal. Otherwise, due to differences in types such as diffusion, the depth varies and it is difficult to match the ratio of conductance coefficients. The reference voltage Vst obtained in this way is generally buffered by a volume follower 16, and its output is, in principle,
Since it is divided by the high resistance 17, 18, the final reference voltage Vst=R ₂ /R ₁ +R ₂ Vst.

The operational amplifier constituting the voltage follower is constructed as shown in Figure 3-a. When Vc is low
NT42 is off, and PT54 is turned off by inverter 53.
is also turned off, supplying current to each conductive path.
PT43 has a higher threshold voltage and lower conductance coefficient than NT44, so the bias voltage VB is
Biased slightly above the NT threshold voltage. The inverting input transistor NT46 and the non-inverting input transistor NT47 are devices with the same geometric dimensions and the same electrical characteristics, and are similar to the complementary load transistor PT48.
PT49 is also an element with the same geometric dimensions and the same electrical characteristics. If the potential of V _I and V _IN is higher than the threshold voltage of NT46 and NT47, NT45
Since the current flowing into PT49 and PT
The ratio of the conductance coefficients of 51 to NT45 and NT5
An operation that completely amplifies only the difference voltage between V _I and V _NI by taking twice the ratio of the conductance coefficient of 0 and placing them close to each other to make the threshold voltages of 49 and 51 and 45 and 50 equal. An amplifier can be made. At this time, it is preferable to make the channel lengths equal to 49 and 51, and 45 and 50, and to determine the ratio by the channel width. Also, the conductance coefficient is 5
If 0,51 is made much larger than 45,46,47,48,49, the amplification output stage consisting of 50,51 will have low impedance, and the frequency crossover point at which the gain is 1 will be 45,46. ，
It is considerably higher than the crossover point of the differential amplifier stage composed of 47, 48, and 49, and even if it is a voltage follower like 16, the phase delay is less than 180° at the crossover point, so oscillation is not possible. do not. Also, at this time, if the conductance coefficient is made large, it is necessary to make the channel width large, and if the channel width is made large, 51
The feedback capacitance that parasitically arrives between the drain and gate of
With C ₂ and the gate film capacitance C ₁ attached to the gate of 51, the total capacitance of C ₁ +C ₂ × (amplification output stage gain) appears to be attached to the drain of 49, making the frequency characteristics even more stable. Referring to Fig. 3-b, if the gate and drain of the PT 51 overlap more than 59 in Fig. 4-a, as shown in Fig. 52, the channel width is large, so the capacitance _C2 becomes large. Also, the gate-source capacitance C ₃ and the gate-substrate capacitance C ₄ are connected in parallel to form a composite capacitance C ₁ , which becomes the gate-power capacitance, which also increases due to the large channel width. be. In order to achieve further stability against oscillation, the feedback capacitance can be arbitrarily increased by increasing the overlap between the gate and the drain of 52. Further, in Fig. 3-b, each number in the figure indicates the same location as in Fig. 4-a.

Another problem with the operational amplifier shown in Fig. 3-a is the offset voltage that occurs in the differential stage, but this is in principle on the order of several mV, and the pulse of the low level signal of the differential pulse of the pulse generating circuit 5 If the width is made large to a certain extent, the current flowing into the constant current source 45 of the operational amplifier can be made small, so that the offset voltage can be kept small. This is because if the pulse width is large to some extent, the response of the operational amplifier can be lowered. On the other hand, the temperature characteristics and voltage characteristics of the offset voltage of an operational amplifier as shown in FIG. 3-a are extremely small and do not pose a problem.

The resistors 17 and 18 can be constructed in the same manner as shown in FIG. 4-b. In other words, in C-MOS, a P ^- well layer formed by diffusion or ion implantation can be used as a resistor, and a P-type or N-type layer formed by diffusion or ion implantation to form the source/drain and isolation layer, as well as polycrystalline silicon. It can be used. FIG. 4-b illustrates the case where a resistor is made by a P ^- well. On the other hand, the resistor can be composed of a MOS as shown in 71 in FIG. 4-c, or a diode as shown in 72 in FIG. 4-d depending on the manufacturing process. In this specific example shown in FIG. 2, since Vst can be determined only by the resistance ratio of this resistor, this ratio naturally has no temperature characteristics or voltage characteristics. From the above, the third feature of the present invention is that linear conversion of the difference in threshold voltage is used as the reference voltage, and this linear conversion is determined by the ratio of the resistors. In other words, this is because Vst = R ₂ /R ₁ +R ₂ Vst, and when R ₁ = 0, Vst = Vst, which is the same as when 17 and 18 are not added. Also, it is equivalent to outputting the outputs Vst of 14 and 15 as Vst, and the comparator 4 of this specific example
Since 0 is a high impedance input of a MOS input as shown in FIG. 3-a, such an output form is also possible. In addition, the reference voltage can be used for silver oxide batteries, nickel cadmium batteries, mercury batteries, etc.
It can be input to the comparator 40 as Vst or directly as Vst, or the forward rising voltage of a diode or the Zener voltage of a Zener diode can be used as something similar to the threshold of a MOS. As is well known, the temperature characteristics of the Zener voltage are opposite to the temperature characteristics of the rising voltage of a diode, so for example, connect them in series as shown in Figure 4-e, 74 and 75, and connect them as a resistor with ₃ .
NT73s that are turned off may be connected in series, and the forward rising voltage of the Zener diode may be used as the reference voltage.

Next, the detected voltage conversion circuit 2 will be explained. Like 16, 19 is configured as shown in Figure 3-a, so it operates as expected when _φ3 is low, and when _φ3 is high, each current path and resistor 20, 21, 22,
No current flows through 23 and 24. Since 19 is a voltage follower, the detected voltage VdΓ is output from V ₀ in Figure 3, and it is divided by a high resistance, and if r ₁ + r ₂ + r ₃ + r ₄ = r, then each
Voltage at ₁ point C: Vc ₁ = r ₁ /R + rVdΓ, Vc ₂ = r ₁ + r ₂ /R + rVdΓ at ₂ points, Vc ₃ = r ₁ + r ₂ + r at ₃ points.
₃ /R+rVdΓ, c The detected voltage is linearly converted to Vc ₄ =r/R+rVdΓ at _four points.

Resistors that perform such linear conversion are 17, 18
Similarly, it is configured as shown in Figure 4-b. 55 is N ^-
It is a silicon substrate, and 56 is a P ^- well layer which is formed at the same time as forming the NT substrate. Further, 63, 66, 67, 68, 69, and 70 are P-type layers, which are formed simultaneously when forming the source and drain of the PT. For example, 63 is grounded by aluminum wiring, 67 is connected to _c1 , 68 is connected to _c2 , and 6
9 corresponds to _c3 , 70 corresponds to _c4 , and 66 is connected to the output of 19 by, for example, aluminum wiring. Also 63,6
The resistance between 7 and 68 is 24 r ₁ , and the resistance between 67 and 68 is 23
The resistance between r ₂ and 68 and 69 corresponds to r ₃ of 22, the resistance between 69 and 70 corresponds to r ₄ of 21, and the resistance between 70 and 66 corresponds to R of 20. Reference numeral 64 indicates a field insulating film, and reference numeral 65 indicates a contact between aluminum and the P-type layer. The advantage of making a resistor with a uniform P ^- layer in this way is that the ratio of the resistor does not have temperature or voltage characteristics, and the other reason is that only the ratio matters. This is because it can be easily and accurately determined by geometric dimensions. In this case as well, it is preferable to keep the width of the resistor constant and take the ratio of the lengths of the resistors as shown in FIG. 4-b.

The reason why four points, C ₁ , C ₂ , C ₃ , and C ₄ are taken, is that FIG. 2 is a specific example in which the detection setting voltage is adjusted using 2 bits. A fourth feature of the present invention is that the detected voltage conversion circuit linearly converts the detected voltage, and this linear conversion is determined by the ratio of the resistors. Also, when R=0, Vc ₄ =
VdΓ, and the detected voltage itself is switched to switch 3.
You can put it in 9. The converted voltage of the detected voltage and the reference voltage become the comparison voltage of the comparator.

Next, the adjustment circuit 4 will be explained. Reference numeral 4 denotes a comparison voltage adjustment circuit that adjusts one or both of the comparison voltages input to the comparator 3. This specific example in FIG.
It is a bit, and can be digitally adjusted to four states (i) to (iv) depending on the state of the signals (b ₁ , b ₂ ). 0 represents low and 1 represents high.

(i) (b ₁ , b ₂ ) = (1, 1) Vd = Vc ₁ (ii) (b ₁ , b ₂ ) = (1, 0) Vd = Vc ₂ (iii) (b ₁ , b ₂ ) = (0, 1) Vd = Vc ₃ (iv) (b ₁ , b ₂ ) = (0, 0) Vd = Vc ₄ (i) When NAND 28 input is (1, 1), its output is 0, the PT gate input of the transmission switch 33 is 0, and the NT gate input is 1 due to the inverter 32, so it is turned on and Vd=
Vc ₁ potential is transferred. Since the NAND 29 input is ₂ = 0 by the inverter 27 and (1, 0), its output is 1, the PT gate input of the transmission switch 35 is 1, and the NT gate input is 0 by the inverter 34. Turn off.
In addition, the NAND 30 input is converted _{to 1} by the inverter 26.
= 0 and (0, 1), so the output is 1, the PT gate input of the transmission switch 37 is 1, and the NT gate input is the inverter 36.
Since it is 0, it is turned off. Furthermore, Nando 31
The input is ₁ = 0, ₂ by inverters 26 and 27.
= 0 and (0, 0), so its output is 1, the PT gate input of the transmission switch 39 is 1, and the NT gate input is the inverter 38.
Since it is 0, it is turned off. In the end, the transmission switch turns on and only Vc ₁ from 33 is transferred. Similarly in case (ii)
Only 35 is turned on and Vc ₂ is transferred. Similarly, in case (iii), only 37 is turned on and Vc ₃ is transferred. Similarly, in case (iv), only 39 is turned on and Vc ₄ is transferred.

In this specific example, in order to perform such adjustment inside the IC, the 5th control circuit shown in FIG.
It is constructed using non-volatile memory elements as shown in Figure a. 76, 77, 81, 82 are FAMOS.
Electrons are not injected into the gate of this FAMOS (of course, if the circuit configuration of the FAMOS has the opposite polarity, they are holes), and furthermore, when _φ3 is low, Vc
is ₃ , so NT79 and 84 are turned on and [a ₁ , a ₂ ] = [0, 0], and the output is output from inverter 8.
Since it is inverted by 0,85, (b ₁ , b ₂ )=
(1, 1), and Vd=Vc ₁ . When _φ3 is high, PT78, 83 are turned on and [a ₁ , a ₂ ] = [1,
1] However, at this time, no current flows through the current paths of the circuits 1, 2, and 3 in FIG. 2, and the circuits do not operate as intended.
In other words, the output of 25 when _φ3 is low is valid. Now, the 25 adjustment circuits corresponding to (i) to (iv) above will be described. Corresponding to (i) is [a ₁ , a ₂ ] =
[0, 0] and this is the dual gate
The gate electrodes of FAMOS 76, 77, 81, and 82 are not implanted.

Corresponding to (ii) is [a ₁ , a ₂ ] = [0, 1]
This is a state in which electrons are injected into the gate electrodes of FAMOS 81 and 82. Corresponding to (iii) is [a ₁ ,
a ₂ ]=[1, 0], and electrons are injected into the gate electrodes of the FAMOSs 76 and 77. Corresponding to (iv) is [a ₁ , a ₂ ] = [1, 1] and FAMOS76,
Electrons are injected into the gate electrodes 77, 81, and 82.

The configuration of this FAMOS is illustrated in Figure 5-b.
55 is an N ^- silicon substrate, 57 and 58 are PT
The P-type layers 87 and 88 which become the source and drain of
This is a P-type layer that becomes the source and drain of FAMOS. 62 is an N-type layer for isolation and contact with the substrate; 89 is a clean insulating film for the gate; 64 is a field insulating film;
Reference numeral 5 denotes a metal layer, such as aluminum, used for the gate electrode, source/drain, substrate electrode, or wiring. 90 is a floating gate electrode of FAMOS, which is made of, for example, P- or N-doped or non-doped polycrystalline silicon. When injecting electrons into the gate electrode of FAMOS, between 55, 62 and 88, that is, the writing FAMOS
This is done by causing an avalanche in the depletion layer between the drain and the substrate (dotted line region in the figure), and injecting the electrons generated at this time into the gate electrode using an accelerating electric field. (Indicated by an arrow in the figure.) Therefore, there is a gap between the drain and substrate of the FAMOS for writing.
In order to prevent the avalanche voltage at the PN junction from being disturbed by the reverse breakdown voltage of the PN junction between its drain and isolation, the gap 92 between the write FAMOS drain 88 and the isolation 86 is similar to that of the normal MOS drain 5.
8. Isolation 86 must be greater than spacing 91. Of course, it is possible to match the length of 91 to 92. 90 can also use polycrystalline silicon for multilayer wiring as a floating gate electrode, and conversely, polycrystalline silicon used for floating gates can also be used for multilayer wiring. Also, in Fig. 5-a, when 77 or 82 is in the injection state and _φ3 is low and 79 and 84 are on, a ₁ and a ₂
The on-state impedances of 79 and 84 are designed to be high so that the potential is high. Of course, if 79 and 82 are in a sufficiently implanted state, the impedance will be sufficiently low even with the same size as 79 and 84 (same channel length, same channel width, same gate insulating film thickness), so in terms of size, 79 and 84 will be 77, The same level as 82 is fine. Figure 5-c encompasses these intentions,
This is an example of patterns 76, 77, and 78. The pattern in the figure is the same as in Figure 5-b. That is, the shaded area is a layer that serves as an N-type isolation layer and makes contact with the substrate, the area itself is a P-type layer or substrate, the double shaded area is a gate electrode of FAMOS, such as polycrystalline silicon, and the dotted area is a gate, A metal layer, for example aluminum, that serves as source, drain, and substrate electrodes. 〓 represents a contact between a P-type or N-type layer and a metal.
In the write FAMOS 76, the gap 92 between the drain and the isolation is set larger than the gap 91 between the drain and the isolation of the read FAMOS or the normal MOS 78.

If FAMOS is used as the adjustment circuit in this way, this invention has the process advantage of directly adjusting from the tester during testing of the integrated circuit in the wafer state, and eliminating the need for any adjustment of this voltage detection circuit later. There is a fifth characteristic.

Next, the comparison circuit 3 will be explained. 3 is _φ3
works as expected when set to low. 3 consists of a comparator 40. The comparator 40 is composed of a differential amplifier (operational amplifier) as shown in FIG. 3-a, and compares the inverting input V _I and the non-inverting input V _NI . When V _I > V _NI , V ₀ = low (0), and when V _I < V _NI , V ₀ = high (1). The resolution is determined by the open-loop gain of the amplifier in Figure 3-a, which typically ranges from 70 to 8.
Since it is 0b _B , approximately 1/3000th of the power supply voltage to 1B
It is possible to compare minute voltages of 1/10,000th. As for the comparator, there is no need to worry about oscillation, and the capacitances C ₁ and C ₂ only need to be small. In other words, the gate structure 5 in FIG. 3-b
2, the gate structure 59 in FIG. 4-a may be used. Further, the ratio of the conductance coefficients of 45 and 50 may be approximately the same. The oven loop gain of the differential amplifier (operational amplifier) shown in FIG. 3-a can be increased by increasing the channel length of each transistor constituting the amplification stage, increasing the substrate concentration, and decreasing the gate film thickness. One way to increase the gain in integrated circuit design is to increase the channel length of each transistor that makes up the amplifier. This is characterized in that the channel length of the transistor in the amplifier is longer than the channel length of a transistor other than the amplifier in a voltage detection circuit or a transistor in an integrated circuit other than the voltage detection circuit in an electronic device.

By the way, in this specific example, the comparison voltage is V _I =
Vd, V _NI =Vst. When the adjustment circuit 4 is in the state (i), Vd=r ₁ /R+rVdΓ, and Vst=R ₂ /R
₁ +R ₂ Vst, so VdΓ ^* R ₂ /R ₁ +R ₂ R+r/r ₁ Vst
When VdΓ>VdΓ ^* , the output of the comparator becomes low (ground potential), and when VdΓ<VdΓ ^* , the comparator output becomes high V ( _VDD ). Conversely _, the ratio of R ₂ /R ¹ and ri/R+r (i=
1, 2...) Furthermore, Vst (=V _TP - V _GTP) is certified.

A sixth feature of the present invention is that the comparison between the reference voltage constituting the voltage detection circuit and the converted voltage to be detected is performed by a comparator, that is, a differential amplifier.

Finally, the hold circuit 6 holds the data as shown in FIG.
Hold flip-flop (shift register) 4
1, and when _φ3 is low, the output of comparator 40
It becomes a memory circuit that writes Vcomp and holds its output when _φ3 is high. Vcomp is further amplified by an inverter in the hold circuit, for example (96, 97) or (102, 103), and the output Vh
becomes.

In the example of FIG. 2b, each voltage detection circuit 1, 2,
The pulse φ ₃ that operates 3 and ₄ is the same as the clock pulse of the hold circuit, but in reality, if the output signal of this hold circuit is always required completely, the high of the φ ₃ pulse The problem is the dynamic characteristics of each circuit when changing from low to low, that is, the transient characteristics. At this time, for example, by subtracting the time τd required for each voltage detection circuit 1, 2, 3, and 4 to become statically uniform from φ ₃ , we obtain φ ₅ in Fig. 7-c.
The hold circuit is driven by a pulse such as . _φ5 is
Half clock time τb (>τd) from ₃ to _φ4
The pulse corresponding to the shift register (flip-flop) 104 is removed as shown in Figure 7-b.
and is made with Noah 105.

In addition to the above, if the transient characteristics of the voltage detection circuit and hold circuit when the _φ3 pulse changes from low to high become a problem in the same sense, then a certain period of time τa ( ₄ - clock minutes) from _φ5 The hold circuit is driven by _φ6 with the pulse corresponding to . _φ6 is made up of a shift register (flip-flop) 106, a NAND 107, and an inverter 108 as shown in FIG. 7-b. The circuit shown in FIG. 7-b is included in the pulse generating circuit 5.

By the way, in the specific example of the present invention shown in FIG. 2, the adjustment is performed using 2, but it is also possible to perform the adjustment using 1, for example, 20, 21, 22, 23,
Connect resistors 17 and 18 instead of 24 and fix it to VdR ₂ /R ₁ +R ₂ VdΓ, and conversely change 16 output to 17
, 18, resistors 20, 21, 22, 23, and 24 are connected to the adjustment circuit 4 to adjust Vst. Also, depending on the precision of the set voltage, it is of course possible to make no adjustment, which means deleting 4 in Figure 2, fixing the resistance value connected to the output of 19, and setting it as the output Vd. . For example, r ₂ = r ₃ = r ₄
= 0, R/r ₁ is set appropriately, and the C ₁ output is directly connected to the inverting input of the comparator 40 as Vd.

In any case, as described above, the IC of the voltage detection circuit of the present invention is characterized in that it can coexist with other circuits constituting electronic equipment and can be easily integrated.

By the way, the IC of the voltage detection circuit in the present invention
Furthermore, the following detection setting voltage automatic adjustment method is also possible. The circuit shown in FIG.
~119 and injection control transistor 12 for controlling ON-OFF of FAMOS
0 to 124, and a shift register 125 configured to sequentially turn on the FAMOS through the control transistors by clock pulse input cl.
It consists of At this time, when the FAMOS is sequentially turned on, the voltage of the Vd terminal, which is the comparison input of the comparator, becomes variable as the resistors r ₂ to rn are sequentially short-circuited. Also FAMOS110
and 115, 111, and 116, which is a dual gate structure as described above. Furthermore, the Vp terminal
This is a write input for injecting charge into the FAMOS, and a voltage of about -30 to -50V is applied in an impulse manner. FIG. 9 shows an example of an actual system for automatic adjustment using the automatic adjustment circuit 109 in FIG. This example detects when the power supply voltage reaches a certain desired voltage, and therefore Vdo= _VDD . First, the power supply voltage V
Set _DD to be lower than the detection setting voltage. At this time, the output Vcomp of the comparator 3 is set to H level.
The controller 127 confirms this, then releases the reset and starts the counter 1 from the clock Clo input.
When Cl is input to the regulator 109 via 26 and the shift register 125 is moved, the register output Q ₁
~Qn sequentially goes to L level, and at this time, the injection pulse is applied to Vp, so FAMOS110~114
are turned on sequentially. Then, the potential of the detected voltage Vd gradually decreases in synchronization with the clock pulse, and when it crosses the reference potential Vst, the comparator output Vcomp becomes L.
Change with level. At this time, controller 127 immediately stops the clock and injection pulse to complete the adjustment. Therefore, when this circuit is normally used, the comparator 3 will immediately detect when the power supply voltage reaches the set voltage.

Especially as a regulating element in the circuit described above,
It includes not only FAMOS but also tunnel injection type devices such as MNOS.

Further, the adjusting means in the present invention includes the following. Figure 10 shows an adjustment circuit that uses a fuse 130 (made of metal or millicon, etc.), which allows a large amount of current to flow between the input 134 and _VDD , and determines the detected voltage by thermally disconnecting it or not. adjust. When the current consumption is extremely limited, a differential pulse such as ₃ may be used and sampling detection may be performed using the NT133. As another means, the portion corresponding to the fuse 130 may be cut using a laser or the like. That is, FAMOS, MNOS, fuses, etc. are nonvolatile, and the adjustment means of the present invention can be applied to all nonvolatile memory elements. Furthermore, although all of the above-mentioned methods enable adjustment before the IC is mounted, that is, in the chip or wafer state, it is also possible to make adjustments by terminal selection during or after the mounting of bonding mechanical contacts, etc. Become.

Figure 11 shows a specific example of applying the voltage detection circuit described above to an electronic watch, which detects a drop in battery voltage, notifies the wearer that the battery has reached the end of its life with an appropriate display, and prompts the user to replace the battery. This is a circuit to encourage this. Reference voltage generation circuits 10 to 15, comparator 3, data hold flip-flop 4
1. The sampling pulse _φ3 generating circuits 7 and 8 and the adjustment circuit 4 using external terminals W ₁ and W ₂ have almost the same configuration as in FIG. 2. In this case, the reference voltage Vsto is directly input to the comparator 3, and the detected voltage is the power supply voltage.

154 is an inverter for crystal oscillation, and 156
is a 16-stage 1/2 frequency divider circuit. Adjustment in this circuit is performed as follows. First, set Reset to H level. At this time, the low frequency stage of the frequency divider circuit is reset, and at the same time the flip-flop (shift registers 7, 140, 143 have a 1/2 bit configuration, so all W = (i = 2.4), and therefore the hand drive The motor outputs O ₁ and O ₂ become H level.At this time, when the O ₂ terminal is forcibly set to L level externally, the gates 148 and 158 are opened, and the sampling pulses φ ₃ and ₃ of the voltage detection circuit are All gates are open and the detection state is maintained steadily. Also, the data hold flip-flop 41 is in the write state by ₃ and the detection data is sent through the gate 148.
Output to _O1 . Thereafter, the power supply voltage V _DD is changed, and an appropriate detection setting voltage is determined from the voltage at which the output of O ₁ changes and is written to the FAMOS from the W ₁ and W ₂ terminals. After that, when the power supply is normalized and Reset is opened, the reset is canceled and driving pulses are outputted to O ₁ and O ₂ alternately every second. Also, since the data input W of the flip-flop (shift register) 7 uses the master signal _M16 of the 16th stage, a sampling pulse _φ3 with a time difference of 0.5 seconds from the motor drive signal is created, which is also 2 seconds. Voltage detection is performed once every minute and the data is stored in the flip-flop 41. If the battery voltage decreases and reaches a predetermined voltage and the output of the comparator is inverted, the gate 141 operates and the signal at the input W of the flip-flop 143 becomes a signal whose duty is largely shifted by the clock _S12 . Therefore, the outputs O ₁ and O ₂ are not alternating signals every second, but are output in a time-biased manner, so that the second hand of the clock, which used to move one second at a time, appears to move once every two seconds. It advances step by step and alerts the person carrying it.

Furthermore, the voltage detection circuit of the present invention is also capable of detecting two or more levels. FIG. 12-a shows a circuit that performs two-level voltage detection. φ ₇ and φ ₈ are the 12th-
As shown in figure b, the signals are out of phase, and the voltage detection circuit operates in the same way at each timing.
However, when _φ8 input is used, transistor 165 is OFF.
Therefore, Vsto is used as the reference potential, and when φ ₇ , 165 is ON and (R ₂ / R ₁ + R ₂ ) Vsto
becomes the reference potential, resulting in two-level detection. The outputs of the comparator 3 detected at each timing are stored in flip-flops 163 and 164, respectively. Further, a circuit for adjusting the detected potential Vd as described above is added if necessary.

The circuit shown in FIG. 12-a is used in a rechargeable watch, such as one equipped with a solar battery.
The timing of _φ7 detects a drop in the secondary battery voltage, and the output of _Q5 displays a notice to prompt the user to charge the battery. Conversely, the timing of _φ8 detects a rise in the secondary battery voltage due to overcharging, and stops charging by the output of _Q6 .

The voltage detection circuit according to the present invention is a monolithic IC.
In particular, it is possible to integrate other functions into the same chip, such as a watch IC, and the detection voltage adjustment circuit can be trimmed within the IC to compensate for variations in detection voltage between ICs. It also makes it possible to

The voltage detection circuit according to the present invention is revolutionary in that it does not require an external trimmer such as a volume or resistor because it has an adjustment circuit, and is also resistant to temperature fluctuations and power supply voltage fluctuations. , is extremely stable. Furthermore, when used in a watch IC, the omission of external adjustment elements further promotes miniaturization and cost reduction, which is of great significance.

Furthermore, since it includes a sampling circuit, current consumption can be significantly reduced. Furthermore, since the holding circuit is provided even when sampling is not being performed, it is possible to always take out the output voltage of the comparator circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a voltage detection circuit according to the present invention. FIG. 2 shows a specific example of the voltage detection circuit of the present invention. FIG. 3-a is a concrete diagram in which an operational amplifier or a differential amplifier in the voltage detection circuit of the present invention is configured with C-MOS. Figure 3-b is a cross-sectional view of a MOS integrated circuit.
Figure 4-a is a sectional view of a MOS integrated circuit. Figure 4-b is a configuration diagram of a resistor in an integrated circuit. Figure 4-c is a MOS configuration diagram of the resistor. Figure 4-d is a diagram showing the configuration of a resistor using diodes. FIG. 4-e is another specific diagram of the reference voltage circuit in the voltage detection circuit of the present invention. FIG. 5-a is a specific diagram of the control circuit of the adjustment circuit in the voltage detection circuit of the present invention. Figure 5-b is
Cross-sectional diagram of MOS and FAMOS integrated circuits. FIG. 5-c is a plan view of the integrated circuit of the control circuit shown in FIG. 5-a. FIG. 6 is a specific diagram of a shift register or flip-flop in the voltage detection circuit of the present invention. 7th-
Figure a is a timing diagram of each pulse of sampling and holding of the pulse generation circuit in the voltage detection circuit of the present invention. FIG. 7-b shows another specific example of the pulse generation circuit in the voltage detection circuit of the present invention. FIG. 7-c is a timing diagram of each pulse of sampling and holding of the pulse generating circuit shown in FIG. 7-b in the voltage detection circuit of the present invention. FIG. 8 is a specific example of an automatic adjustment circuit for the detection setting voltage of the voltage detection circuit of the present invention. FIG. 9 is a specific example of an automatic adjustment system for a voltage detection circuit according to the present invention. FIG. 10 shows another specific example of the adjustment circuit in the voltage detection circuit of the present invention. FIG. 11 shows a specific example in which the voltage detection circuit of the present invention is applied to an electronic watch. 12th-
Figure a is a specific example of the voltage detection circuit of the present invention that detects two levels of voltage. FIG. 12-b is a timing chart of sampling and holding pulses of the voltage detection circuit of the present invention that performs two-level voltage detection. Fig. 10 131...Resistor, 132...Inverter, Fig. 11 Pf...Feedback resistance of oscillation inverter, R
_D ...Oscillation inverter output resistance, C _D , C _G ...Oscillation circuit capacitor, Rr...Reset terminal pull-down resistor, 144, 146, 151, 153, 15
7,159,162...Inverter, 142,14
5,155...NAND circuit, 149,161...AND circuit, 150,160...NOR circuit, 147,1
52... Motor drive inverter, S ₉ ... 9th stage output out of 16 stages of 1/2 frequency divider circuit, R... Reset input, 1st
2-a Figure 166... Inverter, 167... NAND circuit.

Claims (1)

[Claims] 1. (a) A reference voltage generation circuit that generates a reference voltage independent of the detected voltage to be detected; (b) A detected voltage conversion circuit that generates a converted voltage that depends on the detected voltage. (c) a comparison circuit that compares the reference voltage and the converted voltage and outputs an output voltage; (d) an adjustment that adjusts the reference voltage generation circuit or the detected voltage conversion circuit to vary the set voltage. (e) a hold circuit that inputs and holds the output voltage; (f) supplies pulses to the reference voltage generation circuit, the detected voltage conversion circuit, the comparison circuit, the adjustment circuit, and the hold circuit; and a pulse generation circuit that generates pulses for sampling drive, (g) the adjustment circuit comprising a gate that selects a dividing point of a plurality of cascade-connected resistors. circuit.