JP2973880B2 - Ultraviolet erasing nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS semiconductor memory device, and more particularly to an ultraviolet erasing nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Hitherto, various structures of a floating gate type nonvolatile semiconductor memory device have been proposed and put to practical use. Above all, a nonvolatile semiconductor memory device capable of erasing ultraviolet rays (hereinafter referred to as “UV-EPROM”) has been most widely used. The structure and operation of this UV-EPROM will be described below with reference to the drawings.

FIG. 5 is a plan view of a memory cell of a conventional UV-EPROM. 6A is a diagram schematically showing a cross section taken along the line AA 'in FIG. 5, and FIG. 6B is a diagram schematically showing a cross section taken along the line BB' in FIG.

Referring to FIGS. 5 and 6, a drain region 9 and a source region 10 are formed on the surface of a P-type semiconductor substrate 1, and a floating gate 3 is formed on a channel region therebetween via a first gate insulating film 2. And a second gate insulating film 4
A control film 5 (also referred to as a “control gate”) is provided through the gate. The contact 11 is normally connected to the drain 9 of the memory cell.
, A metal wiring 7 (also referred to as a “digit line”) is connected, and the second-layer polysilicon forming the control gate 5 forms a word line. The metal wires 7 are arranged in parallel on the interlayer insulating film 6, and a passivation film 8 is formed so as to cover them.

Next, a UV-EP having this two-layer poly structure is used.
The writing and erasing operations of the memory cells of the ROM will be briefly described.

In writing data, first, a high voltage (V _pp = 14 V) is applied to the control gate electrode 5 (word line) of the memory cell.
-17V) to invert the channel to N-type. Next, a high voltage (7 V to 8 V) is applied to the drain 9 (digit line).
Is applied, a potential difference occurs in the N-type inversion layer, and the drain 9
A pinch-off state occurs in the vicinity.

Electrons from the source 10 are accelerated by this potential difference, become hot electrons near the drain 9, and are injected into the floating gate electrode 3 by an electric field generated by a high voltage applied to the control gate electrode 5.

As a result, the floating gate electrode 3 is negatively charged, and the threshold voltage (V _T ) of the memory cell increases.

Therefore, the channel under the floating gate electrode 3 is not turned on by the gate voltage at the time of reading. Increasing the threshold voltage of a memory cell by this operation is referred to as “data writing”.

On the other hand, erasing is performed by irradiating the floating gate electrode 3 with the injected electrons with ultraviolet rays, whereby the electrons in the floating gate are excited to exceed the energy barrier of the gate insulating film around the floating gate electrode 3. To the control gate electrode 5, the source 10 or the drain 9. This is called "erasing data".

[0011] This operation lowers the threshold value of the memory cell, and the gate voltage at the time of reading makes the channel O
The state is the same as the initial state of N.

FIG. 4 shows a change in the threshold value of the memory cell due to the writing and erasing. In FIG. 4, the horizontal axis represents the gate voltage of the memory cell (the voltage V _CG of the control gate electrode 5), and the vertical axis represents the drain current of the memory cell. In FIG. 4, the sense level on the vertical axis (drain current Id) indicates the threshold of the current level detected by a sense amplifier (not shown) at the time of reading, and is lower than the sense level from the sense amplifier. "1" is output.

By repeatedly writing and erasing data, the threshold value changes between two states (ie, a state after writing and after erasing). If the erasing is insufficient, the threshold value of the memory cell is changed to the initial state. There is a possibility that erroneous data may be output when reading data because the data does not return to the threshold value. That is, referring to FIG. 4, when a read gate voltage is applied at the time of reading, and the threshold voltage in the initial state after erasing exceeds, for example, the gate voltage (indicated by a dashed line) in the read mode shown in FIG. Even if a voltage is applied, the channel of the memory cell does not turn on, and erroneous data is read.

Therefore, it is necessary to return the threshold voltage of the memory cell to the same threshold voltage as the initial state by irradiating ultraviolet rays.

However, as the size of memory cells is reduced,
The UV-EPROM is shown in FIGS. 5 and 6 (A) and 6 (B).
As shown in FIG. 1, a structure is adopted in which a metal wiring 7 is arranged on the floating gate electrode 3 to be irradiated with ultraviolet rays in order to make a contact 11 with the drain region 9.

[0016]

As described above, UV-E
In the PROM, a large area on the floating gate electrode is covered by a metal wiring, which hinders irradiation of ultraviolet rays.

Furthermore, recently, as the memory cell becomes finer, the interval between metal wirings becomes smaller and the floating gate electrode becomes smaller, so that the amount of transmitted ultraviolet rays reaching the floating gate electrode decreases, and the erasing efficiency deteriorates. The problem of doing so is becoming apparent.

Conventionally, various methods have been proposed to deal with such a problem. For example, Japanese Patent Laid-Open No. 1-1294
No. 67 proposes a configuration for removing an interlayer insulating film on a floating gate electrode for the purpose of improving erasing characteristics as shown in FIG. That is, referring to FIG. 7, floating gate 3 made of normal polysilicon is provided on gate oxide film 2, and PSG 1 is formed as interlayer insulating film 6.
6 and a CVD nitride film 17 are provided, and the PSG 16 and the CVD nitride film 17 are selectively etched on the floating gate 3 as an erasing window.

However, the method of avoiding the formation of the metal wiring 7 from above the floating gate electrode 3 leads to an increase in the size of the memory cell, which is not practical, and the UV-EPROM described in the above publication is put to practical use after all. Did not reach.

Therefore, the present invention solves the above problems,
It is an object of the present invention to provide a nonvolatile semiconductor memory device that avoids deterioration of the erasing efficiency due to miniaturization of an ultraviolet erasing nonvolatile semiconductor memory element.

[0021]

According to another aspect of the present invention, there is provided a semiconductor device comprising: a source region and a drain region provided on a surface of a semiconductor substrate of a first conductivity type and having a conductivity type opposite to the first conductivity type; A floating gate electrode provided on a channel region between the source region and the drain region via a first gate insulating film, and a control gate electrode formed on the floating gate electrode via a second gate insulating film It has a two-layer structure composed of, formed by depositing on the structure of the interlayer insulating film
Cover on digit metal wiring provided in parallel on top
In a nonvolatile semiconductor memory device in which floating gate type nonvolatile semiconductor memory elements having films formed thereon are arranged in an array, at least a part of an interlayer insulating film in a region located between the digit metal wirings is removed. A nonvolatile semiconductor memory device characterized by comprising:

According to the present invention, by removing at least a part of the interlayer film located between the parallel metal wirings (digit lines), the transmittance of ultraviolet rays to the floating gate electrode is improved, and the erasing characteristics are improved. In addition, it is possible to satisfactorily avoid the deterioration of the erasing efficiency due to the miniaturization of the element.

According to the present invention, since the interlayer insulating film can be continuously etched after the metal wiring is dry-etched, the interlayer insulating film can be removed only by adding a dry etching step. Is possible,
There is no need to create or modify new masks,
It can be easily applied to mass production.

[0024]

Embodiments of the present invention will be described with reference to the drawings.

[0025]

Embodiment 1 FIG. 1 is a diagram schematically showing a cross section of an ultraviolet erasing nonvolatile semiconductor memory device according to a first embodiment of the present invention. A plan view of the ultraviolet erasing nonvolatile semiconductor memory device according to this embodiment as viewed from above is the same as FIG. 5 referred to in the description of the conventional example. FIG. 1 is a sectional view of FIG.
It is a figure which shows the cross section of the A 'line. In the following description about the case of using a P-type semiconductor substrate 1 as the substrate.

On the surface of the P-type semiconductor substrate 1, an N + type drain region (9 in FIG. 6 ) and an N + type source region (10 in FIG. 6 ) are formed, and on a channel region between the drain region 9 and the source region 10. A floating gate electrode 3 is provided via a first gate insulating film 2 formed on the substrate, and a control gate electrode 5 is provided on the floating gate electrode 3 via a second gate insulating film 4.

In this embodiment, an interlayer insulating film 6 such as BPSG is provided on the above structure, and at least a part of the interlayer insulating film 6 located between parallel metal wirings 7 (digit lines). Has been removed.

In this embodiment, due to its structure, after the metal wiring 7 is dry-etched, it is continuously (ie, the metal wiring 7).
Since the etching of the interlayer insulating film 6 can be performed (using the resist mask used for the etching of
Just by adding a dry etching step, the interlayer insulating film 6
Can be realized, and it is not necessary to newly create or modify a mask, so that the present invention can be easily applied to mass-produced products.

[0029]

Second Embodiment Next, an ultraviolet erasing nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG. A plan view of the ultraviolet erasing nonvolatile semiconductor memory device according to this embodiment as viewed from above is the same as FIG. 5 referred to in the description of the conventional example. FIG.
It is a figure which shows the cross section of the -A 'line. In the following, P
The case where the mold semiconductor substrate 1 is used will be described.

Referring to FIG. 2, this embodiment is different from the first embodiment in that the interlayer insulating film has a multilayer structure with first to third interlayer insulating films 6, 12, and 13. That is.

In general, a multilayer structure is used as an insulating film of a multilayer wiring, or in a case of a package having a low moisture resistance such as a mold resin for improving the moisture resistance. In the case of a one-time (One Time) PROM of a nonvolatile semiconductor memory device, an interlayer insulating film having a multilayer structure is often adopted for the latter reason.

This is because the oxide-based interlayer insulating film has a problem in moisture resistance, and the nitride-based interlayer insulating film alone extremely reduces the amount of transmitted ultraviolet light. Is what it is.

As described above, when the interlayer insulating film has a multilayer structure, the following operation and effect are newly obtained.

Referring to FIG. 2, for example, first interlayer insulating film 6
And a third interlayer insulating film 13 using a phosphorus glass-based BPSG film, and a second interlayer insulating film 12 between which a nitride-based Si ₃ N ₄
When the BPSG film is used, since the BPSG film and the Si ₃ N ₄ film have different etching rates, the second interlayer insulating film 12 can be used as an etching stopper when the third interlayer insulating film 13 is etched.

In this way, extreme deterioration of the shape due to extreme over-etching can be prevented, and at the same time, the silicon substrate 1
Only the third interlayer insulating film 13 can be selectively etched without damaging the control gate electrode 5.

According to the above embodiment, the parallel metal wiring 7
By removing at least a part of the interlayer film located therebetween, the transmittance of ultraviolet rays to the floating gate electrode 3 is improved. FIG. 3 shows the erasing characteristics of the ultraviolet erasing nonvolatile semiconductor device (product of the present invention) according to the embodiment of the present invention by solid lines.
Note that the dotted line in FIG. 3 shows the erase characteristics of the conventional structure (conventional product) manufactured according to the same design rules as the present embodiment.

As is apparent from FIG. 3, according to the embodiment of the present invention, the erasing efficiency is greatly improved (the fall of the threshold voltage due to ultraviolet irradiation is earlier than in the conventional example).

Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the above-described embodiments, but includes various forms according to the principle of the present invention.

[0039]

As described above, according to the present invention, by removing at least a part of the interlayer film located between the parallel metal wirings, the transmittance of ultraviolet rays to the floating gate electrode is improved, and erasing is performed. The characteristics have been improved. Therefore, according to the present invention, it is possible to satisfactorily avoid deterioration of the erasing efficiency due to miniaturization of the element.

According to the present invention, since the interlayer insulating film can be continuously etched after the metal wiring is dry-etched, the interlayer insulating film can be removed only by adding a dry etching step. Is possible,
There is no need to create or modify new masks,
It can be easily applied to mass production.

Further, when the interlayer insulating film has a multilayer structure, it is possible to prevent extreme deterioration of the shape due to extreme over-etching, and at the same time, without damaging the silicon substrate and the control gate electrode, for example, the uppermost interlayer insulating film. This has the effect that only one can be selectively etched.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross section of an ultraviolet ray erasing nonvolatile semiconductor memory element according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a cross section of an ultraviolet-erasable nonvolatile semiconductor memory element according to a second embodiment of the present invention.

FIG. 3 is a diagram showing erasing characteristics of an ultraviolet erasing nonvolatile semiconductor memory device according to an embodiment of the present invention and erasing characteristics of a conventional example.

FIG. 4 is a diagram showing a threshold voltage in a writing and erasing state of the ultraviolet erasing nonvolatile semiconductor memory element.

FIG. 5 is a plan view of a conventional ultraviolet erasing nonvolatile semiconductor memory device.

FIG. 6 is a diagram showing a cross section of the structure of a conventional ultraviolet erasing nonvolatile semiconductor memory element. FIG. 6A is a cross-sectional view taken along line AA ′ of FIG. (B) It is sectional drawing along the BB 'line of FIG.

FIG. 7 is a view showing a cross section of an ultraviolet ray erasing nonvolatile semiconductor memory element described in JP-A-1-129467.

[Explanation of symbols]

 Reference Signs List 1 P-type semiconductor substrate 2 First gate insulating film 3 Floating gate electrode 4 Second gate insulating film 5 Control gate electrode 6 Interlayer insulating film or first interlayer insulating film 7 Metal wiring 8 Passivation film 9 Drain region 10 Source region 11 Contact 12 Second interlayer insulating film 13 Third interlayer insulating film 14 Field oxide film 15 PSG 16 CVD nitride film

Claims (2)

(57) [Claims] A first conductive type opposite to the first conductive type and a source region and a drain region provided on a surface of the semiconductor substrate of the first conductive type; and a channel region between the source and drain regions. A two-layer structure including a floating gate electrode provided with a gate insulating film interposed therebetween and a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween; In a nonvolatile semiconductor memory device, a floating gate type nonvolatile semiconductor memory element in which a cover film is formed on digit metal wiring provided in parallel with an upper portion of an interlayer insulating film formed is arranged in an array, An ultraviolet-erasable nonvolatile semiconductor memory device, wherein at least a part of an interlayer insulating film in a region located between the digit metal wirings is removed. 2. The method according to claim 1, wherein the interlayer insulating film has a multilayer structure in which a plurality of interlayer films are deposited, and a predetermined number of interlayer films among the interlayer insulating films between the parallel digit metal wirings are removed. The nonvolatile semiconductor memory device for erasing ultraviolet rays according to claim 1, wherein