JP2971875B2 - Arithmetic unit and data processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit and a data processing unit mounted on a digital signal processor (hereinafter referred to as DSP) or the like.

[0002]

2. Description of the Related Art A conventional data processing apparatus for comparing data will be described below. This conventional data processing apparatus is mainly used as a dedicated circuit when performing variable-length coding after performing discrete cosine transform on image information and the like. For example, in the conventional data processing device shown in FIG. 16, reference numeral 1x denotes a memory (addresses 0 to 63, data of 8 bits), reference numeral 2x denotes a read control circuit, reference numeral 3x denotes a zero run counter, reference numeral 4x denotes a zero decoder, and reference numeral 5x is memory data, 6x is a memory read control signal, 7x
Is an enable signal, 8x is a zero decode signal, and 9x is a zero run count signal. The code 10x is a variable length coding device that performs variable length coding.

FIG. 17 is a waveform diagram of the data processing apparatus configured as described above (reference numerals correspond to FIG. 16).
The operation will be described with reference to FIG. Note that FIG. 17 illustrates a typical memory read address signal as the memory read control signal 6x.

A waveform 1w shown in FIG. 17 is used as an operation clock (CLK) of the data processing device shown in FIG. The read control circuit 2x of FIG. 16 outputs the memory read control signal 6x when the enable signal 7x is at a high level (hereinafter, H level).
Is read (in this example, addresses are generated in the order of 0, 1, 2 to 63).

[0005] The zero decoder 4x decodes the memory data 5x, and sets the zero decode signal 8x to the H level when the memory data 5x indicates the value 0. At this time, the zero-run counter 3x counts up and counts the number of continuous values 0. When the zero decode signal 8x is at a low level (hereinafter, L level), the zero run counter 3x indicates a value of 0.

The zero run count signal 9x and the zero decode signal 8x thus generated are output together with the memory data 5x, and the zero run count signal 9x and the memory data 5x when the zero decode signal 8x is at the L level are output. The subsequent data processing, that is, the variable length coding processing, is performed by the variable length coding circuit 10x. What is variable length coding?
The data compression process is performed with the number of times that zero data continues and the non-zero data that follows the zero data as one set. Strictly speaking, quantization processing is performed before variable-length coding. The zero run count signal 9x indicates the number of times zero data has continued, and the memory data 5x indicates non-zero data.

[0007]

This data processing device is designed to sequentially detect and output the number of times zero data continues and non-zero data following the zero data, so that a zero run counter 3x, a zero decoder 4x, etc. Since the dedicated circuit configuration is used, the versatility is low, for example, detection of a continuous number of arbitrary data other than zero cannot be performed, and further, for example, the number of times the zero data continues and the next data after the zero data If it is necessary to perform addition processing and comparison processing in addition to the processing of sequentially detecting and outputting non-zero data that follows, it is necessary to add an additional circuit to perform addition processing and comparison processing. Become.

When the data processing device is provided as a dedicated circuit in a DSP or the like, when the memory data continues to have a value of 0, the data processing using the zero run count signal 9x and the memory data 5x is continuously performed. It is impossible to do it. The reason for this is that it is impossible to perform the output of the zero run counter 3x and the output of the non-zero data every cycle because the data compression process is performed using both the number of continuous zero data and the non-zero data. It is.

Further, this data processing device is a data process for fixed data (here, the value of the data is 0), so that it is poor in versatility. Further, all data after a certain memory range becomes zero. There is a problem that the processing time increases because the search is performed on the entire memory range even for the data that has a possibility.

An object of the present invention is to provide a versatility capable of sequentially detecting and outputting the number of times zero data continues and non-zero data following the zero data, and performing other processing. It is to provide a rich computing device.

Another object of the present invention is to execute a process for sequentially detecting and outputting the number of times zero data continues and non-zero data following the zero data, and the same process for non-zero data. And to provide a versatile data processing device.

Another object of the present invention is to provide a data processing device capable of continuously executing data processing.

Still another object of the present invention is to provide a data processing device capable of shortening the processing time required for data processing.

Still another object of the present invention is to provide a data processing apparatus capable of increasing the degree of freedom of a data processing program.

[0015]

According to a first aspect of the present invention, there is provided an arithmetic unit including a comparison circuit, a shifter, an addition circuit, a register, and a selection circuit. The comparison circuit inputs the first data to be compared and the second data to be compared with the first data, and executes the comparison between the first and second data to thereby execute the first and second data. When the data match, a value 1 is output and the match signal is activated. When the first and second data do not match, the second data is output and the match signal is deactivated. The shifter receives the output of the comparison circuit as an input, and switches whether or not to execute the shift of the output of the comparison circuit according to the state of the coincidence signal provided from the comparison circuit. The adder circuit uses the output of the shifter as one input. The register receives an output of the adder circuit as an input. The selection circuit has the value 0 as one input, the output of the register as the other input, and any one as the other input of the addition circuit according to the selection signal.

A value of 0 is selected by the selection circuit according to the selection signal.
By selecting one of the register outputs
When the first data and the second data do not match, the first
In addition, the number of the second data that matches the first data after the mismatch of the second data and the second data that does not match the current first data are output as a pair. .

According to this configuration, the comparison circuit for comparing the first and second data, and the output of the comparison circuit as an input,
A shifter that switches whether or not to execute the shift of the output of the comparison circuit in accordance with the state of the match signal given from the comparison circuit;
Since the addition circuit and the selection circuit for accumulating the output of the shifter are provided, it is possible to execute a process of sequentially detecting and outputting the number of times zero data continues and non-zero data following the zero data. In addition, the same processing can be performed for data other than zero, and the versatility is high.

Further, only the function of the comparison circuit is used by controlling the shifter, the addition circuit, and the selection circuit, or only the function of the shifter is used by controlling the comparison circuit, the addition circuit, and the selection circuit. By controlling the circuit, the shifter, and the selection circuit, it is possible to use only the function of the addition circuit, and the device becomes versatile.

An arithmetic unit according to a second aspect of the present invention includes a comparison circuit, a flag register, a first register, a shifter, a second register, a third register, and a selection circuit. The comparison circuit inputs the first data to be compared and the second data to be compared with the first data, and executes the comparison between the first and second data to thereby execute the first and second data. When the data match, a value 1 is output and the match signal is activated. When the first and second data do not match, the second data is output and the match signal is deactivated. The flag register receives a match signal as input. The first register receives an output of the comparison circuit as an input. The shifter receives the output of the first register as input, and switches whether or not to execute the shift of the output of the first register in accordance with the state of the coincidence signal provided from the flag register. The second register receives the output of the shifter as an input. The addition circuit uses the output of the second register as one input. The third register receives an output of the adding circuit as an input. The selection circuit receives the value 0 as one input and
And the other output is used as the other input of the adder circuit according to the selection signal.

Then, the value of the selection circuit is set to 0 in accordance with the selection signal.
And the output of the third register to select the first data after the previous first and second data did not match when the first data and the second data did not match. The number of matched second data and the present first data and the unmatched second data are output as a pair.

According to this configuration, the first and second registers and the flag register are provided between the comparison circuit, the shifter, and the addition circuit in addition to having the same operation as that of the arithmetic unit according to the first aspect. Even if the operation of the comparison circuit, the shifter, and the addition circuit is not high-speed, it is possible to execute a process of sequentially detecting and outputting the number of times the zero data continues and the non-zero data following the zero data. The same process can be performed for other data.

According to a third aspect of the present invention, there is provided a data processing device which outputs a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, and an end flag signal when executing an instruction, and a memory read control signal. , A first data register that receives a comparison data setting signal and sets data to be compared, a second data register that stores data from the first memory, and an instruction execution instruction. A search counter for inputting a signal to output the number of searches to the first memory to the control unit; a comparison signal and execution data to which an instruction execution signal, output data of the first data register and output data of the second data register are input; An execution unit that outputs a signal, a memory write control signal, an execution data signal of the execution unit, and an end flag signal. And a second memory that.

Then, when the comparison instruction is executed, the output data of the first data register and the second data register are input to the execution unit by the instruction execution signal to compare the data, and at the same time, the search number counter is counted up. Until the output of the number-of-times counter reaches a predetermined value, the end flag signal is deactivated, and when the output of the number-of-searches counter reaches the predetermined value, the control unit ends the comparison instruction and activates the end flag signal. By outputting the comparison signal of the execution unit to the control unit and controlling the writing to the second memory, both when the end flag signal is in the inactive state and when the end flag signal is in the active state, the data is transferred to the second memory. Writing an execution data signal and an end flag signal indicating data of the first memory that did not match the number of times the comparison data matched. That.

According to this configuration, a comparison instruction can be executed for an arbitrary value by setting data to be compared in the first data register, and a search number counter for counting the number of searches in the comparison range is provided. Since the comparison instruction can be ended and the end flag signal can be written in the second memory, the final data can be detected only by reading the written data in the second memory.

As described above, the number of times that the comparison data matches and the data that does not match and the end flag signal are written to the second memory, and then the data of the second memory is written at an arbitrary time (in the order of writing). 3) Since reading is possible every cycle, it is possible to continuously execute data processing such as variable length coding. Further, by setting an arbitrary value in the first data register, it is possible to deal with all kinds of data, and it is versatile.

Further, by writing the data which did not coincide with the comparison data and the end flag signal to the second memory, the number of coincidences of the comparison data which is the basis of the variable length coding is reduced by one. It is possible to execute a variable-length coding instruction at any time without being limited by the timing of taking in data that has not been performed.

Also, the execution unit having a function other than the detection of the number of values 0 can be used because it has a path for storing data in the second memory, so that it can have versatility. It is.

When data for variable-length encoding is generated with a dedicated configuration as in the conventional example, arithmetic processing other than data generation for variable-length encoding is impossible. If other processing such as addition and comparison is to be performed in addition to the generation of data for variable-length encoding, an adder and a comparator besides a dedicated circuit for generating data for variable-length encoding Such a general-purpose circuit is required, and the area of the integrated circuit increases. However, according to the present invention, a circuit for generating data for variable-length encoding can be made versatile, and other processing such as addition and comparison can be performed using this circuit. Therefore, it is possible to generate data for variable-length encoding and perform other processing without increasing the area of the integrated circuit as compared with a case where only data for variable-length encoding is generated. It is.

Further, since the data before the variable-length encoding is present in the second memory, it is checked whether the data after the variable-length encoding is correctly converted after the variable-length encoding with the data in the second memory. By comparing the data, you can check and debug.

Note that the last data indicates, for example, data written to the last address when comparing a certain address to a certain address in the first memory.
Further, by detecting the last data, the execution of the comparison instruction is terminated, and the end flag signal is written to the second memory.

When performing variable-length coding, etc.,
By reading the data written by the comparison instruction and reading the final data including the end flag signal, the end of the data can be detected, and the variable length encoding process can be executed without any trouble.

According to a fourth aspect of the present invention, there is provided a data processing device, comprising: a control unit for outputting a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, and an end flag signal when executing an instruction; , A first data register that receives a comparison data setting signal as input, sets a data to be compared, a second data register that stores data of the first memory, and an instruction execution signal. , A search frequency counter for outputting the number of searches to the first memory to the control unit, a comparison signal and an execution data signal to which an instruction execution signal, output data of the first data register and output data of the second data register are input. An output unit, a second memory that receives a memory write control signal and an execution data signal of the execution unit, And a third data register for storing an address of the second memory as input completion flag signal.

Then, when the comparison instruction is executed, the output data of the first data register and the second data register are input to the execution unit by the instruction execution signal to compare the data, and at the same time, the search number counter is counted up. Until the output of the number-of-times counter reaches a predetermined value, the end flag signal is deactivated, and when the output of the number-of-searches counter reaches the predetermined value, the control unit ends the comparison instruction and activates the end flag signal. By outputting the comparison signal of the execution unit to the control unit and controlling the writing to the second memory, both when the end flag signal is in the inactive state and when the end flag signal is in the active state, the data is transferred to the second memory. An execution data signal indicating data of the first memory that did not match the number of times the comparison data matched is written, and the end flag signal is activated. And so as to store the last written address of the second memory to the third data register when it is on purpose.

According to this configuration, a comparison instruction can be executed for an arbitrary value by setting data to be compared in the first data register, and a search number counter for counting the number of searches in the comparison range is provided. The comparison instruction can be ended, thereby generating an end flag signal, and setting the memory address as a third address as a memory address setting register.
Since the data can be stored in the third data register, the memory address having the final data can be detected only by reading the data in the third data register.

As described above, the number of times that the comparison data matches and the data that does not match are written into the second memory,
Thereafter, the data in the second memory can be read every cycle at an arbitrary time, so that data processing such as variable-length encoding processing can be continuously performed. Further, instead of writing the end flag signal to the second memory, the memory address having the final data is held in the third register, so that the number of bits of the second memory is reduced.
In the case of claim 3 described above, 1 is added to the end flag portion.
The number of bits increases (portion 4z in FIG. 8). In the case of claim 4, since the last address is stored in the third register, the address where the last data is stored can be known. Further, by setting an arbitrary value in the first data register, it is possible to deal with all kinds of data, and it is versatile.

The operation other than the above is the same as that of the third aspect.

According to a fifth aspect of the present invention, there is provided a data processing apparatus which outputs a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, an end flag signal, and a search count setting signal when executing an instruction. A first memory that receives a memory read control signal, a first data register that receives a comparison data setting signal and sets data to be compared, and a second data register that stores data of the first memory A search number counter for inputting an instruction execution signal and outputting the number of searches to the first memory; a third data register for inputting a search number setting signal and setting a final value of the number of searches; An execution unit that receives output data of the first data register and the output data of the second data register and outputs a comparison signal and an execution data signal; A second memory to which the write control signal, the execution data signal of the execution unit, and the end flag signal are inputted, and a coincidence which receives the output of the search counter and the value of the third register as input and outputs a coincidence signal to the control unit A detection circuit.

Then, when the comparison instruction is executed, the output data of the first data register and the second data register are input to the execution unit by the instruction execution signal to compare the data, and at the same time, the search counter is counted up, Until the coincidence signal of the detection circuit is generated, the end flag signal is deactivated, the control unit ends the comparison instruction in response to the coincidence signal of the coincidence detection circuit, and the end flag signal is activated, and the execution unit Is output to the control unit to control the writing to the second memory, so that when the end flag signal is in the inactive state and in the active state, the comparison data is stored in the second memory. The execution data signal and the end flag signal indicating the data of the first memory that did not match the number of times of writing are written.

According to this configuration, the comparison instruction can be executed for an arbitrary value by setting the data to be compared in the first data register, and the number of searches for the comparison range can be set by the third data register. It can be set arbitrarily, and the comparison command can be ended with an arbitrary number of searches. As a result, the end flag signal can be written in the second memory, so that the final data can be detected only by reading the written data in the second memory.

As described above, the number of times that the comparison data matches and the data that did not match and the end flag signal are written into the second memory, and then the data in the second memory is written at an arbitrary time (in the order of writing). 3) Since reading is possible every cycle, it is possible to continuously execute data processing such as variable length coding. Further, by setting an arbitrary value in the third data register and the first data register, it is possible to deal with all kinds of data, and it is versatile.

The operation other than the above is the same as that of the third aspect.

According to a sixth aspect of the present invention, at the time of executing an instruction, a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, an end flag signal, a search count setting signal, and a selection signal are output. A control unit, a first memory that receives a memory read control signal, a first data register that receives a comparison data setting signal and sets data to be compared, and a second memory that stores data of the first memory. And a third data register for setting an initial value of the number of searches by inputting a search number setting signal, and an instruction execution signal and output data of the third data register to input the remaining data to the first memory. A search counter for outputting a search count, an instruction execution signal and a first
An execution unit that receives the output data of the second data register and the output data of the second data register and outputs a comparison signal and an execution data signal; and an input of the output of the search counter and the data signal of the number of matches in the execution data signal. Adder,
A selector for selecting either the output of the adder or the data signal of the number of matches by a selection signal generated by the control unit based on the data signal of the number of matches in the execution data signal; and a memory write control signal and a selector in the execution data signal. A second memory to which the data of the first memory that did not match, the output of the selector, and the end flag signal are input.

Then, when the comparison instruction is executed, the output data of the first data register and the second data register are input to the execution unit by the instruction execution signal to compare the data, and at the same time, the search number counter is counted down, The end flag signal is deactivated until the output of the counter reaches a first predetermined value or the data signal of the number of matches in the execution data signal reaches a second predetermined value,
When the output of the search number counter reaches the first predetermined value, the control unit ends the comparison instruction and activates the end flag signal, or the data signal of the number of matches in the execution data signal becomes the second predetermined value. When the value reaches the value, the control unit ends the comparison instruction and activates the end flag signal,
Output the comparison signal of the execution unit to the control unit and
Of the first memory that does not match the number of matches of the comparison data to the second memory both when the end flag signal is in the inactive state and when the end flag signal is in the active state. run shows the data data signal and the end flag signal and the lump can write the output of the adder as a data signal matches the number in the execution data signal matches all the remaining data to be compared when it reaches a predetermined value The matched data of the first memory and the end flag signal are written to the second memory.

According to this configuration, the comparison instruction can be executed for an arbitrary value by setting the data to be compared in the first data register, and the number of comparison range searches can be performed by the third data register. It can be set arbitrarily, and the comparison command can be ended with an arbitrary number of searches. Also,
When the comparison data successively matches, the remaining search data is also considered to match, and the search instruction can be terminated to reduce the search time. Thus, the end data can be detected only by writing the end flag signal on the second memory and reading the written data of the second memory.

As described above, the number of times the comparison data matches and the data that did not match and the end flag signal are written into the second memory, and then the data in the second memory is written at an arbitrary time (in the order of writing). 3) Since reading is possible every cycle, it is possible to continuously execute data processing such as variable length coding. Further, when the comparison data successively matches, the remaining search data is also regarded as matching, and the search time can be reduced by terminating the comparison instruction, so that the processing time can be reduced. Further, by setting an arbitrary value in the search number counter and the first data register, it is possible to deal with all kinds of data, and it is versatile.

The operation other than the above is the same as that of the third aspect.

According to a seventh aspect of the present invention, a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, an end flag signal, a search count setting signal, a consecutive match count setting signal, A control unit that outputs a selection signal; a first memory that receives a memory read control signal; a first data register that receives a comparison data setting signal and sets data to be compared; A second data register for storing data, a third data register for inputting a search count setting signal and setting an initial value of the search count, and a count for successively matching the comparison result by inputting a continuous match count setting signal. A fourth data register to be set, an instruction execution signal and output data of the third data register are input and the remaining search times to the first memory are performed. , An execution unit that receives an instruction execution signal, output data of the first data register and the output data of the second data register, and outputs a comparison signal and an execution data signal, and an output of the search number counter. An adder that receives the data signal of the number of matches in the execution data signal as an input, a match detection circuit that receives the data signal of the number of matches and the output of the fourth data register to detect data match, and a match detection circuit A selector for selecting one of the output of the adder and the data signal of the number of matches by a selection signal generated by the control unit in response to the output of the memory unit; and a first memory that does not match the memory write control signal and the execution data signal. And a second memory to which the data of the selector, the output of the selector, and the end flag signal are input.

Then, when the comparison instruction is executed, the output data of the first data register and the second data register are input to the execution unit by the instruction execution signal to compare the data, and at the same time, the search number counter is counted down, Until the output of the counter reaches a predetermined value or the coincidence output of the coincidence detection circuit is generated, the end flag signal is deactivated, and when the output of the search counter reaches the predetermined value, the control unit issues a comparison instruction. End and activate the end flag signal, or terminate the comparison instruction in the control unit in response to the coincidence output of the coincidence detection circuit to activate the end flag signal and send the comparison signal of the execution unit to the control unit. Output to control the writing to the second memory so that when the end flag signal is in the inactive state and in the activated state Writing a first execution data signal and the end flag signal indicating the data of the memory that did not match the both number of matched comparison data to the second memory when,
In response to the coincidence output of the coincidence detection circuit, the first data that coincides with the output of the adder assuming that all the remaining data to be compared coincides
Is written to the second memory.

According to this configuration, a comparison instruction can be executed for an arbitrary value by setting data to be compared in the first data register, and the number of searches for the comparison range can be performed by the third data register. It can be set arbitrarily, and the comparison command can be ended with an arbitrary number of searches. Also,
By arbitrarily setting the number of matches in the fourth data register, when the comparison data successively matches by an arbitrary number, the remaining search data is also regarded as matching, and the comparison instruction is terminated, thereby reducing the search time. . Thus, the end data can be detected only by writing the end flag signal on the second memory and reading the written data of the second memory.

As described above, the number of times that the comparison data matched and the data that did not match and the end flag signal are written to the second memory, and then the data in the second memory is written at an arbitrary time (in the order of writing). 3) Since reading is possible every cycle, it is possible to continuously execute data processing such as variable length coding. In addition, by setting the number of matches in the fourth data register arbitrarily, if the comparison data matches an arbitrary number consecutively, the remaining search data is also considered to match, and the comparison instruction is terminated, thereby shortening the search time. Since the size can be reduced, the processing time can be reduced.
Further, by setting an arbitrary value in the search number counter and the first data register, it is possible to deal with all kinds of data, and it is versatile.

The operation other than the above is the same as that of the third aspect.

The data processing device according to claim 8 is the data processing device according to claim 3, claim 4, claim 5, claim 6, or claim 7, wherein the execution unit outputs the first data register. The data is input as first data to be compared, and the output data of the second data register is input to the first data.
Input as the second data to be compared with the data of the first
When the first and second data match, a value 1 is output when the first and second data match, and the match signal is activated. When the first and second data do not match, A comparison circuit that outputs the second data and deactivates the coincidence signal, and receives the output of the comparison circuit as an input, and executes the shift of the output of the comparison circuit according to the state of the coincidence signal given from the comparison circuit. A shifter whose presence or absence is switched, an adder circuit having the output of the shifter as one input, a register having the output of the adder as an input, and having a value 0 as one input, and having the output of the register being the other input and having a selection signal. A selection circuit for setting either one of them as the other input of the addition circuit.

Then, in response to the selection signal, the value of the value 0 is set in the selection circuit.
And selecting one of the outputs of the register
When the first data and the second data do not match, the number of the second data that matches the first data after the mismatch between the first and second data last time and the current first number
And the unmatched second data are output as an execution data signal.

According to this configuration, claim 3, claim 4,
In addition to the operation of the data processing device according to the fifth, sixth or seventh aspect, the same operation as that of the arithmetic unit of the first aspect is obtained.

According to a ninth aspect of the present invention, in the data processing apparatus according to the third, fourth, fifth, sixth, or seventh aspect, the execution unit includes an output unit of the first data register. The data is input as first data to be compared, and the output data of the second data register is input to the first data.
Input as the second data to be compared with the data of the first
When the first and second data match, a value 1 is output when the first and second data match, and the match signal is activated. When the first and second data do not match, A comparison circuit that outputs the second data and also makes the match signal inactive, a flag register that receives the match signal, a first register that receives the output of the comparison circuit, A shifter that receives an output as an input, and switches whether or not to execute the shift of the output of the first register in accordance with the state of the coincidence signal provided from the flag register; a second register that receives the output of the shifter as an input; An adder circuit having an output of the register as one input, a third register having an output of the adder circuit as an input, and a value 0 having one input and an output of the third register having the other input. Depending on an input selection signal and a selection circuit to the other input of either an adder circuit.

Then, in response to the selection signal, the value of the value 0 is set in the selection circuit.
And the output of the third register to select the first data after the previous first and second data did not match when the first data and the second data did not match. The number of matched second data and the second data that does not match the current first data are output as an execution data signal in pairs.

According to this configuration, claim 3, claim 4,
In addition to the operation of the data processing device according to the fifth, sixth or seventh aspect, the same operation as that of the arithmetic unit of the second aspect is obtained.

[0058]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

(First Embodiment: Claims 1, 2, 8,
An arithmetic device according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2 (numerical values are expressed in HEX).

FIG. 1 is a block diagram showing the configuration of the arithmetic unit according to the first embodiment of the present invention. In FIG. 1, reference numeral 1A is a comparison circuit, reference numeral 2A is an 8-bit first register, reference numeral 3A is a flag register, reference numeral 4A is a shifter, reference numeral 5A is a 9-bit second register, reference numeral 6A is a selection circuit, and reference numeral 7A is an addition circuit for performing accumulation, and 8A is a 14-bit third register.

Hereinafter, the operation of the arithmetic unit will be described. The comparison circuit 1A operates at an operation clock (waveform 1B in FIG. 2).
The first data output in synchronization with the rising edge of
2B, value 0: HEX notation) and second data (FIG. 2)
Compared with the waveform 2B), when the second data is a value 0, the coincidence signal (waveform 5B in FIG. 2) is set to a high level and output to the flag register 3A, and the flag register 3A is synchronized with the rising edge of the operation clock. Latch (see waveform 7 in FIG. 2).
B). At the same time, the comparison circuit 1A stores the value 1 in the register 2A.
(A waveform 4B in FIG. 2), and the first register 2A latches in synchronization with the rise of the operation clock (a waveform 6B in FIG. 2).

On the other hand, when the first data and the second data do not match, the comparison circuit 1A outputs a match signal (waveform 5 in FIG. 2).
B) is set to the low level and output to the flag register 3A, which latches in synchronization with the rise of the operation clock (waveform 7B in FIG. 2). At the same time, the second data (waveform 4B in FIG. 2) is output to the first register 2A, and the first register 2A latches in synchronization with the rise of the operation clock (waveform 6B in FIG. 2).

When the coincidence signal (waveform 7B in FIG. 2) is at a high level, the shifter 4A shifts the value of the first register 2A (waveform 6B in FIG. 2) to the left by 8 bits and sets the value to 100
(HEX notation, waveform 8B in FIG. 2) is output to the second register 5A (waveform 8B in FIG. 2), and is output to the second register 5A.
Latches in synchronization with the rise of the operation clock (waveform 9B in FIG. 2). When the coincidence signal is at the low level, the shifter 4A outputs the value of the first register 2A (waveform 6 in FIG. 2).
The shift of B) is not executed, and the value of the first register 2A is output to the second register 5A as it is (waveform 8 in FIG. 2).
B), the second register 5A latches in synchronization with the rise of the operation clock (waveform 9B in FIG. 2).

The selection circuit 6A outputs a selection signal (waveform 12 in FIG. 2).
When B) is low, a value 0 (waveform 10B in FIG. 2) is output, and when high, a third register 8A (waveform 11B in FIG. 2) latches the output of the adder circuit 7A in synchronization with the rising edge of the clock. ) Output.

The addition circuit 7A receives the output of the second register 5A (waveform 9B in FIG. 2) and the output of the selection circuit 6A (waveform 10B in FIG. 2), and performs an addition of both. 3 to the register 8A for accumulation. However, the third register 8A needs to be initialized before the execution of a series of arithmetic operations, and the value when the selection signal is at the low level is used as the result of this arithmetic device. Of the 14 bits of the operation result of this operation device, the lower 8 bits indicate data other than the value 0, and the upper 6 bits indicate the number of consecutive values 0.

By changing the value of the first data, this device can perform the above-described operation not only on the value 0 but also on any data. The shifter 4A and the adder circuit 7A By controlling the selection circuit 6A, only the function of the comparison circuit 1A is used, or by controlling the comparison circuit 1A, the addition circuit 7A, and the selection circuit 6A, the shifter 4A is controlled.
, The comparison circuit 1A, the shifter 4A,
By controlling the selection circuit 6A, it is possible to use only the function of the addition circuit 7A, so that the device is versatile.

Further, the first and second registers 2A, 5
A and the flag register 3A, the comparison circuit 1
A, even if the operations of the shifter 4A and the adder circuit 7A are not fast, it is possible to execute a process of sequentially detecting and outputting the number of times the zero data continues and the non-zero data following the zero data. The same process can be performed for other data.

In the above embodiment, the comparison circuit 1
The first register 2A and the flag register 3A are arranged between the A and the shifter 4A, and the second register 5A is arranged between the shifter 4A and the adder circuit 7A. If the operation proceeds and the comparison circuit 1A, the shifter 4A, and the addition circuit 7A can operate at high speed, the first register 2A, the flag register 3A, and the second register 5A can be omitted. The time chart in this case shows that the one-cycle delay caused by the first register 2A and the flag register 3A in the signal applied from the comparison circuit 1A to the shifter 4A is eliminated, and the second signal in the signal applied from the shifter 4A to the addition circuit 7A is eliminated. Register 5 of
The one-cycle delay caused by A is eliminated.

(Second Embodiment: Claims 1, 2, 8,
An arithmetic device according to the second embodiment of the present invention will be described with reference to FIGS. 1 and 3 (numerical values are expressed in HEX).

FIG. 1 is a block diagram showing a configuration of an arithmetic unit according to the second embodiment of the present invention, and the configuration has been described in the first embodiment. The difference from the configuration of the first embodiment is that the second register 5A has 9
What was a bit register is now a 14-bit register, and the rest is the same as in the first embodiment.

Hereinafter, the operation of the arithmetic unit will be described. The comparison circuit 1A operates at an operation clock (waveform 1C in FIG. 3).
The first data output in synchronization with the rising edge of
3C, value 0: HEX notation) and second data (FIG. 3)
When the second data has a value of 0, the coincidence signal (waveform 5C in FIG. 3) is set to a high level and output to the flag register 3A, and the flag register 3A is synchronized with the rising edge of the operation clock. Latch (see waveform 7 in FIG. 3).
C). At the same time, the comparison circuit 1A stores the value 1 in the register 2A.
(A waveform 4C in FIG. 3), and the first register 2A latches in synchronization with the rising edge of the operation clock.

On the other hand, when the first data and the second data do not match, the comparison circuit 1A outputs a match signal (waveform 5 in FIG. 3).
C) is set to the low level and output to the flag register 3A, which latches in synchronization with the rise of the operation clock (waveform 7C in FIG. 3). At the same time, the second data (waveform 4C in FIG. 3) is output to the first register 2A, and the first register 2A latches in synchronization with the rise of the operation clock.

When the coincidence signal (waveform 7C in FIG. 3) is at the low level, shifter 4A shifts the value of first register 2A (waveform 6C in FIG. 3) left by 6 bits, and the value after left shift by 6 bits (HEX notation, waveform 8C in FIG. 3) is output to the second register 5A (waveform 8C in FIG. 3), and the second register 5A latches in synchronization with the rise of the operation clock (waveform 9C in FIG. 3). . When the coincidence signal is at the high level, the shifter 4A does not shift the value of the first register 2A (waveform 6C in FIG. 3), and keeps the value of the first register 2A as it is, that is, the value 1 is changed to the first value. 2 (the waveform 8C in FIG. 3), and the second register 5A latches in synchronization with the rising edge of the operation clock (the waveform 9 in FIG. 3).
C).

The selection circuit 6A outputs a selection signal (waveform 12 in FIG. 3).
When C) is at a low level, a value 0 (waveform 10C in FIG. 3) is output, and when it is at a high level, a third register 8A (waveform 11C in FIG. 3) latches the output of the adder circuit 7A in synchronization with the rise of the clock. ) Output.

The addition circuit 7A receives the output of the second register 5A (waveform 9C in FIG. 3) and the output of the selection circuit 6A (waveform 10C in FIG. 3), and adds both of them. 3 to the register 8A for accumulation. However, the third register 8A needs to be initialized before the execution of a series of arithmetic operations, and the value when the selection signal is at the low level is used as the result of this arithmetic device. Of the 14 bits of the operation result of this operation device, the upper 8 bits indicate data other than the value 0, and the lower 6 bits indicate the number of consecutive values 0.

This apparatus is a versatile apparatus as in the case of the above-described first embodiment.

Also, the first and second registers 2A, 5
A and the effect of providing the flag register 3A are the same as those of the first embodiment described above.

Also, in this embodiment, the first and second registers 2A and 5A and the flag register 3A can be omitted, as in the case of the above-described first embodiment. As in the first embodiment, the one-cycle delay caused by the first and second registers 2A and 5A and the flag register 3A is eliminated.

Hereinafter, a description will be given of an embodiment of a data processing device including the arithmetic units described in the first and second embodiments as main components of an execution unit.

(Third Embodiment: Corresponding to Claim 3) A data processing apparatus according to a third embodiment of the present invention will be described with reference to FIGS.

FIG. 4 is a block diagram showing a configuration of a data processing device according to the third embodiment of the present invention. In FIG. 4, reference numeral 1 denotes a control unit, reference numeral 2 denotes an execution unit, reference numeral 3 denotes a first memory, reference numeral 4 denotes a second memory, and reference numeral 5 denotes a first memory as an 8-bit comparison data setting register.
Reference numeral 6 denotes a second data register as an 8-bit memory data register, and reference numeral 7 denotes a search counter. The first data in the arithmetic unit of FIG. 1 is temporarily stored in the first data register 5, and the second data is also temporarily stored in the second data register.

Reference numeral 8 denotes an instruction execution signal, reference numeral 9 denotes a comparison data setting signal, reference numeral 10 denotes a memory read control signal, reference numeral 11 denotes an end flag signal, reference numeral 12 denotes a memory write control signal, reference numeral 13 denotes a comparison signal, and reference numeral Reference numeral 14 denotes an output signal of the search number counter 7, reference numeral 15 denotes a memory data signal, reference numeral 16 denotes an output signal of the first data register 5, reference numeral 17 denotes an output signal of the second data register 6, reference numeral 18
Is an execution data signal. The comparison signal 13 shown in FIG.
Corresponds to the coincidence signal output from the comparison circuit 1A or the output of the flag register 3A in the arithmetic device.

In the data processing apparatus according to the third embodiment, the first memory 3 is a memory of addresses 0 to 63 and 8 bits of data, and the second memory 4 is a memory of addresses 0 to 63 and 15 bits of data. The search number counter counts from 0 to 64. Also,
FIG. 5 is an operation waveform diagram of the data processing device according to the third embodiment of the present invention. FIG. 6 shows the contents of the second memory 4 at the end of writing, and reference numeral 1z denotes a memory address (decimal display). 2z indicates memory data,
Reference numeral 3z indicates the number of matches, and reference numeral 4z indicates an end flag. The memory data 2z is data written in the arithmetic device of FIG. 1 without being shifted.
The number of matches 3z is data written in a shifted state in the arithmetic device of FIG. Also, the memory data 2z and the number of matches 3z
May be reversed.

The operation of the data processing apparatus configured as described above will be described below with reference to FIGS.

The waveform 1w in FIG. 5 is used as the operation clock (CLK) of the data processing device in FIG. 4, and the data processing device in FIG. 4 operates in synchronization with the rising edge of the operation clock 1w. The control unit 1 receives an instruction execution signal 8
(Waveform 2w in FIG. 5) is set to the H level, and the comparison instruction is executed. The control unit 1 outputs a memory read control signal 10, reads a memory data signal 15 corresponding to the memory read address signal (waveform 3w in FIG. 5) from the first memory 3, and stores it in the second data register 6. (Waveform 4w in FIG. 5). Before the execution of the comparison instruction, data to be compared is set in the first data register 5 by the comparison data setting signal 9 (waveform 5w in FIG. 5, the comparison value is 0).

The execution unit 2 causes the execution signal 2 of the second data register 6 to be
7 (waveform 4w in FIG. 5) and the output signal 16 (waveform 5w in FIG. 5) of the first data register 5, and when they match, a comparison signal 13 is output to the control unit 1 to control By setting the memory write control signal 12 (waveform 6w in FIG. 5) output from the unit 1 to the H level, writing to the second memory 4 is not performed, and the number of consecutive matches is counted. If they do not match, the result signal of the execution unit 2 is sent to the address (single address) indicated by the memory write address signal (waveform 8w in FIG. 5) of the memory write control signal 12 of the second memory 4 as the execution data signal 18. (Waveform 7w in FIG. 5) and the end flag signal 11 (Waveform 9w in FIG. 5) are simultaneously written.

When the output signal 14 (waveform 10w in FIG. 5) of the search number counter 7 indicates 64, the control unit 1 sets the instruction execution signal 8 to L level to end the comparison instruction, and changes the end flag signal 11 to H level. And

In FIG. 6, memory address 1z is
The 8-bit memory data 2z of 0 to 7 corresponds to the waveform 4w of FIG. 5, the 6-bit matching frequency 3z of 8 to 13 corresponds to the waveform 7w of FIG. Corresponds to the waveform 9w in FIG.

As described above, in the data processing device according to the third embodiment, the comparison instruction is issued to an arbitrary value by setting the data to be compared in the first data register 5 as the comparison data setting register. Executable,
Further, the comparison instruction can be ended by the search number counter 7 that counts the number of searches in the comparison range, whereby the end flag signal 11 can be written in the second memory 4. The final data can be detected simply by reading out the data.

As described above, the data which did not match the number of times the comparison data matched and the end flag signal 11
It is possible to read the data in the second memory 4 every cycle (in the order in which they were written) at an arbitrary time thereafter, so that data processing such as variable-length coding can be performed continuously. Becomes possible. Further, by setting an arbitrary value in the first data register 5, it is possible to deal with any data, and the versatility is enhanced.

The number of times that the comparison data matches the number of times that the comparison data based on the variable-length coding matches the number of times that the comparison data matches the number of times that the comparison data does not match and the end flag signal 11 are written into the second memory 4. It is possible to execute a variable-length coding instruction at any time, without being limited by the time of capturing data that does not match with.

Also, the execution unit 2 having a function other than the detection of the number of values 0 can be used because it has a path for storing data in the second memory 4, so that it can have versatility. Is possible.

When data for variable-length encoding is generated by a dedicated configuration as in the conventional example, arithmetic processing other than data generation for variable-length encoding is impossible. If other processing such as addition and comparison is to be performed in addition to the generation of data for variable-length encoding, an adder and a comparator besides a dedicated circuit for generating data for variable-length encoding Such a general-purpose circuit is required, and the area of the integrated circuit increases. However, according to the present invention, a circuit for generating data for variable-length encoding can be made versatile, and other processing such as addition and comparison can be performed using this circuit. Therefore, it is possible to generate data for variable-length encoding and perform other processing without increasing the area of the integrated circuit as compared with a case where only data for variable-length encoding is generated. It is.

Further, since data before the variable length encoding is present in the second memory 4, it is determined whether the data after the variable length encoding is correctly converted by comparing the data in the second memory 4 with the variable length encoding. By comparing the data after the comparison, it can be confirmed and debugged.

The last data indicates, for example, data written to the last address when a comparison is made from a certain address to a certain address in the first memory 3. Further, by detecting the last data, the execution of the comparison instruction is completed, and the end flag signal 11 is written into the second memory 4.

When performing variable-length coding, etc.,
By reading out the data written by the comparison instruction and reading out the final data including the end flag signal 11, the end of the data can be detected and the variable length encoding process can be executed.

Further, even if data on an arbitrary memory is input to the first data register 5 as data to be compared, this data processing device can be similarly realized.
That is, at present, the value of the data register 5 is compared with the data of the first memory 3. However, any data of the memory is written into the data register 5, and the value of a certain memory is compared with the value of the first memory 5. This means that the data may be compared.

(Fourth Embodiment: Corresponding to Claim 4) A data processing apparatus according to a fourth embodiment of the present invention will be described with reference to FIGS.

FIG. 7 is a block diagram showing a configuration of a data processing device according to the fourth embodiment of the present invention. In FIG. 7, reference numeral 4a denotes a second memory, and reference numeral 19 denotes a third data register as a 6-bit memory address storage register.

In the data processing apparatus according to the fourth embodiment, the control unit 1, the execution unit 2, the first
The configuration of the memory 3, the first data register 5, the second data register 6, and the search counter 7 is substantially the same as the corresponding part of FIG. 4 shown in the third embodiment. The difference from the third embodiment is that the second memory 4
a is a memory of addresses 0 to 63 and data of 14 bits, and is provided with a third data register 19 as a memory address storage register. FIG. 8 is an operation waveform diagram of the data processing device according to the fourth embodiment of the present invention.

The operation of the data processing apparatus configured as described above will be described below with reference to FIGS. 7 and 8.

The waveform 1w in FIG. 8 is used as the operation clock (CLK) of the data processing device in FIG. 7, and the data processing device in FIG. 7 operates in synchronization with the rising edge of the operation clock 1w. The control unit 1 receives an instruction execution signal 8
(Waveform 2w in FIG. 8) is set to the H level, and the comparison instruction is executed. The control unit 1 outputs a memory read control signal 10, and a read address signal (waveform 3 in FIG.
w) the memory data signal 15 for the address corresponding to
Is read from the first memory 3 and stored in the second data register 6 (waveform 4w in FIG. 8). Before the execution of the comparison instruction, data to be compared is set in the comparison data setting register 5 by the comparison data setting signal 9 (waveform 5w in FIG. 8, the comparison value is 0).

The execution unit 2 receives the output signal 1 of the second data register 6 by the instruction execution signal 8 comprising a comparison instruction.
7 (waveform 4w in FIG. 8) and the output signal 16 (waveform 5w in FIG. 8) of the first data register 5 are compared, and if they match, a comparison signal 13 is output to the control unit 1 to control By setting the memory write control signal 12 (waveform 6w in FIG. 8) output from the unit 1 to the H level, writing to the second memory 4a is not performed, and the number of consecutive matches is counted. If they do not match, the second memory 4a
To the address (single address) indicated by the memory write address signal (waveform 8w in FIG. 8) of the memory write control signal 12 of FIG.
And the end flag signal 11 (waveform 9w in FIG. 8) is simultaneously written.

The control unit 1 indicates that the output signal 14 (waveform 10w in FIG. 8) of the search number counter 7 indicates 64,
The address indicated by the memory write address signal (waveform 8w in FIG. 8) of the memory write control signal 12 at that time is stored in the third data register 19 (waveform 11 in FIG. 8).
w), the comparison instruction is ended by setting the instruction execution signal 8 to L level, and the end flag signal 11 (waveform 9w in FIG. 8)
Is set to the H level.

As described above, in the data processing device according to the fourth embodiment, the comparison instruction is issued to an arbitrary value by setting the data to be compared in the first data register 5 as the comparison data setting register. Executable,
The comparison instruction can be ended by the search number counter 7 that counts the number of searches in the comparison range, thereby generating an end flag signal 11 and setting the memory address at that time to a third data register 19 as a memory address setting register. , It is possible to detect the memory address where the final data is located simply by reading the data in the third data register 19.

As described above, it is possible to write the number of times that the comparison data matched and the data that did not match to the second memory 4a, and thereafter read the data of the second memory 4a every cycle at an arbitrary time. Therefore, it is possible to continuously execute data processing such as variable length coding processing. Also, instead of writing the end flag signal to the second memory 4a, the memory address having the final data is stored in the third memory 4a.
, The number of bits in the second memory 4a is reduced. In the case of the third embodiment described above, one bit is added to the end flag part (the part 4z in FIG. 6). In the case of the fourth embodiment, the address where the final data is stored is stored in the third register 19, so that the address where the final data is stored can be known.

Further, by setting an arbitrary value in the first data register 5, it is possible to deal with all kinds of data, and the versatility is enhanced.

The other effects are similar to those of the third embodiment.

The data processing device can be realized in the same manner even if data on an arbitrary memory is input to the first data register 5 as data to be compared.

(Fifth Embodiment: Corresponding to Claim 5) A data processing apparatus according to a fifth embodiment of the present invention will be described with reference to FIGS.

FIG. 9 is a block diagram showing a configuration of a data processing device according to the fifth embodiment of the present invention. 9, reference numeral 1a denotes a control unit, reference numeral 20 denotes a third data register serving as a 7-bit search count setting register, reference numeral 21 denotes a coincidence detection circuit, reference numeral 22 denotes a search count number setting signal, and reference numeral 23 denotes a third search count number setting signal. Data register 20
The reference numeral 24 denotes a match detection signal.

In the data processing device according to the fifth embodiment, the execution unit 2, the first memory 3, the second
The configuration of the memory 4, the first data register 5, the second data register 6, and the search counter 7 is substantially the same as the corresponding part of FIG. 4 shown in the third embodiment. The difference from the third embodiment is that the control unit 1
a that the match detection signal 24 is input instead of the output signal 14 of the search number counter 7, that the search count number setting signal 22 is output, and that the third data register 20
And a coincidence detecting circuit 21. FIG. 10 is an operation waveform diagram of the data processing device according to the fifth embodiment of the present invention.

The operation of the data processing device configured as described above will be described below with reference to FIGS. 9 and 10.

The waveform 1w in FIG. 10 is used as the operation clock (CLK) of the data processing device in FIG. 9, and the data processing device in FIG. 9 operates in synchronization with the rising edge of the operation clock 1w. The control unit 1a sets the instruction execution signal 8 (waveform 2w in FIG. 10) to the H level and executes the comparison instruction. The control unit 1a receives a memory read control signal 10
Is output, and the memory read address signal therein (FIG. 1)
The memory data signal 15 for the address corresponding to the 0 waveform 3w) is read and stored in the second data register 6 (waveform 4w in FIG. 10). Before the execution of the comparison instruction, data to be compared is set in the first data register 5 by the comparison data setting signal 9 (waveform 5w in FIG. 10, the comparison value is 0). Search count number (final value of search count) is used as search count setting signal 2
2 (the waveform 12w in FIG. 10, the search count number is 64).

The execution unit 2 is determined by the comparison instruction execution signal 8.
Are the output signal 17 of the second data register 6 (waveform 4w in FIG. 10) and the output signal 16 of the first data register 5.
(Waveform 5w in FIG. 10) are compared, and if they match, a comparison signal 13 is output to the control unit 1a, whereby the memory write control signal 12 (Waveform 6w in FIG. 10) output from the control unit 1a is output. By setting it to the H level, writing to the second memory 4 is not performed, and the number of consecutive matches is counted. In the case of a mismatch, the result signal of the execution unit 2 is sent to the address (single address) indicated by the memory write address signal (waveform 8w in FIG. 10) of the memory write control signal 12 of the second memory 4 as the execution data signal 18. (Waveform 7w in FIG. 10) and the end flag signal 11 (Waveform 9w in FIG. 10) are simultaneously written.

The match detection circuit 21 is provided with a search number counter 7
Of the output signal 14 (the waveform 10w in FIG. 10) and the output signal 23 of the third data register 20. When both the output signal 14 and the output signal 23 indicate the value 64, the coincidence detection signal 24 is set to H. Output as a level (FIG. 10
Waveform 13w). The control unit 1a outputs the coincidence detection signal 2
4, the instruction execution signal 8 is set to L level to end the comparison instruction, and the end flag signal (waveform 9 in FIG. 10).
w) is set to the H level.

As described above, in the data processing device according to the fifth embodiment, the comparison instruction is issued to an arbitrary value by setting the data to be compared in the first data register 5 as the comparison data setting register. Executable,
Further, the number of searches in the comparison range can be arbitrarily set in the third data register 20 as a search count number setting register, and the comparison instruction can be terminated with an arbitrary search number.
Thus, the end flag signal 11 can be written on the second memory 4, so that the last data can be detected only by reading the written data of the second memory 4.

As described above, the data which did not match the number of times the comparison data matched and the end flag signal 11
It is possible to read the data in the second memory 4 every cycle (in the order in which they were written) at an arbitrary time thereafter, so that data processing such as variable-length coding can be performed continuously. Becomes possible. Further, by setting an arbitrary value in the third data register 20 and the first data register 5, any data can be handled, and the versatility is enhanced.

The other effects are the same as in the third embodiment.

Further, even if data on an arbitrary memory is input to the first data register 5 as data to be compared, this data processing device can be similarly realized.

(Sixth Embodiment: Corresponding to Claim 6) A data processing apparatus according to a sixth embodiment of the present invention will be described with reference to FIGS.

FIG. 11 is a block diagram showing a configuration of a data processing device according to the sixth embodiment of the present invention. FIG.
In FIG. 1, reference numeral 1b denotes a control unit, reference numeral 7a denotes a search counter, reference numeral 14 denotes an output signal of the search counter 7a, reference numeral 18a denotes a coincidence number data signal of the execution data signal 18, and reference numeral 18b denotes an execution data signal 18. Among them, the mismatched data signal, reference numeral 20a is a third data register as a 6-bit search count number setting register, reference numeral 22 is a search count number setting signal, reference numeral 23 is an output signal of the third data register 20a, and reference numeral 25 is An adder, reference numeral 26 denotes an output signal of the adder 25, reference numeral 27 denotes a selector,
Reference numeral 28 denotes an output signal of the selector 27, and reference numeral 29 denotes a selection signal of the selector 27.

In the data processing apparatus according to the sixth embodiment, the execution unit 2, the first memory 3, the second
The configuration of the memory 4, the first data register 5 and the second data register 6 is substantially the same as that of the corresponding portion of FIG. 9 shown in the fifth embodiment. The difference from the fifth embodiment is that the control unit 1b receives the output signal 14 of the search number counter 7a and the coincidence number data signal 18a as inputs, outputs the selection signal 29, and sets the search count number. The third data register 20a as a register has 6 bits, the output signal 23 of the third data register 20a is loaded by the search counter 7a having a down counter configuration, and the adder 25 and the selector 27 are provided. That is. Note that the third data register 20a stores an initial value of the number of searches. FIG. 12 is an operation waveform diagram of the data processing device according to the sixth embodiment of the present invention, and FIG.
1z indicates a memory address (decimal display), 2z indicates memory data, 3z indicates the number of matches, and 4z indicates an end flag. The memory data 2z is data written in the arithmetic device of FIG. 1 in a non-shifted state, and the match count 3z is data written in the arithmetic device of FIG. 1 in a shifted state. Further, the position of the memory data 2z and the number of matches 3z may be reversed depending on the setting of the shifter of the arithmetic unit.

The operation of the data processing device configured as described above will be described below with reference to FIGS.

The waveform 1w in FIG. 12 is used as the operation clock (CLK) of the data processing device in FIG. 11, and the data processing device in FIG. 11 operates in synchronization with the rising edge of the operation clock 1w. The control unit 1b sets the instruction execution signal 8 (waveform 2w in FIG. 12) to the H level and executes the comparison instruction. The control unit 1b outputs the memory read control signal 10 (waveform 3w in FIG. 12), reads the memory data signal 15 corresponding to the address, and stores it in the second data register 6 (waveform 4w in FIG. 12). Before the execution of the comparison instruction, the data to be compared is set in the first data register 5 by the comparison data setting signal 9 (waveform 5w in FIG. 12, the comparison value is 0), and the third data register 20 is set.
The search count number (search count initial value) is set to a by the search count number setting signal 22 (the waveform 12w in FIG. 12, the search count number is 63).

The execution unit 2 is determined by the comparison instruction execution signal 8.
Compares the output signal 17 of the second data register (waveform 4w in FIG. 12) with the output signal 16 of the first data register 5 (waveform 5w in FIG. 12). By outputting to the control unit 1b, the memory write control signal 12 output from the control unit 1b is output.
(Waveform 6w in FIG. 12) is set to H level,
Is not written into the memory 4, and the number of consecutive matches is counted. In the case of non-coincidence, the execution data signal 18 (coincides with the non-coincidence data signal 18b) with the address (single address) indicated by the memory write address signal (waveform 8w in FIG. 12) of the memory write control signal 12 of the second memory 4. As a result 18a), the result signal (waveform 7w in FIG. 12) of the execution unit 2 is written, and the end flag signal 11 (waveform 9w in FIG. 12) is simultaneously written.

The control unit 1b sets the initial value of the search counter 7a (the value of the third data register 20a) based on the instruction execution signal 8, performs countdown, and outputs the output signal 14 of the search counter 7a (see FIG. When the waveform 10W) is 0, the instruction execution signal 8 is set to L level to end the comparison instruction, and the end flag signal 11 is set to H level. Alternatively, when the number of consecutive matches is a certain value (waveform 7w in FIG. 12, 700 in this case), the remaining search range is also considered to match the data to be compared, and the selection signal 29 (waveform 14w in FIG. 12) is set to H. When the lower order 8 bits of the output signal 14 (10W in FIG. 12) and the execution unit result signal are 0, the upper 6 bits are added by the adder 25, and the output data 26 (waveform 15w in FIG. ) Is written in the memory 4 in place of the number of times 18a are continuously matched, the comparison command is ended, and the end flag signal 11 is set to the H level.

In FIG. 13, the memory address 1z corresponds to the waveform 8w in FIG. 12, the 8-bit memory data 2z of 0 to 7 corresponds to the waveform 4w in FIG. Corresponds to the waveform 7w in FIG.
The bit end flag 4z corresponds to the waveform 9w in FIG.

As described above, in the data processing device according to the sixth embodiment, the comparison instruction is issued to an arbitrary value by setting the data to be compared in the first data register 5 as the comparison data setting register. Executable,
Further, the number of searches in the comparison range can be arbitrarily set by the third data register 20a as a search count number setting register, and the comparison instruction can be terminated with an arbitrary search number. In addition, when the comparison data successively matches, the remaining search data is regarded as matching, and the comparison instruction is terminated, thereby reducing the search time. Thereby, the end flag signal 1
1 is written in the second memory 4 and the last data can be detected only by reading the written data in the second memory 4.

As described above, the data which did not match the number of times the comparison data matched and the end flag signal 11
It is possible to read the data in the second memory 4 every cycle (in the order in which they were written) at an arbitrary time thereafter, so that data processing such as variable-length coding can be performed continuously. Becomes possible. Further, when the comparison data successively matches, the remaining search data is also regarded as matching, and the search time can be reduced by terminating the comparison instruction, so that the processing time can be reduced. Further, by setting an arbitrary value in the search counter 7a and the first data register 5, any data can be handled, and the versatility is enhanced.

The effects other than those described above are the same as in the third embodiment.

The data processing device can be realized in the same manner even if data on an arbitrary memory is input to the first data register 5 as data to be compared.

(Seventh Embodiment: Corresponding to Claim 7) A data processing apparatus according to a seventh embodiment of the present invention will be described with reference to FIGS.

FIG. 14 is a block diagram showing a configuration of a data processing device according to the seventh embodiment of the present invention. FIG.
4, reference numeral 1c denotes a control unit, reference numeral 30 denotes a fourth data register as a coincidence number setting register, reference numeral 31 denotes a coincidence detection circuit, reference numeral 32 denotes a continuous coincidence number setting signal, and reference numeral 33 denotes a fourth data register 30. Output signal,
Reference numeral 34 denotes a coincidence detection signal.

In the data processing device according to the seventh embodiment, the execution unit 2, the first memory 3, the second
The configuration of the memory 4, the first data register 5, the second data register 6, the third data register 20a, the adder 25, and the selector 27 are the same as those of FIG. 11 shown in the sixth embodiment. Substantially the same. The difference from the sixth embodiment is that the control unit 1c receives the match detection signal 34 instead of the match count data signal 18a, outputs the continuous match count setting signal 32, and sets the match count register As a fourth data register 30 and a coincidence detecting circuit 31. Also,
FIG. 15 is an operation waveform diagram of the data processing device according to the seventh embodiment of the present invention.

The operation of the data processing device configured as described above will be described below with reference to FIGS. 14 and 15.

The waveform 1w in FIG. 15 is used as the operation clock (CLK) of the data processing device in FIG. 14, and the data processing device in FIG. 14 operates in synchronization with the rising edge of the operation clock 1w. The control unit 1c sets the instruction execution signal 8 (waveform 2w in FIG. 15) to the H level and executes the comparison instruction. The control unit 1c outputs the memory read control signal 10 (waveform 3w in FIG. 15), reads the memory data signal 15 corresponding to the address, and stores it in the second data register 6 (waveform 4w in FIG. 15). Before the execution of the comparison instruction, the data to be compared is set in the first data register 5 by the comparison data setting signal 9 (waveform 5w in FIG. 15, the comparison value is 0), and the third data register 20 is set.
The search count number (search count initial value) is set to a by the search count number setting signal 22 (waveform 12w in FIG. 15, the search count number is 63), and matches with the fourth data register 30 by the continuous match number setting signal 32. Set the number of times (Fig. 15
And the number of matches is 7).

The execution unit 2 is determined by the comparison instruction execution signal 8.
Are the output signal 17 of the second data register 6 (waveform 4w in FIG. 15) and the output signal 16 of the first data register 5.
(Waveform 5w in FIG. 15) are compared, and if they match, a comparison signal 13 is output to the control unit 1c, so that the memory write control signal 12 (Waveform 6w in FIG. 15) output from the control unit 1c is output. By setting it to the H level, writing to the second memory 4 is not performed, and the number of consecutive matches (waveform 7w in FIG. 15) is counted. In the case of non-coincidence, the execution data signal 18 (coincides with the non-coincidence data signal 18b) with the address (single address) indicated by the memory write address signal (waveform 8w in FIG. 15) of the memory write control signal 12 of the second memory 4. As the number of times 18a), the result signal of the execution unit 2 (waveform 7w in FIG. 15) is written and the end flag signal 11 (waveform 9w in FIG. 15) is simultaneously written.

The control unit 1c sets the initial value of the number-of-retrievals counter 7a (the value of the third data register 20a) based on the instruction execution signal 8, performs countdown, and sets the output signal 14 of the number-of-retrievals counter 7a to 0. At the time
The comparison instruction is ended by setting the instruction execution signal 8 to L level, and the end flag signal is set to H level, or the number of consecutive matches is equal to the set value of the fourth data register 30, and the match detection signal Becomes H level (waveform 17 in FIG. 15).
w, 700), the remaining search range is considered to match the data to be compared, the selection signal 29 (waveform 14w in FIG. 15) is set to the H level, and the output signal 14 of the search times counter 7a and the execution unit result signal are compared. Lower 8 bits are 0
In this case, the upper 6 bits are added by the adder 25, and the output data 26 (the waveform 15w in FIG. 15) is written to the second memory 4 instead of the number of times of continuous matching 18a. The signal 11 is set to the H level.

As described above, in the data processing device according to the seventh embodiment, the comparison command is issued to an arbitrary value by setting the data to be compared in the first data register 5 as the comparison data setting register. Executable,
Further, the number of searches in the comparison range can be arbitrarily set by the third data register 20a as a search count number setting register, and the comparison instruction can be terminated with an arbitrary search number. Also, by setting the number of matches arbitrarily in the fourth data register 30 as a match number setting register,
When an arbitrary number of comparison data successively match, the remaining search data is also considered to match, and the comparison instruction is terminated, thereby reducing the search time. As a result, the end data can be detected only by writing the end flag signal 11 on the second memory 4 and reading the written data of the second memory 4.

As described above, the number of times the comparison data matched and the data that did not match the end flag signal 11
It is possible to read the data in the second memory 4 every cycle (in the order in which they were written) at an arbitrary time thereafter, so that data processing such as variable-length coding can be performed continuously. Becomes possible. Also, by setting the number of matches in the fourth data register 30 arbitrarily, if the comparison data matches an arbitrary number consecutively, the remaining search data is regarded as matching, and the comparison instruction is terminated. Can be reduced, so that the processing time can be reduced. Further, by setting an arbitrary value in the search counter 7a and the first data register 5, any data can be handled, and the versatility is enhanced.

The other effects are the same as those of the third embodiment.

The data processing device can be realized in the same manner even if data on an arbitrary memory is input to the first data register 5 as data to be compared.

[0144]

According to the arithmetic unit of the present invention, the first and second data are compared, and when the first and second data match, a value of 1 is output and the match signal is activated, When the first and second data do not match, a comparison circuit that outputs the second data and deactivates the match signal, an output of the comparison circuit as an input, and a comparison signal of the match signal given from the comparison circuit. The shifter switches the execution of the shift of the output of the comparison circuit depending on the state, and the addition circuit and the selection circuit for accumulating the output of the shifter are provided. The process of sequentially detecting and outputting the next non-zero data can be executed, and the same process can be performed on data other than zero, which is highly versatile. Also,
Only the function of the comparison circuit is used by controlling the shifter, the addition circuit, and the selection circuit. Only the function of the shifter is used by controlling the comparison circuit, the addition circuit, and the selection circuit. By controlling the circuit, it is possible to use only the function of the adder circuit, and the device becomes versatile.

Further, if the first and second registers and the flag register are provided, even if the operation of the comparison circuit, the shifter, and the addition circuit is not high speed, the number of times zero data continues and the non-zero A process of sequentially detecting and outputting data can be executed, and similarly, a process other than zero can be executed.

According to the data processing device of the present invention, after the number of matches and the mismatch data are simultaneously written in the second memory, the data in the second memory is read, so that the subsequent data processing can be performed continuously. It is possible, and it becomes possible to simultaneously detect the written final data of the second memory (claims 3 to 7). That is, in the present invention, the number of consecutive zero data and the non-zero data are packed and once written to the memory, and then the memory data is read every cycle, so that the variable length coding can be continuously performed. . In the conventional example, since the data when the zero decode signal is at the L level is used, processing cannot be performed in the cycle of the H level section.

[0147] The last data indicates, for example, the data written to the last address when comparing from a certain address to a certain address in the memory. Also,
By detecting the last data, the execution of the comparison instruction is terminated, and an end flag is written to the memory.
In addition, when performing variable-length encoding processing or the like, the end of data can be detected and variable-length encoding processing can be executed by reading data written by the comparison instruction and reading the final data including the end flag signal. .

Further, an arbitrary value is set in the search number counter (in the case of claim 6 or 7) or the third data register (in the case of claim 5) and the first data register (in the case of claim 3 to 7). Can handle all kinds of data,
Versatile. Further, when a certain number of consecutive matches are made, the remaining search range is regarded as the same, and the processing time can be reduced by terminating the comparison instruction (in the case of claim 6 or 7). In this case, the number of consecutive matches with the comparison data can be arbitrarily set, and the versatility is high.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arithmetic unit according to first and second embodiments of the present invention.

FIG. 2 is an operation waveform diagram of the arithmetic unit according to the first embodiment of the present invention.

FIG. 3 is an operation waveform diagram of an arithmetic unit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a data processing device according to a third embodiment of the present invention.

FIG. 5 is an operation waveform diagram of a data processing device according to a third embodiment of the present invention.

FIG. 6 is a schematic diagram showing a memory configuration of a data processing device according to a third embodiment of the present invention at the end of writing.

FIG. 7 is a block diagram showing a configuration of a data processing device according to a fourth embodiment of the present invention.

FIG. 8 is an operation waveform diagram of the data processing device according to the fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a data processing device according to a fifth embodiment of the present invention.

FIG. 10 is an operation waveform diagram of a data processing device according to a fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a data processing device according to a sixth embodiment of the present invention.

FIG. 12 is an operation waveform diagram of a data processing device according to a sixth embodiment of the present invention.

FIG. 13 is a schematic diagram showing a memory configuration of a data processing device according to a sixth embodiment of the present invention at the end of writing.

FIG. 14 is a block diagram showing a configuration of a data processing device according to a seventh embodiment of the present invention.

FIG. 15 is an operation waveform diagram of the data processing device according to the seventh embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a conventional data processing device.

FIG. 17 is an operation waveform diagram of a conventional data processing device.

[Explanation of symbols]

 1A Comparison circuit 2A First register 3A Flag register 4A Shifter 5A Second register 6A Selection circuit 7A Addition circuit 8A Third register 1, 1a, 1b, 1c Control unit 2 Execution unit 3 First memory 4 Second Memory 5 First data register 6 Second data register 7, 7a Search frequency counter 8 Instruction execution signal 9 Comparison data setting signal 10 Memory read control signal 11 End flag signal 12 Memory write control signal 13 Comparison signal 14 Output signal 15 Memory Data signal 16 Output signal 17 Output signal 18 Execution data signal 18a Number of match data signal 18b Mismatch data signal 19 Third data register 20 Third data register 20a Third data register 21 Match detection circuit 22 Search count setting signal 23 Output signal No. 24 Match detection signal 25 Adder 26 Output signal 27 Selector 28 Output signal 29 Selection signal 30 Fourth data register 31 Match detection circuit 32 Continuous match count setting signal 33 Output signal 34 Match detection signal 1x Memory 2x Read control circuit 3x Zero Run counter 4x Zero decoder 5x Memory data signal 6x Memory read control signal 7x Enable signal 8x Zero decode signal 9x Zero run count signal

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuo Takahashi 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Masatoshi Matsuo 1006 Kadoma Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. In-company (72) Inventor Katsuyoshi Higashijima 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Yuki Yonezawa 1006 Oji Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) Reference Reference JP-A-11-163736 (JP, A) Table 2 2-500634 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 7/00 102 G06F 7/00 G06F 5 / 00 H03M 7/40

Claims (9)

(57) [Claims] 1. The first data to be compared and second data to be compared with the first data are input, and the first and second data are compared to execute the first data.
And when the second data matches, outputs a value of 1 and activates the match signal. When the first and second data do not match, outputs the second data and outputs the match signal. A comparison circuit to be inactivated, a shifter which receives an output of the comparison circuit as an input, and switches whether or not to execute the shift of the output of the comparison circuit in accordance with the state of the coincidence signal given from the comparison circuit;
An adder circuit having an output of the shifter as one input; a register having an output of the adder circuit as an input; and a value 0 having one input and an output of the register having the other input according to a selection signal. A selection circuit for setting either the value 0 or the output of the register in response to the selection signal. When the second data is inconsistent, the first
And the number of the second data that matches the first data after the mismatch of the second data and the second data that does not match the current first data are output as a pair. An arithmetic unit characterized in that: 2. The first data to be compared and the second data to be compared with the first data are input, and the first and second data are compared to execute the first data.
And when the second data matches, outputs a value of 1 and activates the match signal. When the first and second data do not match, outputs the second data and outputs the match signal. A comparison circuit for inactivating a signal, a flag register for receiving the coincidence signal, a first register for receiving an output of the comparison circuit, a flag register for receiving an output of the first register, A shifter that switches whether or not to execute the shift of the output of the first register in accordance with the state of the match signal provided from the second register, a second register that receives the output of the shifter as an input, and an output of the second register. An adder circuit as one input, a third register as an input of the output of the adder circuit, and a value 0 as one input and an output of the third register as the other input; A selection circuit for inputting one of the values to the other input of the addition circuit according to the selection signal, wherein the selection circuit outputs one of the value 0 and the output of the third register in response to the selection signal. By selecting, when the first data and the second data do not match, the second data that matches the first data after the last time the first and second data did not match An arithmetic unit, wherein the number and the second data that does not match the current first data are output as a pair. 3. A control unit for outputting a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, and an end flag signal when executing an instruction,
A first memory that receives the memory read control signal as input, a first data register that receives the comparison data setting signal as input, and sets data to be compared, and a second memory that stores data from the first memory A data register, and a search counter for inputting the instruction execution signal and outputting the number of searches to the first memory to the control unit;
An execution unit which receives the instruction execution signal, the output data of the first data register and the output data of the second data register, and outputs a comparison signal and an execution data signal; a memory write control signal and an execution of the execution unit A second memory to which a data signal and the end flag signal are inputted, wherein output data of the first data register and the second data register is output to the execution unit by the instruction execution signal when a comparison instruction is executed. At the same time as the input and data comparison, the search counter is counted up, and the end flag signal is deactivated until the output of the search counter reaches a predetermined value. When the control unit reaches a predetermined value, the control unit ends the comparison command and activates the end flag signal, By outputting a comparison signal of the execution unit to the control unit and controlling the writing to the second memory, the second flag is output both when the end flag signal is in the inactive state and when the end flag signal is in the active state. A data processing device, wherein the execution data signal indicating the data of the first memory that did not match the number of times the comparison data matched and the end flag signal are written to the memory. 4. A control unit for outputting a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, and an end flag signal when executing an instruction,
A first memory that receives the memory read control signal, a first data register that receives the comparison data setting signal and sets data to be compared, and a second memory that stores data of the first memory A data register, a search counter for inputting the instruction execution signal and outputting the number of searches to the first memory to the control unit, the instruction execution signal, the first data register, and the second data register An execution unit that receives the output data of the execution unit and outputs a comparison signal and an execution data signal; a second memory that receives the memory write control signal and the execution data signal of the execution unit; and an end flag signal. And a third data register for storing an address of the second memory as an input, wherein the instruction execution signal is used when the comparison instruction is executed. The output data of the first data register and the second data register are input to the execution unit, the data is compared, and at the same time the search number counter is counted up, and the output of the search number counter reaches a predetermined value. Until the end flag signal is deactivated, and when the output of the search counter reaches a predetermined value, the control unit ends the comparison instruction and the end flag signal is activated, and the execution unit Is output to the control unit to control writing to the second memory, so that the end flag signal is output to the second memory both when the end flag signal is in the inactive state and when the end flag signal is in the active state. The execution data signal indicating the data of the first memory that did not match the number of times the comparison data matched is written, and the end flag signal is written. There the data processing apparatus characterized by storing the last written address of said second memory to said third data register when it becomes an active state. 5. A control unit for outputting a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, an end flag signal, and a search count setting signal when executing an instruction, and receiving the memory read control signal. A first memory, a first data register that receives the comparison data setting signal and sets data to be compared, a second data register that stores data in the first memory, A search number counter that receives a signal as an input and outputs the number of searches to the first memory; a third data register that receives the search number setting signal as an input and sets a final value of the number of searches; 1
An execution unit that receives a data register and output data of the second data register as inputs and outputs a comparison signal and an execution data signal; the memory write control signal; the execution data signal of the execution unit; and the end flag signal; And a match detection circuit that receives the output of the search number counter and the value of the third register as inputs and outputs a match signal to the control unit. An output signal of the first data register and the second data register is input to the execution unit in response to an execution signal, data is compared, and at the same time, the search counter is counted up. The end flag signal is kept in an inactive state until the occurrence of the signal, and the control is performed in response to the match signal of the match detection circuit. The control unit terminates the comparison command, activates the termination flag signal, outputs the comparison signal of the execution unit to the control unit, and controls the writing to the second memory, thereby completing the termination. The execution data signal and the end flag indicating data of the first memory that did not match the number of times the comparison data matched with the second memory both when the flag signal was in the inactive state and when the flag signal was in the active state. A data processing device for writing a signal. 6. A control unit for outputting a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, an end flag signal, a search count setting signal, and a selection signal when executing an instruction, and the memory read control. A first memory that receives a signal, a first data register that receives the comparison data setting signal and sets data to be compared, a second data register that stores data of the first memory, A third data register that receives the search count setting signal and sets an initial value of the search count;
A search counter for inputting the instruction execution signal and the output data of the third data register and outputting a remaining number of searches to the first memory; an instruction execution signal, the first data register; An execution unit that receives the output data of the second data register as input and outputs a comparison signal and an execution data signal, and an addition that receives as input the output of the search counter and the data signal of the number of matches in the execution data signal A selector for selecting either the output of the adder or the data signal of the number of matches by the selection signal generated by the control unit based on the data signal of the number of matches in the execution data signal; and the memory. The write control signal, the data of the first memory that did not match in the execution data signal, the output of the selector, and the end flag signal. And a second memory for inputting output data of the first data register and the second data register to the execution unit according to the instruction execution signal when a comparison instruction is executed, and comparing the data. At the same time, the search number counter is counted down, and the process is terminated until the output of the search number counter reaches a first predetermined value or the data signal of the number of matches in the execution data signal reaches a second predetermined value. The flag signal is deactivated, and when the output of the search counter reaches the first predetermined value, the control unit terminates the comparison instruction to activate the end flag signal, or The data signal of the number of matches in the data signal is the second data signal.
When the predetermined value is reached, the control unit terminates the comparison instruction, activates the termination flag signal, outputs a comparison signal of the execution unit to the control unit, and writes the comparison signal to the second memory. Is performed, the data of the first memory, which does not match the number of times the comparison data matches, is stored in the second memory both when the end flag signal is in the inactive state and when the end flag signal is in the active state. Write the execution data signal and the end flag signal,
When the data signal of the number of matches in the execution data signal reaches a predetermined value, the data of the first memory and the end flag signal that match the output of the adder assuming that all the remaining data to be compared match. The data processing device according to claim 1, further comprising: 7. A control unit for outputting a memory read control signal, a memory write control signal, an instruction execution signal, a comparison data setting signal, an end flag signal, a search count setting signal, a continuous match count setting signal, and a selection signal when executing an instruction. When,
A first memory that receives the memory read control signal, a first data register that receives the comparison data setting signal and sets data to be compared, and a second memory that stores data of the first memory A data register, a third data register for inputting the search count setting signal and setting an initial value of the search count, and a fourth data register for inputting the continuous match count setting signal and setting the number of times the comparison result continuously matches
A data register, and a search frequency counter that receives the instruction execution signal and the output data of the third data register and outputs a remaining search frequency to the first memory;
An execution unit that receives the instruction execution signal, output data of the first data register and output data of the second data register, and outputs a comparison signal and an execution data signal; an output of the search counter and the execution data signal An adder that receives the data signal of the number of matches in the input, a match detection circuit that receives the data signal of the number of matches and the output of the fourth data register to detect data match, and the match detection circuit A selector for selecting one of the output of the adder and the data signal of the number of coincidences by the selection signal generated by the control unit by the output of the control unit; and a match between the memory write control signal and the execution data signal. A second memory that receives the data of the first memory that did not exist, the output of the selector, and the end flag signal as inputs. When the instruction is executed, the output data of the first data register and the second data register are input to the execution unit by the instruction execution signal, and the data is compared. Until the output of the counter reaches a predetermined value or the coincidence output of the coincidence detection circuit is generated, the end flag signal is kept in an inactive state, and the control is performed when the output of the search number counter reaches the predetermined value. A unit ending the comparison instruction to activate the end flag signal, or, in response to the coincidence output of the coincidence detection circuit, ending the comparison instruction in the control unit to activate the end flag signal; By outputting a comparison signal of the execution unit to the control unit to control writing to the second memory, The completion flag signal does not match the number of both matched comparison data to the second memory when and activation state when the deactivated state first
The execution data signal indicating the data of the memory and the end flag signal are written, and in response to the coincidence output of the coincidence detection circuit, all the remaining data to be compared coincide with the output of the adder. A data processing device for writing data in a first memory and the end flag signal to the second memory. 8. The execution unit inputs the output data of the first data register as first data to be compared, and compares the output data of the second data register with the first data. Enter as the second data,
By performing a comparison of the first and second data, a value 1 is obtained when the first and second data match.
And a comparison circuit that outputs a second signal when the first and second data do not match, and outputs the second data when the first and second data do not match. A shifter that receives the output of the comparison circuit as an input, and switches whether or not to execute the shift of the output of the comparison circuit in accordance with the state of the coincidence signal given from the comparison circuit; and an addition circuit that receives the output of the shifter as one input. A register that receives an output of the adding circuit as an input,
A selection circuit having a value of 0 as one input, an output of the register as the other input, and one of the other inputs of the addition circuit according to a selection signal, wherein the selection is performed according to the selection signal. The circuit selects either the value 0 or the output of the register so that when the first data and the second data do not match,
And performing the execution by pairing the number of the second data that matches the first data after the mismatch of the second data with the second data that does not match the current first data. 3. The method according to claim 2, wherein the data is output as a data signal.
Alternatively, the data processing device according to claim 7. 9. The execution unit inputs the output data of the first data register as first data to be compared, and compares the output data of the second data register with the first data. Enter as the second data,
By performing a comparison of the first and second data, a value 1 is obtained when the first and second data match.
And a comparison circuit that outputs a second signal when the first and second data do not match, and outputs the second data when the first and second data do not match. A flag register that receives a match signal, a first register that receives an output of the comparison circuit, and an output that receives an output of the first register. A shifter for switching whether to execute the shift of the output of the first register, and a second shifter which receives the output of the shifter as an input
, An addition circuit having the output of the second register as one input, a third register having an output of the addition circuit as an input, and a third register having a value of 0 as one input. A selection circuit that takes the output of the other input as the other input according to a selection signal, and selects one of the outputs of the third register according to the selection signal. By selecting any one of the outputs, when the first data and the second data do not match, the first data and the second data match with the first data after the mismatch between the first and second data last time. 4. The execution data signal according to claim 3, wherein the number of the second data and the second data that does not match the current first data are output as a pair. Claim 5, Claim The data processing device according to claim 6 or 7.