JP4211851B2 - Integrated circuit device - Google Patents

Description

  The present invention relates to an integrated circuit device.

  With the recent improvement of semiconductor technology, the demand for various electronic devices has been expanded. Such electronic devices often have a built-in CPU (Central-Processing-Unit) for processing various controls. In order to provide an electronic device incorporating such a processor with a higher level of processing capability, a method is known in which a coprocessor specialized for specific processing is provided separately from the CPU. In this case, the overall processing can be performed at high speed by causing the coprocessor to perform processing that the CPU is not good at.

However, due to restrictions on the bus connecting the CPU and the coprocessor, when there are multiple coprocessor processing results or when the data amount of the processing results is large, the CPU may receive the processing results from the coprocessor at a time. could not. For this reason, it is necessary for the CPU to receive information from the coprocessor in a plurality of times, which hinders improvement in processing capability. In order to further improve the processing capacity, it was necessary to increase the processing capacity by raising the operating clock or expanding the hardware scale, but these methods hinder low power consumption and cost reduction. It was.
Japanese Patent Laid-Open No. 2000-284963

  The present invention has been made in view of the above technical problems, and an object thereof is to provide an integrated circuit device that performs high-speed arithmetic processing while minimizing an increase in hardware scale. There is.

(1) The present invention
An integrated circuit device including a CPU that executes a given process based on an instruction code,
A data address supply line for supplying a data address output from the coprocessor to the CPU;
The CPU
A load store unit for writing data to the memory by supplying a data address to the memory via the data address bus and supplying write data via the write data bus;
A data address selection circuit that receives a data address supplied via the data address supply line and a data address output from the load store unit, and supplies any one of the data addresses to the data address bus;
It is characterized by including.

(2) The integrated circuit device of the present invention is
A data address selection signal supply line for supplying a data address selection signal from the coprocessor to the data address selection circuit;
The data address selection circuit includes:
Based on the data address selection signal, one of a data address supplied via the data address supply line and a data address output from the load store unit is supplied to the data address bus. It is characterized by.

(3) The present invention
An integrated circuit device including a CPU that executes a given process based on an instruction code,
A write data supply line for supplying the CPU with write data output from the coprocessor;
The CPU
A load store unit for writing data to the memory by supplying a data address to the memory via the data address bus and supplying write data via the write data bus;
A write data selection circuit that receives write data supplied via the write data supply line and write data output from the load store unit, and supplies any one of the write data to the write data bus;
It is characterized by including.

(4) The integrated circuit device of the present invention is
A write data selection signal supply line for supplying a write data selection signal from the coprocessor to the write data selection circuit;
The write data selection circuit includes:
Based on the write data selection signal, one of the write data supplied via the write data supply line and the write data output from the load store unit is supplied to the write data bus. It is characterized by.

(5) The present invention
An integrated circuit device including a CPU that executes a given process based on an instruction code,
A read data supply line for supplying read data output from the coprocessor to the CPU;
The CPU
A load store unit for reading data from the memory by supplying a data address to the memory via the data address bus and receiving read data via the read data bus;
A read data selection circuit which receives the read data supplied from the read data supply line and the read data supplied from the read data bus, and supplies any one of the read data to the load store unit;
It is characterized by including.

(6) The integrated circuit device of the present invention is
A read data selection signal supply line for supplying a read data selection signal from the coprocessor to a read data selection circuit;
The read data selection circuit includes:
One of the coprocessor read data and the CPU read data is supplied to the load store section based on the read data selection signal.

(7) The integrated circuit device of the present invention is
The CPU includes an ALU that performs arithmetic processing based on the instruction code,
The CPU
A first flag data supply line for supplying first flag data based on the arithmetic processing result of the ALU to the coprocessor;
A second flag data supply line for supplying second flag data based on the arithmetic processing result of the coprocessor to the ALU;
Including
The ALU is
A flag register for storing the first or second flag data;
A flag data selection circuit that receives the first and second flag data from the first and second flag data supply lines and supplies either of the first and second flag data to the flag register;
It is characterized by including.

(8) The integrated circuit device of the present invention is
The CPU
A flag data selection signal supply line for supplying a flag data selection signal from the coprocessor to the ALU;
The flag data selection circuit of the ALU selects one of the first and second flag data as the flag register based on the flag data selection signal supplied via the flag data selection signal supply line. It is characterized by outputting.

  The present embodiment is an integrated circuit device including a CPU that executes a given process based on an instruction code, and is output from an instruction code bus for supplying the instruction code from a memory to the CPU and a coprocessor. An instruction code supply line for supplying an instruction code to the CPU, wherein the CPU fetches the instruction code, an instruction code input via the instruction code bus, and the instruction code The present invention relates to an integrated circuit device including an instruction code selection circuit that receives an instruction code supplied via a supply line and supplies one of the instruction codes to the fetch unit.

  Thereby, an instruction code based on the arithmetic processing result of the coprocessor can be supplied to the CPU, for example, with one clock of the CPU operation clock. Further, the instruction code generated by the coprocessor can be fetched by the fetch unit of the CPU. Further, it is possible to cause the CPU to perform processing such as saturation processing at high speed.

  The embodiment further includes an instruction code selection signal supply line for supplying an instruction code selection signal from the coprocessor to the instruction code selection circuit, and the instruction code selection circuit receives the instruction code selection signal. On the basis of the instruction code, any one of an instruction code input via the instruction code bus and an instruction code supplied via the instruction code supply line may be supplied to the fetch unit.

As a result, the instruction code fetched by the fetch unit of the CPU can be selected and controlled on the coprocessor side, either the instruction code supplied from the coprocessor or the instruction code supplied from the instruction code bus.

  The present embodiment is an integrated circuit device including a CPU that executes a given process based on an instruction code, and is output from an instruction address bus for supplying an instruction address to a memory and a coprocessor. An instruction address supply line for supplying an instruction address to the CPU, wherein the CPU fetches the instruction code, an instruction address supplied via the instruction address supply line, and the fetch unit. And an instruction address selection circuit for supplying any one of the instruction addresses to the instruction address bus.

  Thereby, the instruction address based on the arithmetic processing result of the coprocessor can be supplied to the CPU, for example, by one clock of the CPU operation clock. Further, the instruction code corresponding to the instruction address generated by the coprocessor can be fetched by the fetch unit of the CPU.

  The present embodiment further includes a program counter that outputs a count value for generating the instruction address, and a count value supply line for supplying the count value to the coprocessor, the program counter The count value output from is supplied to the coprocessor via the count value supply line, and the fetch unit generates and generates the instruction address based on the count value output from the program counter The instruction address thus provided may be supplied to the instruction address selection circuit.

  Thus, the coprocessor can generate an instruction address based on the count value supplied from the CPU, and can cause the CPU to perform complicated processing such as loop processing at high speed.

  The embodiment further includes an instruction address selection signal supply line for supplying an instruction address selection signal from the coprocessor to the instruction address selection circuit, and the instruction address selection circuit receives the instruction address selection signal. Based on the instruction address supplied from the instruction address supply line and the instruction address supplied from the fetch unit, an instruction address may be supplied to the instruction address bus.

  As a result, the coprocessor can select and control the instruction address supplied to the instruction address bus to either the instruction address supplied from the coprocessor or the instruction address supplied from the fetch unit.

  The present embodiment also includes an instruction code bus for supplying an instruction code from the memory to the CPU, and an instruction code supply line for supplying an instruction code output from the coprocessor to the CPU. The CPU further includes the instruction code supplied via the instruction code supply line and the instruction code input via the instruction code bus, and supplies any one of the instruction codes to the fetch unit. An instruction code selection circuit may be included.

  The present embodiment is an integrated circuit device including a CPU that executes a given process based on an instruction code, and supplies first and second register data output from a coprocessor to the CPU. The CPU includes a register file including a plurality of registers, the first register data supplied via the first register data supply line, and the first register data supply line. A first register data selection circuit that receives internal data of the CPU and supplies any of the data to the register file, and the second register data output from the coprocessor includes the second register data The present invention relates to an integrated circuit device which is supplied to the register file via a register data supply line.

  As a result, a plurality of register data of the coprocessor can be supplied to the register file of the CPU with, for example, one clock of the CPU operation clock.

  The present embodiment further includes a first register data selection signal supply line for supplying a first register data selection signal from the coprocessor to the first register data selection circuit. The register data selection circuit may supply any one of the first register data and the internal data of the CPU to the register file based on the first register data selection signal. .

  Thereby, the data supplied to the register file can be selected and controlled on the coprocessor side to either the first register data supplied from the coprocessor or the data inside the CPU.

  The present embodiment also provides a register number supply for supplying a coprocessor designated register number indicating a register designated by the coprocessor among the plurality of registers of the register file from the coprocessor to the register file. The first register data selection signal is supplied to the register file, and the register file includes an internal number specified in the CPU and the coprocessor designation register number supplied from the coprocessor. A register number selection circuit that receives a designated register number and selects and outputs either the coprocessor designated register number or the internal designated register number based on the first register data selection signal; Based on the selected register number May be at least one of the number of registers is set to a writable state.

  Thereby, on the coprocessor side, the register number for storing the data supplied to the register file is selected and controlled to either the coprocessor designated register number supplied from the coprocessor or the internal designated number of the CPU. Can do.

  In this embodiment, the CPU uses the second register data supplied via the second register data supply line as a first input, and is supplied from the first register data selection circuit. A second register data selection circuit may be included which uses data as a second input and supplies any one of the first and second inputs to at least one of the plurality of registers.

  As a result, either the second register data supplied from the coprocessor or the data supplied from the first register data selection circuit can be selected and supplied to the register file.

  The present embodiment further includes a second register data selection signal supply line for supplying a second register data selection signal from the coprocessor to the second register data selection circuit. The register data selection circuit supplies one of the first and second inputs of the second register data selection circuit to at least one of the plurality of registers based on the second register data selection signal. You may do it.

  Thus, the coprocessor side selects and controls the data supplied to the register file to either the second register data supplied from the coprocessor or the data supplied from the first register data selection circuit. Can do.

  In addition, the present embodiment is an integrated circuit device including a CPU that executes a given process based on an instruction code, and a data address supply line for supplying a data address output from a coprocessor to the CPU The CPU supplies a data address to the memory via a data address bus and supplies write data via the write data bus, thereby writing data to the memory, and the data An integrated circuit device including a data address supplied via an address supply line and a data address output from the load store unit, and supplying any one of the data addresses to the data address bus About.

  As a result, the data address generated by the coprocessor can be supplied to the data address bus with one operating clock of the CPU, for example.

  The embodiment further includes a data address selection signal supply line for supplying a data address selection signal from the coprocessor to the data address selection circuit, and the data address selection circuit receives the data address selection signal. Based on the data address, either a data address supplied via the data address supply line or a data address output from the load store unit may be supplied to the data address bus.

  As a result, the data address supplied to the data address bus can be selected and controlled on the coprocessor side to either the data address supplied from the coprocessor or the data address supplied from the load store unit.

  Further, the present embodiment is an integrated circuit device including a CPU that executes a given process based on an instruction code, and supplies write data for supplying write data output from the coprocessor to the CPU. A load store unit that writes data to the memory by supplying a data address to the memory via a data address bus and supplying write data via a write data bus; An integrated circuit including a write data selection circuit that receives write data supplied via a write data supply line and write data output from the load store unit, and supplies any one of the write data to the write data bus Relates to the device.

  As a result, the write data generated by the coprocessor can be supplied to the write data bus at one operating clock of the CPU, for example.

  The embodiment further includes a write data selection signal supply line for supplying a write data selection signal from the coprocessor to the write data selection circuit, and the write data selection circuit receives the write data selection signal. Based on the write data, one of the write data supplied via the write data supply line and the write data output from the load store unit may be supplied to the write data bus.

  As a result, the write data supplied to the write data bus can be selected and controlled on the coprocessor side between the write data supplied from the coprocessor and the write data supplied from the load store unit.

  Further, the present embodiment is an integrated circuit device including a CPU that executes a given process based on an instruction code, and provides read data for supplying read data output from the coprocessor to the CPU. The CPU supplies a data address to the memory via a data address bus and receives read data via the read data bus, thereby reading data from the memory; and the read An integrated circuit comprising: a read data selection circuit that receives the read data supplied via a data supply line and read data supplied from the read data bus and supplies any one of the read data to the load store unit; Relates to the device.

  As a result, the read data generated by the coprocessor can be supplied to the load store unit with one operating clock of the CPU, for example.

  The present embodiment further includes a read data selection signal supply line for supplying a read data selection signal from the coprocessor to the read data selection circuit, and the read data selection circuit is based on the read data selection signal. Then, any one of the coprocessor read data and the CPU read data may be supplied to the load store unit.

  As a result, the read data supplied to the load store unit can be selected and controlled on the coprocessor side as either read data supplied from the coprocessor or read data supplied from the read data bus. In addition, the data address supplied to the data address bus can be selected and controlled on the coprocessor side to one of the data address supplied from the coprocessor and the data address supplied from the load store unit.

  In this embodiment, the CPU includes an ALU that performs arithmetic processing based on the instruction code, and the CPU supplies the first flag data based on the arithmetic processing result of the ALU to the coprocessor. A first flag data supply line, and a second flag data supply line for supplying second flag data based on the arithmetic processing result of the coprocessor to the ALU. One of the first and second flag data received from the flag register for storing the first or second flag data and the first and second flag data from the first and second flag data supply lines And a flag data selection circuit that supplies the flag register to the flag register.

  Thereby, the coprocessor can perform processing based on the first flag data supplied from the CPU. Further, the CPU can perform processing based on the second flag data based on the processing result of the coprocessor. Further, the integrated circuit device can perform saturation processing based on the first flag data at high speed.

  In this embodiment, the CPU further includes a flag data selection signal supply line for supplying a flag data selection signal from the coprocessor to the ALU, and the flag data selection circuit of the ALU includes the flag data selection circuit. One of the first and second flag data may be selectively output to the flag register based on the flag data selection signal supplied via the data selection signal supply line.

  Accordingly, the coprocessor side selects and controls the flag data supplied to the flag register to either the second flag data supplied from the coprocessor or the first flag data supplied from the ALU. Can do.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention. In the following drawings, the same reference numerals have the same meaning.

1. Integrated Circuit Device FIG. 1 is a configuration example of an integrated circuit device 1000 according to the present embodiment. The integrated circuit device 1000 includes a CPU (Central-Processing-Unit) 10, a memory 20, and a coprocessor 30, but is not limited thereto. For example, the integrated circuit device 1000 may have a configuration in which the memory 20 and the coprocessor 30 are omitted. The CPU 10 exchanges various information with the coprocessor 30. For example, the memory 20 stores instruction codes 22 and data 24 processed by the CPU 10.

  For example, the memory 20 receives an instruction address from the CPU 10 side via the instruction address bus 50 and outputs an instruction code stored in the memory 20 to the CPU 10 via the instruction data bus 60 according to the instruction address. Further, the memory 20 receives a data address from the CPU 10 side through, for example, the data address bus 70 and outputs the data 24 stored in the memory 20 to the CPU 10 through, for example, the data bus 80 in accordance with the data address. Note that an instruction address may be supplied to the memory 20 via the data address bus 70, or an instruction code may be supplied to the CPU 10 via the data bus 80. The CPU 10 can perform various processes based on the information acquired from the memory 20 as described above. The memory 20 can also store data output from the CPU 10 side, for example, via the data bus 80.

  On the other hand, the coprocessor 30 includes an arithmetic processing unit 32 that can process arithmetic operations that the CPU 10 is not good at at high speed. That is, the CPU 10 can perform efficient processing by using the coprocessor 30 according to the processing content.

  FIG. 2 is a configuration example of the CPU 10 according to the present embodiment. In FIG. 2, the connection between the CPU 10 and the coprocessor 30 is partially omitted in order to simplify the description of the configuration of the CPU 10. The CPU 10 includes a fetch unit 100 that performs instruction fetch, a direct value generation unit 200 that generates a direct value (also referred to as an immediate value), and a register file 300 that includes a plurality of registers. Furthermore, the CPU 10 includes an ALU (Arithmetic-and-Logic-Unit) 400 that performs arithmetic processing, a load store unit 500 that reads or writes data, and a decode control unit 600 that decodes and controls the instructions fetched by the fetch unit 100. Including.

  The fetch unit 100 fetches the instruction code 22 stored in the memory 20, for example, but is not limited to this. Further, the fetch unit 100 includes a program counter 110 that outputs a count value PC, and outputs an instruction address based on the count value output from the program counter 110 to, for example, the memory 20 when performing instruction fetch. When fetching an instruction, the fetch unit 100 outputs, for example, a value output from the program counter 110 to the memory 20 via the instruction address bus 50 as an instruction address, but is not limited thereto. When fetching an instruction, the fetch unit 100 may, for example, increment the count value of the program counter 110 after outputting the count value as an instruction address, or the incremented value of the count value of the program counter 110 may be used. It may be output as an instruction address.

  In addition, the fetch unit 100 outputs the fetched instruction code 22 to the decode control unit 600. Although omitted in FIG. 2, one end of a count value supply line PCC (see, for example, FIG. 3) is connected to the program counter 110 of the fetch unit 100. The program counter 110 can be connected to the coprocessor 30 via the count value supply line PCC. In this case, the program counter 110 of the fetch unit 100 can supply the count value PC to the coprocessor 30 via the count value supply line PCC. Note that the fetch unit 100 performs the next instruction fetch based on the control signal CS1 from the decode control unit 600, for example.

  The direct value generation unit 200 generates, for example, 32-bit direct data based on the control signal CS2 output from the decode control unit 600 when the instruction code 22 includes a direct value. The direct data generated by the direct value generation unit 200 is supplied to the ALU 400 and the load store unit 500 via the multiplexer (MUX) M1.

  The register file 300 includes a plurality of registers, for example, 16 registers R0 to R15. Each of the registers R0 to R15 is, for example, a 32-bit register, but is not limited thereto. The register file 300 can select an arbitrary register from each of the registers R0 to R15 based on the control signal CS3 output from the decode control unit 600, for example, and output a value stored in the register.

  The output RQ1 of the register file 300 is connected to, for example, the multiplexer M1, and the value output from the output RQ1 is supplied to the ALU 400 and the load store unit 500 via the multiplexer M1.

  The output RQ2 of the register file 300 is connected to the ALU 400 and the load store unit 500, for example. From the output RQ2, the value stored in the register selected based on the control signal CS3 is output. In addition, at least one of the registers R0 to R15 of the register file 300 can be set as a fixed register.

  The ALU 400 includes, for example, a first ALU input AIN1 and a second ALU input AIN2, and a value output from the output RQ2 of the second register selection circuit 320 is input to the first ALU input AIN1, for example. For example, the output of the multiplexer M1 is input to the ALU input AIN2. The ALU 400 performs arithmetic processing on the values input to the inputs AIN1 and AIN2 based on, for example, the control signal CS4 output from the decode control unit 600, and outputs the result from the ALU output AQ. The ALU output AQ is connected to the multiplexer M2, for example.

  The ALU 400 also includes a flag register 410, which stores flag data of, for example, a carry flag C (hereinafter also referred to as C flag), an overflow flag V, a zero flag Z, and a negative flag N. Although omitted in FIG. 2, the output of the flag register 410 is connected to, for example, one end of a flag register supply line FLC1 (first flag register supply line in a broad sense) (see FIG. 3). . The flag register 410 of the ALU 400 can be connected to the coprocessor 30 via the flag data supply line FLC1. In this case, the flag data C, V, Z, and N stored in the flag register 410 can be supplied to the coprocessor 30.

  The load store unit 500 receives the value output from the multiplexer M1 or the value output from the output RQ2 of the register file 300, and stores (writes) it in the memory 20 based on the control signal CS5 output from the decode control unit 600. . Further, the load store unit 500 reads (reads) data from the memory 20 based on the control signal CS5, and outputs the read data from the load data output LDD to, for example, the multiplexer M2.

  The decode control unit 600 receives, for example, the instruction code 22 from the fetch unit 100, decodes the instruction code 22, generates a control signal based on the result, and outputs the control signals CS1 to CS5. The decode control unit 600 can also generate a signal (not shown) for controlling the multiplexers M1 and M2.

  Further, the calculation result of the coprocessor 30 is supplied to the CPU 10 through, for example, the first register data supply line RDC1, but the present invention is not limited to this. The coprocessor 30 is supplied with the instruction code 22 from, for example, the fetch unit 100 via the instruction code input line IRC, but is not limited thereto.

  In addition, said structure is an example of a structure of CPU10, CPU10 is not limited to said structure.

2. Connection Relationship with Each Unit FIG. 3 is a diagram for explaining the connection relationship between the CPU 10 and the coprocessor 30.

  The integrated circuit device 1000 supplies an instruction address supply line CIAC for supplying the instruction address CIA generated on the coprocessor 30 side to the CPU 10 and an instruction code for supplying the instruction code IR2 generated on the coprocessor 30 side to the CPU 10. Includes line CICC. Further, the integrated circuit device 1000 supplies the CPU 10 with the instruction address selection signal supply line CSC11 for supplying the instruction address CIA supplied from the coprocessor 30 to the CPU 10 and the instruction code IR2 supplied from the coprocessor 30. Instruction address selection signal supply line CSC12.

  Further, the integrated circuit device 1000 includes first and second register data supply lines RDC1 and RDC2 for supplying the CPU 10 with the first and second register data RDT1 and RDT2 of the coprocessor 30. The integrated circuit device 1000 also supplies a first register data selection signal supply line CSC31 for supplying the first register data selection signal CS31 to the CPU 10 and a second register data selection signal CS32 for the CPU 10. A second register data selection signal supply line CSC32 is included.

  The first register data selection signal CS31 is a signal for selecting, for example, the first register data RDT1 of the coprocessor 30 or the data inside the CPU 10, for example, the second register data selection The signal CS32 is a signal for selecting either the second register data RDT2 of the coprocessor 30 or the data inside the CPU 10.

  Further, the integrated circuit device 1000 includes a register number supply line RNC for supplying the CPU 10 with a register number RNM designated by the coprocessor 30 (coprocessor designated register number in a broad sense). The register number RNM indicates, for example, the register number of the storage destination of the first register data RDT1.

  Further, the integrated circuit device 1000 includes a second flag data supply line FLC2 for supplying the CPU 10 with flag data FLD2 (second flag data in a broad sense) based on the arithmetic processing result on the coprocessor 30 side. Further, the integrated circuit device 1000 provides the CPU 10 with a flag data selection signal CS41 for selecting either the flag data FLD1 based on the arithmetic processing result on the ALU 400 side of the CPU 10 or the flag data FLD2 based on the arithmetic processing result on the coprocessor 30 side. Includes a flag data selection signal supply line CSC41.

  Further, the integrated circuit device 1000 includes. The integrated circuit device 1000 also includes a data address supply line DAC for supplying the data address DTAD generated on the coprocessor 30 side to the CPU 10. The integrated circuit device 1000 also includes a write data supply line WDAC for supplying write data WDA1 generated on the coprocessor 30 side to the CPU 10, and read data for supplying read data RDA1 generated on the coprocessor 30 side to the CPU 10. Includes supply line RDAC.

  The integrated circuit device 1000 also supplies the data address selection signal CS51 for selecting either the data address DTAD supplied from the coprocessor 30 or the data address CDAD generated inside the CPU 10 to the CPU 10. A selection signal supply line CSC51 is included. Further, the integrated circuit device 1000 has write data for supplying the CPU 10 with a write data selection signal CS52 for selecting either the write data WDA1 supplied from the coprocessor 30 or the write data WDA2 generated inside the CPU 10. A selection signal supply line CSC52 is included. Further, the integrated circuit device 1000 supplies the CPU 10 with a read data selection signal CS53 for selecting either the read data RDA1 supplied from the coprocessor 30 or the read data RDA2 supplied via the data bus 80, for example. Read data selection signal supply line CSC53 for this purpose is included.

  When one end of the instruction code input line IRC is connected to the fetch unit 100 and the other end of the instruction code input line IRC is connected to the coprocessor 30, the coprocessor 30 outputs the instruction code 22 output from the fetch unit 100. (IR1) can be received. Thereby, the coprocessor 30 can acquire the instruction code 22 output from the fetch unit 100 with one clock of the operation clock of the CPU 10. The instruction code 22 is composed of 32 bits, but is not limited to this.

  When the other end of the count value supply line PCC is connected to the coprocessor 30, the coprocessor 30 can receive the count value output from the program counter 110. Thereby, the coprocessor 30 can acquire the count value output from the program counter 110 with one clock of the operation clock of the CPU 10.

  FIG. 4 is a block diagram showing the connection between the fetch unit 100 of the CPU 10 and the coprocessor 30.

  The CPU 10 includes a fetch unit 100, an instruction code selection circuit MUX_IRC, and an instruction address selection circuit MUX_ADD, but is not limited thereto. The instruction code selection circuit MUX_IRC or the instruction address selection circuit MUX_ADD may be omitted. The fetch unit 100 includes a program counter 110, an instruction code register 120, and an arithmetic unit 130, but is not limited thereto. The computing unit 130 may be an adder or a subtracter.

  The CPU 10 and the coprocessor 30 operate in synchronization with the clock CLK, but are not limited to this.

  On the CPU 10 side, the count value PC is output from the program counter 110 of the fetch unit 100. The calculator 130 receives the output count value PC, adds a value of, for example, 4 to the count value PC, and outputs the result. The value output from the arithmetic unit 130 is input to one of the inputs of the instruction address selection circuit MUX_ADD, and the instruction address from the coprocessor 30 via the instruction address supply line CIAC is input to the other input of the instruction address selection circuit MUX_ADD. CIA is entered.

  The instruction address selection circuit MUX_ADD receives either the value output from the arithmetic unit 130 or the instruction address CIA based on the instruction address selection signal CS11 supplied from the coprocessor 30 via the instruction address selection signal supply line CSC11. Is supplied to the instruction address bus 50. That is, either the instruction address CIA supplied from the coprocessor 30 or the value output from the fetch unit 100 can be supplied to the instruction address bus 50. As a result, the coprocessor 30 can be controlled to change the instruction code 22 supplied to the CPU 10.

  Further, the output of the instruction address selection circuit MUX_ADD is input to the program counter 110. The program counter 110 stores a value output from the instruction address selection circuit MUX_ADD based on the clock CLK, for example. The count value PC output from the program counter 110 is supplied to the coprocessor 30 via the count value supply line PCC.

  The instruction code 22 based on the instruction address supplied to the instruction address bus 50, for example, is input to one of the inputs of the instruction code selection circuit MUX_IRC. The instruction code IR2 supplied from the coprocessor 30 via the instruction code supply line CICC is input to the other input of the instruction code selection circuit MUX_IRC. The instruction code selection circuit MUX_IRC selects either the instruction code 22 or the instruction code IR2 based on the instruction code selection signal CS12 supplied from the coprocessor 30 through the instruction code selection signal supply line CSC12, and fetches the instruction unit 100. To the instruction code register 120.

  That is, the instruction code IR2 generated on the coprocessor 30 side can be stored in the instruction code register 120 of the fetch unit 100. Thereby, the process with respect to CPU10 can be instruct | indicated on the coprocessor 30 side. The instruction code stored in the instruction code register 120 is supplied to the coprocessor 30 via the instruction code input line IRC.

  The coprocessor 30 can supply the instruction address CIA, the instruction code IR2, the instruction address selection signal CS11, and the instruction address selection signal CS12 to the CPU 10 with one operation clock of the CPU 10. Further, the instruction address selection signal CS11 and the instruction address selection signal CS12 may be generated inside the CPU 10.

  FIG. 5 is a block diagram showing the connection between the register file 300 and the coprocessor 30 of the CPU 10.

  The CPU 10 includes, but is not limited to, a register file 300, a register data selection circuit MUX_RG1 (first register data selection circuit in a broad sense), and a register number selection circuit MUX_RNM. For example, the register data selection circuit MUX_RG1 may be omitted. The register file 300 includes, but is not limited to, a register data selection circuit MUX_RG2 (second register data selection circuit in a broad sense), a plurality of registers R0 to R15, a register selection unit 310, and a logic circuit 320. . For example, although a plurality of registers R0 to R15 are illustrated in FIG. 5, the number of registers may be 32, for example, or may be set to an arbitrary number. For example, the register data selection circuit MUX_RG2 may be omitted. Note that the register data selection circuit MUX_RG1 in FIG. 5 corresponds to the multiplexer M2 in FIG.

  The first register data RDT1 is input from the coprocessor 30 to the input of the register data selection circuit MUX_RG1 via the first register data supply line RDC1. The internal data IDT of the CPU 10 is input to the other input of the register data selection circuit MUX_RG1. The internal data IDT of the CPU 10 corresponds to, for example, output data of the ALU 400 or data output from the output LDD of the load store unit 500, but is not limited thereto.

  Further, the first register data selection signal CS31 is supplied to the CPU 10 via the first register data selection signal supply line CSC31. Based on the first register data selection signal CS31, the register data selection circuit MUX_RG1 converts either the internal data IDT of the CPU 10 or the first register data RDT1 from the coprocessor 30 into a plurality of registers R0 to R0. Supply to at least one of R15. Further, for example, the register data selection circuit MUX_RG2 is provided between the register R15 and the register data selection circuit MUX_RG1, but the present invention is not limited to this. For example, the register data selection circuit MUX_RG2 may be provided between any of the other registers R0 to R14 and the register data selection circuit MUX_RG1, or a plurality of register data selection circuits MUX_RG2 may be provided.

  The register data selection circuit MUX_RG2 receives, for example, the output of the register data selection circuit MUX_RG1 and the second register data RDT2 supplied from the coprocessor 30 via the second register data supply line RDC2, and receives either of them. For example, it is supplied to the register R15. The register data selection circuit MUX_RG2 outputs and registers the register data selection circuit MUX_RG1 based on the second register data selection signal CS32 supplied from the coprocessor 30 via the second register data selection signal supply line CSC32. One of the data RDT2 is selected.

  Note that the register data selection signals CS31 and CS32 may be generated inside the CPU 10.

  Further, a register number RNM (coprocessor designation register number in a broad sense) designated by the coprocessor 30 is supplied from the coprocessor 30 to the CPU 10 via a register number supply line RNC. The register number RNM is supplied to one of the inputs of the register number selection circuit MUX_RNM. A register number INM (internally designated register number in a broad sense) designated within the CPU 10 is supplied to the other input of the register number selection circuit MUX_RNM. The register number selection circuit MUX_RNM selects one of the register numbers RNM and INM based on the register data selection signal CS31, for example, and supplies the selected register number to the register selection unit 310 of the register file 300.

  The register selection unit 310 selects one of the write enable signal lines W0 to W15 based on the register number output from the register number selection circuit MUX_RNM, and an active signal (for example, a high level) is selected for the selected write enable signal line. Signal). In FIG. 5, for example, the write enable signal line W0 corresponds to the register R0, and W1 corresponds to the register R1. Similarly, the write enable signal lines W2 to W15 correspond to the registers R2 to R15. Each of the registers R0 to R15 is set in a writable state when a signal supplied to the write enable signal lines W0 to W15 is set active. Here, the writable state indicates a state in which each of the registers R0 to R15 can store the supplied data.

  Each of the registers R0 to R15 stores the register data supplied via the register selection circuit MUX_RG1 or MUX_RG2 based on the signal supplied to the write enable signal lines W0 to W15. For example, when an active signal is supplied to the write enable signal line W0, the register R0 stores the register data supplied via the register selection circuit MUX_RG1.

For example, the logic circuit 320 is connected to the register R15 to which the register data selection circuit MUX_RG2 is connected. A write enable signal line W15 and a register data selection signal supply line CSC32 are connected to the logic circuit 320. For example, when an active signal is supplied to the write enable signal line W15, the register R15 is set in a writable state. Accordingly, the register R15 stores register data supplied via the register selection circuit MUX_RG2. Even when the register data selection signal CS32 supplied via the register data selection signal supply line CSC32 is set to active, the register R15 is set in a writable state. That is, the register R15 to which the register selection circuit MUX_RG2 is connected is set in a writable state when at least one of the signal supplied to the write enable signal line W15 and the register data selection signal CS32 is set active.

  FIG. 6 is a block diagram showing the connection between the ALU 400 of the CPU 10 and the coprocessor 30. The ALU 400 includes a flag register 410, an arithmetic processing unit 420 that performs arithmetic processing, and a flag data selection circuit MUX_FLG. Flag data FLD1 (first flag data in a broad sense) based on the computation result of the arithmetic processing unit 420 is supplied to the coprocessor 30 via a flag data supply line FLC1 (first flag data supply line in a broad sense). .

  The flag data selection circuit MUX_FLG has flag data FLD1 and flag data FLD2 (second flag data in a broad sense) supplied via a flag data supply line FLC2 (second flag data supply line in a broad sense). ) Is supplied. The flag data selection circuit MUX_FLG selects one of the flag data FLD1 and FLD2 based on the flag data selection signal CS41 supplied from the coprocessor 30 via the flag data selection signal supply line CSC41, and supplies it to the flag register 410. To do. The flag register 410 stores a value output from the flag data selection circuit MUX_FLG.

  Note that the flag data selection signal CS41 may be generated inside the CPU 10.

  FIG. 7 is a block diagram showing the connection between the load store unit 500 of the CPU 10 and the coprocessor 30. The CPU 10 includes a load store unit 500, a data address selection circuit MUX_DT, a write data selection circuit MUX_WD, and a read data selection circuit MUX_RD, but is not limited thereto. For example, the write data selection circuit MUX_WD or the like may be omitted.

  A data address DTAD for reading or writing data is supplied from the coprocessor 30 to the CPU 10 via the data address supply line DAC. Further, the write data WDA1 is supplied from the coprocessor 30 to the CPU 10 via the write data supply line WDAC. Further, read data RDA1 is supplied from the coprocessor 30 to the CPU 10 via the read data supply line RDAC.

  The load store unit 500 supplies the data address DTAD supplied from the coprocessor 30 and the data address CDAD generated inside the CPU 10 to the data address selection circuit MUX_DT. In addition, the load store unit 500 supplies the write data WDA1 supplied from the coprocessor 30 and the write data WDA2 generated inside the CPU 10 to the write data selection circuit MUX_WD.

  Further, the data address selection signal CS51 is supplied from the coprocessor 30 to the CPU 10 via the data address selection signal supply line CSC51. Further, the write data selection signal CS52 is supplied from the coprocessor 30 to the CPU 10 via the write data selection signal supply line CSC52.

  The address selection circuit MUX_DT selects one of the data addresses DTAD and CDAD based on the data address selection signal CS51 supplied from the coprocessor 30 and supplies the selected data address to the data address bus 70. The write data selection circuit MUX_WD selects one of the write data WDA1 and WDA2 based on the write data selection signal CS52 supplied from the coprocessor 30 and supplies the selected data to the write data bus 82 included in the data bus 80.

  The read data RDA1 from the coprocessor 30 and the read data RDA2 supplied via the read data bus 84 included in the data bus 80 are supplied to the read data selection circuit MUX_RD. Further, the read data selection signal CS52 is supplied from the coprocessor 30 to the CPU 10 via the read data selection signal supply line CSC52.

  The read data selection circuit MUX_RD selects one of the read data RDA1 and RDA2 based on the read data selection signal CS53 supplied from the coprocessor 30 and supplies the selected data to the read data bus 82.

  The coprocessor 30 can supply the data address selection signal CS51, the write data selection signal CS52, and the read data selection signal CS53 to the CPU 10 with one clock of the operation clock of the CPU 10. Further, the data address selection signal CS51, the write data selection signal CS52, and the read data selection signal CS53 may be generated inside the CPU 10.

  With such a configuration, it is possible to specify an address and data for data reading or writing performed by the CPU 10 on the coprocessor 30 side.

  The CPU 10 and the coprocessor 30 operate based on the same clock CLK, but are not limited to this. Further, in the CPU 10, any of the above-described components may be omitted.

3. Command definition and command example 3.1. Instruction Definition FIG. 8 is a diagram illustrating an example of the definition of the instruction code 22. The instruction code 22 includes, for example, a coprocessor enable bit CEN, a coprocessor code CCD, and a CPU opcode OPCD. The coprocessor enable bit CEN indicates whether the coprocessor 30 is enabled or disabled, the coprocessor code CCD indicates an instruction for the coprocessor 30, and the CPU opcode OPCD indicates the opcode of the CPU 10.

  The instruction code 22 has a length of, for example, 32 bits. For example, a 1-bit coprocessor enable bit CEN is set in the MSB (for example, the 31st bit). For example, a 7-bit CPU opcode OPCD is set in the 26th to 20th bits. If the coprocessor enable bit CEN is 1, for example, the operation of the coprocessor 30 is set to enable, and if the coprocessor enable bit CEN is 0, the operation of the coprocessor 30 is set to disable, for example. In the instruction code 22, the remaining 20 bits from the 19th bit to the LSB (0th bit) are appropriately used by the CPU opcode OPCD.

  For example, when the addition instruction add is set in the CPU opcode OPCD, as shown in FIG. 8, the 4th bit of the 19th to 16th bits and the 4th bit of the 15th to 12th bits are, for example, the register address src1 , Src2, and 12 bits from the 11th bit to the 0th bit are used for the direct data imm12.

  The coprocessor 30 performs arithmetic processing based on the coprocessor code CCD.

  Note that the above-described configuration example of the instruction code 22 is merely an example, and other instruction definitions are possible.

3.2. Loop Processing Next, an example in which the coprocessor 30 performs loop processing will be described.

  FIG. 9 is a configuration example of the coprocessor 30 that performs loop processing. The coprocessor 30 includes an arithmetic processing unit 32. The arithmetic processing unit 32 includes a count value end 32-1, a comparator 32-2, a control unit 32-3, a number counter 32-4, a subtractor 32-5, and a count value start 32-6, but is not limited thereto. . For example, the subtractor 32-5 may be an adder. Further, the count value end 32-1 and the count value start 32-6 are constituted by registers in which a given value is stored, for example. For example, the count value end 32-1 stores a value corresponding to the end of the loop process, and the count value start 32-6 stores a value corresponding to the start of the loop process.

  The arithmetic processing unit 32 receives the count value PC from the CPU 10 side, and compares the value stored in the count value end 32-1 with the count value PC by the comparator 32-2. When the comparator 32-2 determines that the value stored in the count value end 32-1 matches the count value PC, the control unit 32-3 issues a command based on the output value of the number counter 32-4. An address selection signal CS11 is output to the CPU 10 side. Specifically, when the output value of the number counter 32-4 is not 0, the control unit 32-3 sets the instruction address selection signal CS11 to active (for example, high level) and is output from the coprocessor 30. The value (instruction address CIA) stored in the count value start 32-6 is set as a signal for selectively outputting the instruction address selection circuit MUX_ADD on the CPU 10 side. Further, the subtracter 32-5 is caused to subtract the value stored in the number counter 32-4.

  On the other hand, when the output value of the number counter 32-4 is 0, the control unit 32-3 stops the subtraction process of the subtractor 32-5 and sends the instruction address selection signal CS11 to the fetch unit 100 on the CPU 10 side. Is set to a signal that causes the instruction address selection circuit MUX_ADD to selectively output the instruction address.

  When the value stored in the count value start 32-6 is selected as the instruction address by the instruction address selection circuit MUX_ADD, the instruction address is stored in the program counter 110. On the CPU 10 side, the value stored in the program counter 110 is incremented, for example, and the corresponding instruction code 22 is sequentially processed. Then, based on the instruction address selection signal CS11 from the coprocessor 30 side, the instruction address selection circuit MUX_ADD switches the instruction address to be output. That is, when it is determined that one loop process is completed on the coprocessor 30 side, the instruction address selection circuit MUX_ADD selects the output of the count value start 39-6. As a result, the value of the count value start 32-6 is output from the instruction address selection circuit MUX_ADD, and the value of the count value start 32-6 is also stored in the program counter 110. In this way, the loop processing is started again. The number of loop processes can be performed based on the value set in the number counter 32-4.

  FIG. 10 is a timing chart showing the start state of the loop processing. In this example, for example, a value “10” is stored in the count value start 32-6 as the start address of the loop process, and a value “1C” is stored in the count value end 32-1 as the end address of the loop process. Yes. Further, this example shows a configuration in which the loop processing is performed, for example, 10 times, and a value of “9” is stored in the number counter 32-4.

  At the timing indicated by A1, the value “10” is supplied from the program counter 110 to the coprocessor 30 as the count value PC. At this time, in the fetch unit 100, the count value PC is incremented by, for example, a value of “4”, and a value of “14” is supplied from the fetch unit 100 as an instruction address to the instruction address selection circuit MUX_ADD at the timing indicated by A2. Since the count value start 32-6 stores, for example, “10” as the start address of the loop processing, the instruction address selection circuit MUX_ADD is supplied with the value “10” as the instruction address CIA. At this time, since the instruction address selection signal CS11 is set to non-active, the instruction address selection circuit MUX_ADD selects the instruction address from the fetch unit 100. Therefore, a value “14” is supplied to the instruction address bus 50 as a life address.

  The above processing is repeated until the value of “1C” stored in the count value end 32-1 matches the value of the count value PC. During this time, the CPU 10 can perform processing based on the instruction code corresponding to the instruction address at that time.

  When the value of the count value PC becomes “1C” at the timing indicated by A3, the comparator 32-2 determines that the count value PC matches the value stored in the count value end 32-1, as indicated by A4. . Based on this, since the value stored in the number counter 32-4 is not “0”, the control unit 32-3 sets the instruction address selection signal CS11 to active as indicated by A5. Accordingly, the instruction address selection circuit MUX_ADD selects the instruction address CIA and supplies the value “10” stored in the count value start 32-6 to the instruction address bus 50. The program counter 110 stores the value “10” output from the instruction address selection circuit MUX_ADD at the timing indicated by A6.

  In this way, one loop process is completed, the start address of the loop process is set as the instruction dress, and the loop process is started.

  FIG. 11 shows an example of an instruction code corresponding to each instruction address. For example, by setting the count value end 32-1 and the count value start 32-6 of the coprocessor 30 to a value of “1C” and a value of “10”, respectively, as shown in FIG. 11, for example, an odd instruction, shift A loop process for repeatedly executing an instruction, a sub instruction, and a shift instruction can be performed at high speed. As indicated by A6 in FIG. 10, the interval from the end address “1C” of the loop process to the start address “10” of the next loop process is set based on the operation clock CLK of the CPU 10 as indicated by A6 in FIG. 0 clock. In other words, in the present embodiment, for example, in the loop processing as shown in FIG. 11, the end of the loop processing is determined, and a predetermined time based on the clock CLK is not required for the processing to branch based on the determination result. For this reason, loop processing can be performed at high speed.

  FIG. 12 is a timing chart showing the start of loop processing. When the value of the count value PC becomes “1C” at the timing indicated by A7, as shown in A8, the comparator 32-2 determines that the count value PC and the value stored in the count value end 32-1 match. . Based on this, the control unit 32-3 sets the instruction address selection signal CS11. At this time, since the value stored in the number counter 32-4 is “0”, the control unit 32-3 does not set the instruction address selection signal CS11 to the active signal indicated by A9, and is non-active. Set to the state of. Therefore, the instruction address selection circuit MUX_ADD does not select the instruction address CIA, but selects the instruction address supplied from the fetch unit 100. Since the count value PC at this time is a value of “1C”, the fetch unit 100 supplies the instruction address selection circuit MUX_ADD with a value of “20” obtained by incrementing a value of “4” as the instruction address. As a result, the instruction address selection circuit MUX_ADD supplies the value “20” supplied from the fetch unit 100 to the instruction address bus 50. The program counter 110 stores the value “20” output from the instruction address selection circuit MUX_ADD at the timing indicated by A11.

  As indicated by A10 in FIG. 12, the interval from when the instruction address for the CPU 10 is set to the next instruction address “20” from the loop processing end address “1C” is 0 clocks based on the operation clock CLK of the CPU 10 It is. In other words, in the present embodiment, for example, in the loop processing as shown in FIG. 11, the end of the loop processing is determined, and a predetermined time based on the clock CLK is not required for the processing to branch based on the determination result. For this reason, loop processing can be performed at high speed.

  FIG. 13 is a flowchart showing the loop processing. Processes PR1 to PR3 indicate processes on the coprocessor 30 side, and process PR4 indicates processes on the CPU 10 side. For example, the control unit 32-3 can perform the processes PR1 to PR3. When the loop process is started in response to, for example, the rising edge of the clock CLK, in the process PR1, it is determined whether or not the value of the number counter 32-6 is “0”. When the value of the number counter 32-6 is not “0”, the subsequent process PR2 is performed.

  In the process PR2, a match determination between the count value PC and the value stored in the count value end 32-1 is performed. In this determination, if it is determined that the count value PC and the value stored in the count value end 32-1 match, a subsequent process PR3 is performed.

  In the process PR3, the instruction address selection signal CS11 is set to logic “1”, for example. The instruction address selection signal CS11 set to logic “1” indicates a signal for causing the instruction address selection circuit MUX_ADD to select the instruction address CIA.

  In process PR4, the CPU 10 supplies the instruction address CIA supplied from the coprocessor 30 to the instruction address bus 50.

  In this way, the coprocessor 30 can determine the start of loop processing, the end address of loop processing, and the end of loop processing.

3.3. Saturation Processing Next, an example where the coprocessor 30 performs saturation processing will be described.

  FIG. 14 is a configuration example of the coprocessor 30 that performs saturation processing. The coprocessor 30 includes an arithmetic processing unit 33. The arithmetic processing unit 33 includes the determination unit 33-1, but is not limited thereto.

  Determination unit 33-1 receives an instruction code input from CPU 10 via instruction code input line IRC. Determination unit 33-1 receives flag data FLD1 supplied via flag data supply line FLC1. The flag data FLD1 supplied via the flag data supply line FLC1 includes a C flag.

  When the coprocessor code CCD included in the instruction code supplied to the determination unit 33-1 indicates processing by the arithmetic processing unit 33, the determination unit 33-1 determines whether or not the C flag is “0”. to decide. When the C flag is “0”, the instruction code selection signal CS12 set to be active is supplied to the CPU 10 via the instruction code selection signal supply line CSC12. In this case, the instruction code selection circuit MUX_IRC of the CPU 10 receives the instruction code selection signal CS12 set to be active, selects the instruction code IR2 supplied from the coprocessor 30, and supplies it to the fetch unit 100.

  The arithmetic processing unit 33 supplies an instruction (nop instruction) indicating that no processing is performed to the CPU 10 as an instruction code IR2 via the instruction code supply line CICC. The instruction code of the nop instruction is set to “00000000”, for example.

  Next, for example, an example in which a program composed of first and second instruction codes is executed in the order of the first and second instruction codes will be described.

  The first instruction code is set so that the coprocessor code CCD indicates the arithmetic processing unit 33, the CPU operation code OPCD is set to an add instruction, for example, the address of the register R1 is set as the register address src1, and the direct data imm12 “12345678” is set. “12345678” indicates an arbitrary value.

  The second instruction code is set so that the coprocessor code CCD indicates the arithmetic processing unit 33, the CPU operation code OPCD is set to, for example, the ld instruction, the address of the register R1 is set as the register address src1, and the direct data imm12 "FFFFFFFF" is set. Here, “FFFFFFFF” indicates, for example, the maximum value when performing saturation processing, and saturation processing (rounding processing) is performed on values exceeding this maximum value.

  On the CPU 10 side, when the first instruction code is executed, the ALU 400 performs a process of adding the value stored in the register R1 and, for example, “12345678” included in the instruction code based on the add instruction. The addition result is stored in the register R1, for example. Based on the calculation result at this time, the flag data of the flag register 410 is set. For example, when an overflow occurs by this addition process, the C flag is set to “1”. The first instruction code is input to the coprocessor 30 via the instruction code input line IRC.

  On the coprocessor 30 side, when the first instruction code is input to the coprocessor 30, the arithmetic processing unit 33 starts processing. The determination unit 33-1 determines whether the value of the C flag is “0”. When the value of the C flag is “0”, an active instruction code selection signal CS12 is supplied to the CPU 10.

  At this time, the instruction code selection circuit MUX_IRC is supplied with the second instruction code supplied via the instruction code bus 60 and the nop instruction supplied from the coprocessor 30. The instruction code selection circuit MUX_IRC supplies a nop instruction to the fetch unit 100 based on the active instruction code selection signal CS12. As a result, the nop instruction is fetched into the fetch unit 100, and as the next instruction step, the nop instruction that no processing is performed on the CPU 10 side is executed.

  On the contrary, when the value of the C flag is “1”, a non-active instruction code selection signal CS12 is supplied to the CPU 10. Based on this, the instruction code selection circuit MUX_IRC selects the second instruction code supplied via the instruction code bus 60 and supplies it to the fetch unit 100. As a result, the second instruction code is executed as the next instruction step. That is, in this case, “FFFFFFFF” is stored in the register R1 based on the ld instruction. In this way, when an overflow occurs in the operation result of the first instruction code, the operation result can be set to a given value. If no overflow has occurred, the next instruction code can be canceled.

  FIG. 15 is a timing chart showing instruction code fetching in the saturation processing of FIG. FIG. 15 shows a case where an overflow occurs in the calculation result of the ALU 400. The first instruction code (add) is supplied to the instruction code bus 60 at the timing indicated by B1, and the first instruction code (add) is fetched by the fetch unit 100 as indicated by B2.

  For example, in response to the rising edge of the next clock CLK, the second instruction code (ld) is supplied to the instruction code bus 60 at the timing indicated by B3, but the second instruction code (ld) is not fetched and B4 As shown, the nop instruction is fetched by the fetch unit 100. This is because the instruction code IR2 from the coprocessor 30 is selected by the instruction code selection circuit MUX_IRC. The first instruction code (add) is executed by the CPU 10 and input to the coprocessor 30 at the timing indicated by B5.

  When the first instruction code (add) is executed, the ALU 400 stores flag data in the flag register 410. This flag data (for example, C flag) is supplied to the coprocessor 30. When an overflow occurs in the ALU 400, the C flag is set to “0” (for example, low level) as indicated by B6. Based on the C flag, the determination unit 33-1 sets the instruction code selection signal CS12 to active (for example, high level) as indicated by B7. Based on the instruction code selection signal CS12, the instruction code selection circuit MUX_IRC selects the instruction code IR2 (nop instruction) from the coprocessor 30 and supplies it to the fetch unit 100. That is, the fetch unit 100 fetches a nop instruction as indicated by B4.

  For example, in response to the next rising edge of the clock CLK, a nop instruction is executed on the CPU 10 side, and a nop instruction is input to the coprocessor 30 as shown at B8.

  FIG. 16 is a flowchart showing the saturation process. Processes PR11 to PR13 indicate processes on the coprocessor 30 side, and process PR14 indicates processes on the CPU 10 side. For example, the control unit 33-1 can perform the processes PR1 to PR3. When saturation processing is started in response to, for example, a rising edge of the clock CLK, the processing PR11 determines whether or not the instruction code IR1 input from the CPU 10 to the coprocessor 30 is an instruction code indicating processing by the arithmetic processing unit 33. To do. For example, when the coprocessor code CCD of the instruction code IR1 is a code indicating processing by the arithmetic processing unit 33, the subsequent processing PR12 is performed.

  In the process PR12, it is determined whether or not the value of the C flag is “0”. In this determination, if it is determined that the value of the C flag is “0”, the subsequent process PR13 is performed.

  In the process PR13, the instruction code selection signal CS12 is set to logic “1”, for example. The instruction code selection signal CS12 set to logic “1” indicates a signal for causing the instruction code selection circuit MUX_IRC to select the instruction code IR2.

  In process PR14, the CPU 10 fetches a nop instruction as the instruction code IR2 supplied from the coprocessor 30.

  In this way, the coprocessor 30 can perform, for example, an overflow determination and a saturation process based on the determination result at high speed in the saturation process.

3.4. Coprocessor register data 3.4.1. Processing for Supplying to Register File FIG. 17 shows a block diagram when register data RDT1 and RDT2 of the coprocessor 30 are supplied to the CPU 10. The coprocessor 30 includes an arithmetic processing unit 34. The arithmetic processing unit 34 includes an accumulator register (ACC) 34-1 and a decoder 34-2. The accumulation register 34-1 can store, for example, 40-bit data. The instruction code IR1 is input to the arithmetic processing unit 34 from the CPU 10 via the instruction code input line IRC. The arithmetic processing unit 34 performs processing based on the instruction code IR1, and stores the result in the accumulation register 34-1, for example.

  Of the 40-bit data stored in the accumulator register 34-1, for example, lower 32 bits of data (31st to 0th bits of data) are used as the first register data RDT1 as the first register data supply line RDC1. To the register file 300 of the CPU 10. Of the 40-bit data, for example, the upper 8-bit data (39th to 32nd bit data) is used as the second register data RDT2 via the second register data supply line RDC2, and the register file of the CPU 10 is used. 300.

  The decoder 34-2 supplies the register number RNM and the register selection signals CS31 and CS32 to the register file 300 of the CPU 10 based on the instruction code IR1 input from the CPU 10. For example, by generating the register number RNM based on the instruction code IR1, the register data RDT1 of the accumulation register 34-1 can be supplied to any of the plurality of registers R0 to R15.

  Large data can be supplied to the CPU 10 at high speed using the arithmetic processing unit 34 configured in this way.

  Further, flag data FLD2 (for example, C flag) generated in the processing performed by the arithmetic processing unit 34 is supplied to the CPU 10 via the second flag data supply line FLC2. Thus, the CPU 10 can use the value of the flag register 410 with the next instruction code. Therefore, it is possible to perform processing for an overflow or the like at high speed on the result of arithmetic processing by the coprocessor 30.

  Further, the arithmetic processing unit 34 can supply the CPU 10 with a flag data write signal CS41 for controlling whether or not the flag data FLD2 is stored in the flag register 410 of the ALU 400. When flag data FLD2 is stored in flag register 410, flag data write signal CS41 is set active. The flag register 410 stores flag data FLD2 based on the flag data write signal CS41 set to be active. In this way, when the flag data FLD2 (for example, C flag) generated by the coprocessor 30 is unnecessary in the CPU 10, the coprocessor 30 can control the flag data FLD2 not to be stored in the flag register 410. It becomes.

  FIG. 18 is a timing chart of the processing shown in FIG. In the arithmetic processing unit 34, the arithmetic result by the arithmetic processing unit 34 is stored in the accumulation register 34-1. For example, the lower 32 bits of the result of the operation are stored as register data RDT1 in the lower 32 bits of the accumulation register 34-1 at the timing indicated by C1. Then, the register data RDT1 is supplied to the register file 300 of the CPU 10.

  In addition, the decoder 34-2 generates a register number RNM as indicated by C2 based on the instruction code IR1, and supplies the register number RNM to the register file 300 of the CPU 10. Further, the decoder 34-2 supplies the register file with the register selection signal CS31 set to active as indicated by C3 based on the instruction code IR1.

  Further, for example, the upper 8 bits data of the calculation result by the operation processing unit 34 is stored as register data RDT2 in the upper 8 bits of the accumulation register 34-1 at the timing indicated by C4. Then, the register data RDT2 is supplied to the register file 300 of the CPU 10.

  Further, the decoder 34-2 supplies the register file with the register selection signal CS32 set to active as indicated by C5 based on the instruction code IR1.

  The above processing is performed, and the register data RDT1 and RDT2 are stored in the register file 300 as indicated by C6 in response to, for example, the rising edge of the next clock CLK. That is, in this embodiment, for example, each register data RDT1, RDT2 and flag data FLD2 can be supplied to the CPU 10 by one clock of the operation clock CLK of the CPU 10. Therefore, the CPU 10 can use each register data RDT1, RDT2 and flag data FLD2 by executing the next instruction code. For example, processing such as saturation processing can be performed at high speed.

3.4.2. Processing for Supplying to Write Data Bus FIG. 19 shows a block diagram when register data RDT 1 and RDT 2 of the coprocessor 30 are supplied to the write data bus 82. The coprocessor 30 includes an arithmetic processing unit 36. The arithmetic processing unit 36 includes an accumulator register (ACC) 36-1, a decoder 36-2, an accumulator register data selection circuit 36-3, a data address output unit 36-4, and an adder 36-5. Note that the arithmetic processing unit 36 may be configured by omitting any of the above-described components. For example, the adder 36-5 may be a subtracter. Further, the data address output unit 36-4 may be constituted by a register, for example.

  The accumulation register 36-1 can store, for example, 40-bit data. The instruction code IR1 is input to the arithmetic processing unit 36 from the CPU 10 via the instruction code input line IRC. The arithmetic processing unit 36 performs processing based on the instruction code IR1, and stores the result in the accumulation register 36-1, for example.

  The decoder 36-2 supplies the data address selection signal CS51 and the write data selection signal CS52 to the register file 300 of the CPU 10 based on the instruction code IR1 input from the CPU 10. The decoder 36-2 supplies an accumulator register data selection signal CS54 to the accumulator register data selection circuit 36-3 based on, for example, the instruction code IR1 input from the CPU 10.

  Of the 40-bit data stored in the accumulator register 36-1, for example, lower 32 bits of data (31st to 0th bits) and upper 8 bits of data (39th to 32nd bits) Data) is supplied to the accumulation register data selection circuit 36-3. The accumulation register data selection circuit 36-3 selects either the lower 32 bits data or the upper 8 bits data based on the accumulation register data selection signal CS54, and writes the write data WDA1 via the write data supply line WDAC. To the CPU 10.

  The data address output unit 36-4 supplies the data address DTAD to the CPU 10 via the data address supply line DAC. The data address output unit 36-4 is constituted by a register, for example, and the output is added by the adder 36-5. For example, the adder 36-5 adds a given value (for example, a value of “4”) to the output value of the data address output unit 36-4, and sends the addition result to the data address output unit 36-4. Output.

  Further, the data address output unit 36-4 stores the result of the addition processing by the adder 36-5, for example, according to the rising edge of the clock CLK. That is, the data address output unit 36-4 supplies the data address DTAD incremented one after another according to, for example, the rising edge of the clock CLK to the data address selection circuit MUX_DT of the CPU 10.

  FIG. 20 is a timing chart of the process shown in FIG. The instruction code IR1 is supplied to the coprocessor 30 at the timing indicated by D1. Further, in the arithmetic processing unit 36, the arithmetic result by the arithmetic processing unit 36 is stored in the accumulation register 36-1. For example, lower 32 bits data or upper 8 bits data of the calculation result is selected by the accumulator register data selection circuit 36-3 and supplied to the CPU 10 as write data WDA1 as indicated by D2.

  When the write data WDA1 supplied from the coprocessor 30 is supplied to the write data bus 82, the data address selection signal CS51 and the write data selection signal CS52 supplied from the decoder 36-2 are active as indicated by D3. (For example, high level).

  Further, the data address output unit 36-4 outputs a data address DTAD as indicated by D4, and outputs a data address DTAD in which, for example, a value of “4” is incremented at the timing indicated by D5.

  Further, the data address selection circuit MUX_DT of the CPU 10 supplies the data address DTAD to the data address bus 70 as indicated by D6 based on the data address selection signal CS51. At this time, the data address DTAD supplied to the data address bus 70 is the data address DTAD indicated by D4.

  The write data selection circuit MUX_WD of the CPU 10 supplies the write data WDA1 to the write data bus 82 as shown at D7 based on the write data selection signal CS52.

  Thus, after the instruction code IR1 is input as indicated by D1, the data address DTAD and the write data WDA1 can be supplied to the data address bus 70 and the write data bus 82 at the timing indicated by D6 and D7. That is, the data address DTAD and the write data WDA1 generated by the coprocessor 30 can be supplied to the data address bus 70 and the write data bus 82 at high speed.

  For example, each time a predetermined address in the memory 20 is incremented, a process for storing the processing result of the coprocessor 30 at that time can be processed at high speed.

  FIG. 21 is a flowchart regarding the processing shown in FIG. Processes PR21 to PR25 indicate processes on the coprocessor 30 side. When the processing is started in response to, for example, a rising edge of the clock CLK, the processing PR21 determines whether or not the instruction code IR1 input from the CPU 10 to the coprocessor 30 is an instruction code indicating processing by the arithmetic processing unit 36. . For example, when the coprocessor code CCD of the instruction code IR1 is a code indicating processing by the arithmetic processing unit 36, subsequent processes PR22 and PR23 are performed.

  In the process PR22, it is determined whether or not the value of the direct data imm12 included in the instruction code IR1 is “1”, for example. When the value of the direct data imm12 is “1”, the subsequent process PR24 is performed. When the value of the direct data imm12 is a value other than “1”, the subsequent process 25 is performed. .

  In the process PR23, the data address DTAD is output from the data address output unit 36-4. Further, the data address DTAD is incremented by a given value (for example, a value of “4”) in accordance with, for example, the rising edge of the next clock CLK.

  In the process PR24, the arithmetic processing unit 36 outputs, for example, upper 8 bits of data stored in the accumulation register 36-1 to the CPU 10. At the time of the output, the arithmetic processing unit 36 sets the upper 8 bits data stored in the accumulation register 36-1 as the lower 8 bits of the write data WDA1 composed of, for example, 32-bit data. Further, the arithmetic processing unit 36 sets the remaining upper 24 bits of the write data WDA1 to a value of “0”. The write data WDA1 set in this way is supplied to the CPU 10.

  In the process PR25, the arithmetic processing unit 36 supplies, for example, lower 32 bits of data stored in the accumulation register 36-1 to the CPU 10 as write data WDA1.

  In the present embodiment, either the upper 8-bit data or the lower 32-bit data stored in the accumulation register 36-1 can be selected and supplied to the CPU 10 by the process PR22. The selection can be performed based on the data value set in the direct data imm12, for example. For example, when the value “1” is set in the direct data imm12, it can be defined to use the upper 8 bits of the data stored in the accumulation register 36-1. In this way, a part of the data of the arithmetic processing unit 36 can be selected based on the instruction code IR1 and supplied to the CPU 10 as write data supplied to the write data bus 82.

4). Comparison with Comparative Example FIG. 22 is a diagram illustrating a connection relationship between the CPU 11 and the coprocessor 31 of the integrated circuit device 2000 which is a comparative example according to the present embodiment. In the comparative example, for example, a 32-bit instruction code 22 (code) output from the fetch unit 100 is supplied to the coprocessor 31 via the instruction code supply IRC. The register data src2 output from the output RQ2 of the register file 300 is supplied to the coprocessor 31 via the second register file supply line RFC2. For example, a value stored in any one of the plurality of registers R0 to R15 of the register file 300 can be supplied to the coprocessor 31. The coprocessor 31 can supply, for example, 32-bit register data RDT1 to the CPU 11 using the coprocessor data input line RDC1.

  In the comparative example, when data is supplied from the coprocessor 31 to the CPU 11, for example, it is necessary to go through the register file 300, for example. In this case, at least processing to be stored in the register file 300 and processing to read the stored data are required, and the processing speed is lost accordingly. Further, when the size of the data generated by the coprocessor 31 is large or when there are a plurality of types of data, it is necessary to supply the data to the register file 300 in a plurality of times. In this case as well, processing speed is lost.

  Further, when data generated by the coprocessor 31 is supplied to the write data bus 82, it is necessary to pass through the register file 300. Further, when the data address generated by the coprocessor 31 is supplied to the data address bus 70, it is necessary to pass through the register address 300. In these cases as well, a plurality of instruction processes are required, resulting in a loss of processing speed.

  On the other hand, in the present embodiment, as described above, various data and the like from the coprocessor 30 are supplied from the supply lines IRC, PCC, CIAC, CICC, CSC11, CSC12, RDC1, CSC31, RNC, RDC2, CSC32, FLC2, The data is supplied to the CPU 10 via the CSC 41, DAC, CSC 51, WDAC, CSC 52, CSC 53, RDAC, and the like. Thereby, in the present embodiment, data or the like to be supplied from the coprocessor 30 to the CPU 10 can be supplied to the CPU 10 with one clock of the operation clock of the CPU 10. That is, the loss of processing speed, which is a problem of the comparative example, can be reduced in this embodiment. Furthermore, in the present embodiment, the addition of complex logic circuit blocks in terms of hardware configuration is small compared to the comparative example. For example, several selection circuits are provided, but an increase in hardware scale can be minimized. Therefore, high-speed processing can be realized with a small circuit scale as compared with the comparative example.

  For example, when the loop process shown in FIG. 9 is performed in the comparative example, a plurality of processes such as a process for determining a branch and a process for determining the end of the loop process are frequently required. This reduces the processing speed of the CPU 11. The decrease in the speed becomes more remarkable with an increase in the number of loop processes and an increase in the number of instruction codes executed in one loop process. That is, in the comparative example, in order to perform the loop processing at a high speed, it is necessary to increase the operation clock of the CPU 11 or to separately provide hardware capable of executing a dedicated instruction.

  On the other hand, in the present embodiment, the coprocessor 30 determines whether the loop processing is completed as described above, and the result can be supplied to the CPU 10 without using the register file 300. For this reason, the processing time required in the comparative example can be significantly reduced, and high-speed loop processing can be performed as compared with the comparative example.

  For example, when the saturation process as shown in FIG. 14 is performed in the comparative example, a process for determining the C flag and a process for changing the calculation result of the ALU 400 to a predetermined value based on the determination result are required. At this time, in the comparative example, a process of acquiring flag data from the flag register 410 and a process of acquiring the calculation result of the ALU 400 are further required. For this reason, a plurality of processes are required, and processing speed is lost.

  On the other hand, in the present embodiment, as described above, the coprocessor 30 can switch the instruction code fetched by the fetch unit 100 of the CPU 10 based on the flag data FLD1 of the CPU 10. Therefore, the integrated circuit device 1000 capable of performing saturation processing at a higher speed than in the comparative example can be realized with a simple circuit configuration as shown in FIG.

  Also, for example, when the process of supplying register data having a long bit length to the CPU as shown in FIG. 17 is performed in the comparative example, the data needs to be divided into a plurality of parts and supplied to the register file 300 in a plurality of times. . For this reason, it takes several clocks of processing time based on the operation clock of the CPU 11 to supply the register data.

  On the other hand, in the present embodiment, since the register data supply line RDC2 is provided in addition to the register data supply line RDC1, the register data RDT1 and RDT2 are supplied to the CPU 10 with one clock of the operation clock CLK of the CPU 10. Can do. That is, the arithmetic processing result of the coprocessor 30 can be supplied to the CPU 10 at a higher speed than in the comparative example. Furthermore, the flag data FLD2 based on the calculation processing result of the coprocessor 30 can be simultaneously supplied to the PCU 10, and the CPU 10 can immediately perform the processing based on the flag data FLD2.

  For example, when the process of supplying the write data from the coprocessor to the write data bus as shown in FIG. 19 is performed in the comparative example, it is necessary to pass through the register file 300. For this reason, the write data from the coprocessor 31 is temporarily stored in the register file 300 and the stored write data is supplied to the write data bus 82. At this time, since several instructions are executed on the CPU 11 side, it takes time for the process.

  On the other hand, in this embodiment, since the write data supply line WDAC and the data address supply line DAC are provided, the write data bus 82 and the data address bus 70 are supplied with one clock of the operation clock CLK of the CPU 10. Can do. Therefore, in the present embodiment, for example, write data can be supplied to the write data bus 82 at a higher speed than in the comparative example. Further, since the write data selection circuit MUX_WD and the data address selection circuit MUX_DT are provided on the CPU 10 side, the write data and the data address are based on the data address selection signal CS51 and the write data selection signal CS52 supplied from the coprocessor 30. Can be switched. For this reason, in the comparative example, processing that takes time (for example, the processing in FIG. 19) can be performed at a higher speed than in the comparative example.

  The coprocessor 30 operates at the same clock frequency as the CPU 10, but is not limited to this.

5. Modified Example FIG. 23 shows a configuration of a modified example according to the present embodiment.

  The integrated circuit device 1000 may further include a direct data supply line IMC for supplying the direct data output from the direct data generation unit 200 to the coprocessor 30. In addition, the integrated circuit device 1000 supplies the output of the first and second register selection circuits 310 and 320 (first to nth register selection circuits in a broad sense) of the register file 300 to the coprocessor 30. 1 and second register file supply lines RFC1 and RFC2 (first to nth register file supply lines in a broad sense) and a fixed register for supplying the output of a register set as a fixed register to the coprocessor 30 A data supply line RFC3 may be further included. The integrated circuit device 1000 may further include an ALU output supply line ALC for supplying the arithmetic processing result of the ALU 400 to the coprocessor 30. Further, the integrated circuit device 1000 sends a load data supply line LDC for supplying data read from, for example, the memory 20 by the load store unit 500 to the coprocessor 30 and a control signal from the decode control unit 600 to the coprocessor 30. A control signal supply line CSC for supply may be further included.

  Note that the integrated circuit device 1000 is not limited to the above configuration. For example, the CPU 10 may be configured to omit the direct data supply line IMC, the first and second register file supply lines RFC1 and RFC2, the fixed register data supply line RFC3, and the like. The coprocessor 30 outputs the result of the coprocessor operation processing to the CPU 10 via the coprocessor data input line RDC1, but the present invention is not limited to this.

  Further, for example, one end of the direct data supply line IMC may be connected to the direct value generating unit 200. The direct value generation unit 200 can be connected to the coprocessor 30 via the direct data supply line IMC. In this case, the direct value generation unit 200 can supply the generated direct data (for example, 32-bit direct data) to the coprocessor 30 via the direct data supply line IMC.

  For example, one end of the register file supply line RFC1 may be connected to the output RQ1 of the first register selection circuit 310. The output RQ1 of the first register selection circuit 310 of the register file 300 can be connected to the coprocessor 30 via the first register file supply line RFC1. In this case, the register file 300 can supply the value output from the output RQ1 of the first register selection circuit 310 to the coprocessor 30.

  For example, one end of an ALU output supply line ALC may be connected to the ALU output AQ. The ALU 400 can be connected to the coprocessor 30 via the ALU output supply line ALC. In this case, the output of the ALU 400 (for example, the calculation processing result) can be supplied to the coprocessor 30.

  Further, for example, one end of a load data supply line LDC may be connected to the load data output LDD of the load store unit 500. The load store unit 500 can be connected to the coprocessor 30 via the load data supply line LDC. In this case, the output (for example, data read from the memory) of the load store unit 500 can be supplied to the coprocessor 30.

  In the modification according to the present embodiment configured as described above, data or the like to be supplied to the coprocessor 30 can be supplied to the coprocessor 30 with one clock of the operation clock of the CPU 10. That is, the processing speed loss can be reduced as compared with the comparative example. Furthermore, in the modified example, it is not necessary to add a complicated logic circuit block in terms of hardware configuration to the comparative example, and therefore, high-speed processing can be realized with a small circuit scale as compared with the comparative example.

  Further, in the modification, the direct data supply line IMC and the first and second register file supply lines RFC1 and RFC2 are connected to the coprocessor 30. Therefore, the CPU 10 can supply the data imm, src1, and src2 to the coprocessor 30 with one clock of the operation clock of the CPU 10. Thereby, complicated product-sum operation processing can be performed at a higher speed than the comparative example.

  Further, in the modification, the ALU output supply line ALC and the flag data supply line FLC1 are connected to the coprocessor 30. Therefore, the CPU 10 can supply each data alu and C flag data to the coprocessor 30 with one clock of the operation clock of the CPU 10. Further, when the value of the arithmetic processing result alu of the ALU 400 is determined, the arithmetic processing result alu can be supplied to the coprocessor 30 immediately. Thereby, for example, saturation processing can be performed at a higher speed than in the comparative example.

  In the modification, an instruction code input line IRC and a load data supply line LDC are connected to the coprocessor 30. Therefore, the CPU 10 can supply the data load and imm12 to the coprocessor 30 with one clock of the operation clock of the CPU 10. Thereby, for example, complex product-sum processing can be performed at a higher speed than in the comparative example.

  As described above, the integrated circuit device 1000 according to this embodiment can supply necessary data to the coprocessor 30 in one clock without adding a complicated logic circuit block as compared with the comparative example. Processing can be performed at a higher speed than the comparative example.

  The coprocessor 30 operates at the same clock frequency as the CPU 10, but is not limited to this.

  As described above, the embodiments of the present invention have been described in detail. However, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. . Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term anywhere in the specification or the drawings.

1 is a block diagram showing an integrated circuit device according to an embodiment. The block diagram which shows CPU which concerns on this embodiment. The figure which shows the connection of CPU and a coprocessor which concerns on this embodiment. The block diagram which shows the connection of the fetch part which concerns on this embodiment, and a coprocessor. The block diagram which shows the connection of the register file which concerns on this embodiment, and a coprocessor. The block diagram which shows the connection of ALU and a coprocessor concerning this embodiment. The block diagram which shows the connection of the load store part and coprocessor which concern on this embodiment. 3 is a configuration example of an instruction code according to the present embodiment. The figure which shows the loop process in the integrated circuit device which concerns on this embodiment. 11 is a timing chart at the start of the loop processing of FIG. 11 is a correspondence example of instruction codes in the loop processing of FIG. 11 is a timing chart at the end of the loop processing of FIG. 11 is a flowchart showing loop processing of FIG. The figure which shows the saturation process of the integrated circuit device which concerns on this embodiment. The timing chart which shows the saturation processing of FIG. The flowchart which shows the saturation process of FIG. The figure which shows supply of the register data of the integrated circuit device which concerns on this embodiment. The timing chart which shows supply of the register data of FIG. FIG. 4 is a diagram showing supply of write data and data addresses in the integrated circuit device according to the embodiment. FIG. 20 is a timing chart showing supply of write data and data addresses in FIG. 19. FIG. The flowchart which shows supply of the write data of FIG. 19, and a data address. The figure which shows the comparative example which concerns on this embodiment. The figure which shows the modification concerning this embodiment.

Explanation of symbols

10 CPU, 20 memory, 22 instruction code, 24 data, 30 coprocessor, 50 instruction address, 60 instruction code bus, 70 data address bus,
80 data bus, 82 write data bus, 84 read data bus,
100 fetch unit, 110 program counter, 200 direct value generation unit,
300 register file, 310 first register selection circuit,
320 second register selection circuit, 400 ALU, 410 flag register,
500 load store section, 600 decode control section, CDAD data address,
CIA instruction address, CIAC instruction address supply line, CICC instruction code supply line, CSC11 instruction address selection signal supply line, CSC12 instruction code selection signal supply line,
CSC31 first register data selection signal supply line,
CSC32 second register data selection signal supply line;
CSC41 flag data selection signal, CSC51 data address selection signal supply line,
CSC52 write data selection signal supply line, CSC53 read data selection signal supply line, CS11 instruction address selection signal, CS12 instruction code selection signal,
CS31 first register data selection signal, CS32 second register data selection signal, CS41 flag data selection signal, CS51 data address selection signal,
CS52 write data selection signal, CS53 read data selection signal,
DAC data address supply line, DTAD data address,
FLC1 first flag data supply line, FLC2 second flag data supply line,
FLD1 first flag data, FLD2 second flag data,
MUX_ADD instruction address selection circuit, MUX_DT data address selection circuit,
MUX_FLG flag data selection circuit, MUX_IRC instruction code selection circuit,
MUX_RD read data selection circuit,
MUX_RG1 first register data selection circuit,
MUX_RG2 second register data selection circuit,
MUX_RNM register number selection circuit, MUX_WD write data selection circuit,
IR1, IR2 instruction code, PCC count value supply line,
RDAC read data supply line, RDA1 read data,
RDC1 first register data supply line, RDC2 second register data supply line,
RDT1 first register data, RDT2 second register data,
RNC register number supply line, RNM register number, R0 to R15 Multiple registers, WDAC write data supply line, WDA1, WDA2 write data

Claims (7)

An integrated circuit device including a CPU that executes a given process based on an instruction code,
A data address supply line for supplying a data address output from the coprocessor to the CPU;
The CPU
A load store unit for writing data to the memory by supplying a data address to the memory via the data address bus and supplying write data via the write data bus;
A data address selection circuit that receives a data address supplied via the data address supply line and a data address output from the load store unit, and supplies any one of the data addresses to the data address bus;
An integrated circuit device comprising: In claim 1,
A data address selection signal supply line for supplying a data address selection signal from the coprocessor to the data address selection circuit;
The data address selection circuit includes:
Based on the data address selection signal, one of a data address supplied via the data address supply line and a data address output from the load store unit is supplied to the data address bus. An integrated circuit device. An integrated circuit device including a CPU that executes a given process based on an instruction code,
A write data supply line for supplying the CPU with write data output from the coprocessor;
The CPU
A load store unit for writing data to the memory by supplying a data address to the memory via the data address bus and supplying write data via the write data bus;
A write data selection circuit that receives write data supplied via the write data supply line and write data output from the load store unit, and supplies any one of the write data to the write data bus;
An integrated circuit device comprising: In claim 3,
A write data selection signal supply line for supplying a write data selection signal from the coprocessor to the write data selection circuit;
The write data selection circuit includes:
Based on the write data selection signal, one of the write data supplied via the write data supply line and the write data output from the load store unit is supplied to the write data bus. An integrated circuit device. An integrated circuit device including a CPU that executes a given process based on an instruction code,
A read data supply line for supplying read data output from the coprocessor to the CPU;
The CPU
A load store unit for reading data from the memory by supplying a data address to the memory via the data address bus and receiving read data via the read data bus;
A read data selection circuit which receives the read data supplied from the read data supply line and the read data supplied from the read data bus, and supplies any one of the read data to the load store unit;
Only including,
The integrated circuit device further includes a read data selection signal supply line for supplying a read data selection signal from the coprocessor to a read data selection circuit,
The read data selection circuit supplies any one of the coprocessor read data and the CPU read data to the load store unit based on the read data selection signal. . In any one of Claims 1 thru | or 5 ,
The CPU includes an ALU that performs arithmetic processing based on the instruction code,
The CPU
A first flag data supply line for supplying first flag data based on the arithmetic processing result of the ALU to the coprocessor;
A second flag data supply line for supplying second flag data based on the arithmetic processing result of the coprocessor to the ALU;
Including
The ALU is
A flag register for storing the first or second flag data;
A flag data selection circuit that receives the first and second flag data from the first and second flag data supply lines and supplies either of the first and second flag data to the flag register;
An integrated circuit device comprising: In claim 6 ,
The CPU
A flag data selection signal supply line for supplying a flag data selection signal from the coprocessor to the ALU;
The flag data selection circuit of the ALU selects one of the first and second flag data as the flag register based on the flag data selection signal supplied via the flag data selection signal supply line. An integrated circuit device for outputting.

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