JP2946953B2 - Information transfer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information transfer circuit, and more particularly, to an information transfer circuit for an operation signal selected by an ALM signal indicating normality or failure of an information system.

[0002]

2. Description of the Related Art A conventional information transfer circuit includes a 0-system fault detecting circuit 1 for outputting a 0-system ALM signal 11a as shown in FIG.
a, a 1-system failure detection circuit 2a that outputs a 1-system ALM signal 12a, a 0-system ALM signal 11a, and a 1-system ALM signal 1.
2a, a system selection circuit 3a for selecting a system to be operated and outputting an operation system signal 13a, and a system ALM signal 11a, a system ALM signal 12a, an operation system signal 13a, and another information signal 14a in a predetermined frame format. A multiplexing circuit 5a that multiplexes the time slots and outputs the multiplexed data as a transfer signal 15a.

Next, the operation of the conventional example will be described. The system selection circuit 3a selects the normal system of the 0 system or the 1 system as the active system based on the 0-system ALM signal 11a from the 0-system failure detection circuit 1a and the 1-system ALM signal 12a from the 1-system failure detection circuit 2a, and operates the system. A system signal 13a is output. The operation system signal 13a is basically a signal indicating a normal system, and is a signal indicating either the 0 system or the 1 system even in the case of both systems normal or both systems ALM.

Next, a 0-system ALM signal 11a and a 1-system ALM1
2a and the operation signal 13a are input to the multiplexing circuit 5a, where they are multiplexed with other information signals 14a into a predetermined time slot corresponding to the frame format of the transfer signal, and output as a transfer signal 15a. You.

As shown in FIG. 3, when the system 0 or 1 is in a normal state (no ALM) and the operating system signal 13a indicates the system 0, a failure occurs in the system 0 in the first half of the second week, and the system 0 is failed. A
Assuming that the LM signal 11a indicates the ALM in the 0 system, the active system signal 13a also changes the active system from the 0 system to the 1 system in the first half of the second week.

In the transfer signal 15a, the time slot A for the 0-system ALM signal becomes NOR (normal) → ALM → ALM when viewed through the first to third cycles, and the time slot C for the 1-system ALM signal becomes the 0-> 1 system. → The transfer signal 15a operates with the 1 system.

[0007]

In this conventional information transfer circuit, the time slot for the 0-system ALM signal or the time slot for the 1-system ALM signal and the time slot for the working system signal in one cycle of the transfer signal are set. If a state is determined based on a transfer signal when a 0-system failure or a 1-system failure such as switching of the active system occurs, the active-system signal becomes 0-system or 1-system ALM.
Since the signal changes one frame before, the concept of selecting a system due to a system 0 or system 1 fault (ALM), which is a basic rule of the active system selection circuit, is not maintained, and the system selection circuit malfunctions or the system 0 or 1 There is a problem that the fault detection circuit of the system malfunctions and makes an erroneous determination.

[0008]

An information transfer circuit according to the present invention comprises: a 0-system fault detecting circuit for outputting a 0-system ALM signal indicating the detected state of the first information system; A system failure detection circuit for outputting a system ALM signal indicating a state, a system selection circuit for selecting an information system operated by the system ALM signal and the system ALM signal and outputting an operation system signal, and the operation system signal Register for delaying the transmission signal by one cycle of the transfer signal, and multiplexing the operation system signal of the shift register output, the 0-system ALM signal, the 1-system ALM signal and other information signals into a time slot of a predetermined frame format and transferring And a multiplexing circuit for outputting as a signal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention.

The present invention relates to a 0-system fault detecting circuit 1 for outputting a 0-system ALM signal 11 indicating the detected state of a first information system.
And a 1-system fault detection circuit 2 that outputs a 1-system ALM signal 12 indicating the detected state of the second information system, and an information system to be operated based on the 0-system ALM signal 11 and the 1-system ALM signal 12 to select the operating system. A system selection circuit 3 that outputs the signal 13, a shift register 4 that delays the operation signal 13 by one cycle of the transfer signal 15, an operation signal 13 from the shift register 4,
The multiplexing circuit 5 multiplexes the 0-system ALM signal 11, the 1-system ALM signal 12, and other information signals 14 into time slots of a predetermined frame format and outputs the multiplexed signal as a transfer signal 15.

Next, the operation of this embodiment will be described. 0
System 0 is faulty or normal 0 system A by system fault detection circuit 1
The LM signal 11 is output, and the 1-system fault detection circuit 2 outputs 1
The 1-system ALM signal 12 in which the system is faulty or normal is output. In accordance with the 0-system ALM signal 11 and the 1-system ALM signal 12, the system selection circuit 3 changes the normal system into the active system according to the selection algorithm, and outputs the selected active system signal 13.

Next, the operation system signal 13 is input to the shift register 4, where it is delayed by one cycle of the transfer signal. Then, the operation system signal output from the shift register 4 and the 0 system ALM
Signal 11, 1-system ALM signal 12, and other information signal 14
Is multiplexed into a corresponding time slot of the frame format of the transfer signal 15 and is output as the transfer signal 15.
Depending on the frame format of the transfer signal 15, when the time slot for the active signal and the time slot for the 0-system or 1-system ALM signal precede and follow within one cycle, the relevant time slots are dispersed into multiple frames by a multi-phrase configuration. However, the same operation is performed by treating the transfer speed of the information signal as one cycle.

[0013]

As described above, the information transfer circuit of the present invention includes the shift register for delaying the operation signal by one period of the transfer signal, and provides the 0-system or 1-system fault information and the operation information by the transfer signal. Can be determined as a pair within one cycle of the transfer signal, so that the same determination processing as that of the source can be performed, and the erroneous determination can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a conventional information transfer circuit.

FIG. 3 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 Reference Signs List 1 0 system failure detection circuit 2 1 system failure detection circuit 3 system selection circuit 4 shift register 5 multiplexing circuit 11 0 system ALM signal 12 1 system ALM signal 13 operation system signal 14 other information signal 15 transfer signal

Claims (1)

(57) [Claims] 1. A 0-system fault detection circuit for outputting a 0-system ALM signal indicating the detected state of the first information system, and a 1-system for outputting a 1-system ALM signal indicating the detected state of the second information system. A failure detection circuit, a system selection circuit that selects an information system operated by the 0-system ALM signal and the 1-system ALM signal and outputs an operation system signal, and a shift register that delays the operation system signal by one cycle of a transfer signal. A multiplexing circuit for multiplexing the operation system signal output from the shift register, the 0-system ALM signal, the 1-system ALM signal, and other information signals into a time slot having a predetermined frame format and outputting the multiplexed signal as a transfer signal. Characteristic information transfer circuit.