JP2941940B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory device (hereinafter, semiconductor memory) such as a dynamic RAM (random access memory), a static RAM, and a ROM (read only memory). In particular, in addition to a main memory area having ordinary memory cells, a redundant memory area having, for example, a redundant memory cell for providing redundancy and a redundant circuit for enabling the redundant memory area are provided. The present invention relates to a semiconductor memory device employing a redundant circuit system using redundant memory cells in a redundant memory area instead of defective memory cells in a main memory area.

(Prior Art) In recent years, semiconductor memory devices tend to be highly integrated and have a large capacity, and it is difficult to manufacture completely non-defective products at a high yield even with advanced technology. For this reason, in recent semiconductor memory devices, for example, 16M5DRAM, in addition to a main memory region having a normal memory cell, a redundant memory region for providing redundancy is provided, so that a part of the main memory region is defective. Even if a memory cell exists, by programming the address of the defective memory cell into a fuse in the redundant circuit pattern, the defective memory cell in the main memory area is not read / written, and The redundant memory cells can be read and written.

FIG. 2 is a block diagram schematically showing a configuration example of a semiconductor memory device employing a conventional redundant circuit system. FIG. 3 schematically shows an example of a circuit configuration of the redundant circuit in FIG. 2. For example, FIG. 3 is a circuit diagram showing a case where an address is specified from a column direction or a row direction.
FIG. 4 is a diagram showing an example of a layout arrangement of the redundant circuit of FIG.

This semiconductor memory device is, for example, a 16M5 DRAM, and includes, for example, a main memory area 1 in which a large number of memory cells are arranged in a matrix.

An address buffer circuit 2 is connected to the main memory area 1, and an address decoder 3 is provided between the main memory area 1 and the address buffer circuit 2. The address buffer circuit 2 receives the clock signal C1 via the address input line.
A circuit that inputs addresses A1IN to A10IN in synchronization with and outputs address signals A1a to A10a and inverted address signals (hereinafter simply referred to as address signals) A1b to A10b via address signal lines. It is configured. The address decoder 3 includes address signals A1a to A10
a, A1b to A10b are decoded, and the address of the memory cell in the main memory area 1 is selected.
And a column address decoder 3b. further,
A read / write input / output circuit (hereinafter referred to as an R / W input / output circuit) 4 for inputting / outputting write data DIN and read data DOUT is connected to the main memory area 1.

Near the main memory area 1, a redundant memory area 5 in which a plurality of redundant memory cells are arranged is provided. A redundant address decoder 6 is connected to the redundant memory area 5, and a redundant circuit 10 is provided between the address buffer circuit 2 and the redundant address decoder 6.

The redundant address decoder 6 outputs a redundant memory activation signal NR
Activated based on DB, for example, address signals A8a to A10b
To select a redundant memory cell in the redundant memory area 5, and is composed of a redundant column address decoder 6a and a redundant row address decoder 6b. The redundant circuit 10 is a circuit for accessing the redundant memory area 5 instead of the main memory area 1 based on the address signals A1a to A10b, and includes a plurality of redundant memory selection circuits 11-n (for example, n = 1 to 8,
Hereinafter, the same applies).

Each of the redundant memory selection circuits 11-n includes address signals A1a to A1a.
10b are circuits for outputting redundant signals NRDB0 to NRDB7, respectively, based on a redundant selection circuit 12-n and a fuse circuit 13-n.
n.

Each of the redundancy selection circuits 12-n includes, for example, address signals A8a to A8a.
Three Ns each having three of 10b as gate inputs
It is composed of 12-nA channel type MOSFET (hereinafter referred to as NMOSFET). Each of the three NMOSFETs 12-nA has a source connected to the ground potential and a drain connected to P
It is connected to a precharge circuit 14-n which includes a channel type MOSFET (hereinafter referred to as a PMOSFET) and an inverter and has a precharge function synchronized with the clock signal CK2.

Each fuse circuit 13-n has, for example, an address signal A1a to A1A.
14 NMOSFETs 13-nA, each having a gate input 7b and a source connected to ground potential, and the NMOSFET 13
It has 14 fuses 13-nB each having one end connected to the drain of -nA. Here, each fuse circuit 13−
The fourteen fuses 13-nB included in n are blown in a predetermined combination in order to program an address of a defective memory cell in the main memory area 1 in advance.

Further, in each of the redundant memory selection circuits 11-n, the drains of the three NMOSFETs 12-nA of the redundancy selection circuit 12-n and the other ends of the fourteen fuses 13-nB of the fuse circuit 13-n are common. Each common connection is connected to the precharge circuit 12-nB, and the clock signal CK2
, And is precharged in synchronization with. On the output side of each commonly connected redundant memory selection circuit 11-n,
The redundant address circuit 15 is connected via eight signal lines.

The redundant address circuit 15 includes, for example, redundant signals NRDB0 to NRDB7.
And a redundant memory activating signal NR for inactivating the address decoder 3 and activating the redundant address decoder 6.
DB, and outputs the redundant memory activation signal NRDB to the row address decoder 3a and the column address decoder 3b of the address decoder 3 and the redundant column address decoder 6a and the redundant row address decoder 6b of the redundant address decoder 6. This is a circuit, for example, composed of an 8-input OR gate 15-1.

 Next, the operation will be described.

For example, the fuse circuit 13- of the redundant memory selection circuit 11-1
Of the 14 fuses 13-1B provided in the circuit 1, each of which is connected to the drain side of seven NMOFETs 13-1A having the gate signals of the address signals A1a, A2a, A3a, A4a, A5a, A6a, A7a. It is assumed that the fuses 13-1B have been blown. At this time, the address A1I input in synchronization with the clock signal CK1
N to A10IN designate defective memory cells in the main memory area 1. For example, if all of them are at a high level (hereinafter referred to as "1"), address signals A1a to A10a output from the address buffer circuit 2 Are all "1", for example, and all the address signals A1b to A10b are at a low level (hereinafter, referred to as "0") which is, for example, the ground potential.

Then, in each of the redundant selection circuits 12-n (n = 1 to 8), all of the three NMOSFETs 12-nA are turned off and the output side thereof is not connected to the ground potential only in the redundant selection circuit 12-1. Of the redundant selection circuits 12-2 to 12-8 are connected to the ground potential. On the other hand, this redundancy selection circuit
In the fuse circuit 13-1 of the redundant memory selection circuit 11-1 having 12-1 the fuse 13-1B is cut off and the address signals A1b, A2b, A3b, A4b, A5b, A6b, A7b are used as gate inputs. Since all the NMOSFETs 13-1A are turned off, the output side of the fuse circuit 13-1 is not connected to the ground potential.

Therefore, the precharge operation of the precharge circuit 14-n synchronized with the clock signal CK2 allows the redundant signals NRDB0 to NRDB
Of the RDB7, only the redundant signal NRDB0 becomes "1", and the OR of the redundant signals NRDB0 to NRDB7 is obtained by the OR gate 15-1, and the OR gate 15-1 outputs the redundant signal having the signal level "1". The memory activation signal NRDB is output to the address decoder 3 and the redundant address decoder 6.

The address decoder 3 to which the redundant memory activation signal NRDB is input is inactivated, and the redundant address decoder 6 is activated. The activated redundant address decoder 6 decodes, for example, the address signals A8a to A10b and activates predetermined redundant memory cells in the redundant memory area 5. Then, the R / W input / output circuit 4 is activated for the activated redundant memory cell.
, Writing of the write data DIN to the redundant memory cell or reading of the read data DOUT can be performed.

As described above, in the conventional semiconductor memory device, when an address designating a defective memory cell in the main memory area 1 is input, it is detected by each redundant memory selection circuit 11-n, and each redundant memory selection circuit 11-n detects the input. Memory selection circuit 11-n
A redundant address circuit 15 takes, for example, a logical sum of the redundant signals NRDB0 to NRDB7 output from the CPU, generates a redundant memory activation signal NRDB as a logical result, and generates an address decoder by the redundant memory activation signal NRDB. 3 is inactivated, that is, disabled, and the redundant address decoder 6
Is activated, that is, a redundant circuit method of enabling is adopted.

By adopting such a redundant circuit system, the semiconductor memory device is provided with redundancy, and even if a part of the main memory area 1 is not completely non-defective, a part of the redundant memory area 5 is replaced. A good product as the device can be obtained.

(Problems to be Solved by the Invention) However, the above-described semiconductor memory device of the redundant circuit type has the following problems.

As shown in FIG. 4, the conventional redundant circuit 10 shown in FIG.
For example, when the semiconductor memory device is integrated into a chip, for example, eight redundant memory selection circuits 11-1 to 11-8 and one redundant address circuit 15 are arranged as shown in FIG.
A wiring region is provided along it. The number of wires constituting this wiring area is 20 wires for address signals A1a to A10b, and 4 wires for NRDB0 to NRDB3 (NRDB4 to NRDB7).
There are a total of 25 lines, one line and one line for the redundant memory activation signal NRDB. However, if the number of wires in the wiring area is 25
In the case of a book, the circuit area (chip area) required for this increases, for example, the chip size increases.

In addition, in the redundant circuit 10 shown in FIG. 2, as can be seen from FIG.
The output side of the redundancy selection circuit 12-n and the output side of the fuse circuit 13-n respectively provided in 11-n are commonly connected, and each connection portion connects eight signal lines to the input side of the redundancy address circuit 15. Connected through. for that reason,
The wiring resistance and the wiring capacitance on these connection portions and the signal lines, that is, the wiring load increases. That is, the time constant of the wiring increases.

To compensate for this, the dimensions of the NMOSFETs 12-nA and 13-nA are increased when the main memory area 1 is used, that is, when the redundant signals NRDB0 to NRDB7 are all "0". It is necessary to increase the driving capability for setting the redundant signals NRDB0 to NRDB7 to "0". However, this leads to an increase in chip size and, consequently, a gate capacity of an address signal line serving as a gate input of each of the MMOSs 12-nA and 13-nA increases, resulting in a heavy load.

An object of the present invention is to provide a redundant circuit type semiconductor memory device which solves the problem of the prior art that a large circuit area is required due to wiring in a wiring region.

(Means for Solving the Problem) According to a first aspect of the present invention, there is provided a redundant memory having a redundant memory cell used in place of a defective memory cell in a main memory area selected by a plurality of address signals. A memory area, a redundant address decoder that decodes a part of the plurality of address signals to select a redundant memory cell in the redundant memory area, and detects the address signal that specifies the defective memory cell, and the detection result A plurality of redundant memory selection circuits for inactivating an address decoder for selecting an address of the main memory area and outputting a redundant memory activation signal for activating the redundant address decoder based on , Each of the redundant memory selection circuits transmits the plurality of address signals to a first
And a decoder circuit for decoding the first address signal divided into a second address signal and outputting a selection signal, and decoding a part of the second address signal using a pre-programmed fuse to generate a redundant signal. And a transmitting means for transmitting the redundant signal to an output node based on the selection signal, comprising a plurality of sub-redundant memory selection circuits each having a plurality of sub-redundant memory selection circuits. The redundant memory activation signal is generated by common connection.

According to a second invention, in the first invention, the sub-redundant memory selection circuits having a fuse circuit for decoding the same second address signal are arranged adjacently and collectively.

(Operation) According to the first aspect of the present invention, since the semiconductor memory device of the redundant circuit type is configured as described above, the decoder circuit of the sub-redundant memory selection circuit converts the plurality of address signals into the first and second address signals. And decodes the first address signal divided into the first address signal to output the selection signal.

The fuse circuit decodes a part of the second address signal using, for example, a fuse in which an address of a defective memory cell in the main memory area is programmed in advance, and the second
And outputs a redundant signal indicating whether or not a part of the address signal is a part of an address designating a defective memory cell.

The transmission means functions to transmit the redundant signal to the output node based on, for example, the selection signal. For example, when the redundant signal is not transmitted, the output is separated from the output of another transmission means.

The decoder circuit, fuse circuit,
In a semiconductor memory device of a redundant circuit type using a sub-redundant memory selection circuit having transmission means, for example, several sub-redundant memory selection circuits are paired to detect an address signal designating a predetermined defective memory cell. Work like that. Here, the sub-redundant memory selection circuit forming the set is
Assuming that the layout is discretely arranged, a corresponding set of sub-redundant memory selection circuits is selected by a decoder circuit included in each. The selected set of sub-redundant memory selection circuits each outputs a redundant signal indicating whether or not each fuse circuit decodes a part of the second address signal and designates a defective memory cell, Each of the redundant signals is transmitted to the commonly connected output nodes by the transmission means based on the selection signal.

Note that, depending on the configuration, for example, each set of fuse circuits decodes a part of the second address signal.
All of the second address signals are decoded without fail in all of the fuse circuits.

As described above, when each redundant signal in the selected set corresponds to a signal indicating the address of a defective memory cell, only the redundant address decoder is activated at the output node to which those redundant signals have been transmitted. A redundant memory activation signal is generated.

According to the second aspect, the layout relating to the sub-redundant memory selection circuit works so that the number of wirings in the wiring area and the wiring can be reduced more effectively.

 Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic block diagram of a semiconductor memory device employing a redundant circuit system according to an embodiment of the present invention, and FIG. 5 shows an example of the configuration of the redundant circuit in FIG. FIG. 6 is a schematic circuit diagram and FIG. 6 is a diagram showing an example of a layout arrangement of the redundant circuit in FIG. In FIG. 1, the same elements as those in FIG. 2 are denoted by the same reference numerals.

This semiconductor memory device includes a main memory region 1, an address decoder 3, an R / W input / output circuit 4, a redundant memory region 5, and a redundant address decoder 6, which are configured similarly to the semiconductor memory device of FIG. Address buffer circuits 21, 2
2 and a redundant circuit 30.

Each of the address buffer circuits 21 and 22 functions in the same manner as the address buffer circuit 2 and has a configuration in which the function is divided. That is, the address buffer circuit 21
Receives addresses A1IN to A3IN via address input lines in synchronization with a clock signal CK11, and outputs address signals A1a to A3a and inverted address signals (hereinafter,
A1b to A3b are output, and the address buffer circuit 22 inputs the addresses A4IN to A10IN through the address input lines in synchronization with the clock signal CK11, and outputs the address signals A4a to A10a through the address signal lines. , And outputs inverted address signals (hereinafter, referred to as address signals) A4b to A10b, each of which is constituted by a plurality of address buffers.

The redundant circuit 30 is a circuit for accessing the redundant memory area 5 in place of the main memory area 1 based on address signals A1a to A10b input via the address buffer circuits 21 and 22, and a plurality of sub-redundant memory selections. The circuit 31-n (n =
1 to 8) and a plurality of sub-redundant memory selection circuits 41-n (n
= 1 to 8).

On the other hand, each sub-redundant memory selection circuit 31-n detects whether or not it is of an address for specifying a defective memory cell based on the address signals A1a to A3b and A8a to A10b, and specifies the defective memory cell. Redundancy signals NRDB 0L to NRDB 7L indicating that the address is the output node, respectively
This is a circuit for outputting to N1, and includes a redundancy selection circuit 32-n and a fuse circuit 33-n.

Each redundancy selection circuit 32-n is connected to a decoder circuit 34-n.
n, and the decoder circuit 34-n has, for example, 3
It consists of an input NAND gate. The three-input NAND gate receives the first address signals A8a-A10b of the address signals A1a-A10b as input signals, decodes the first address signals A8a-A10b, and selects the selection signals S0L-S7L, respectively.
Is output.

Each fuse circuit 33-n includes a second address signal A1a to A1A.
6 NMOSFETs 33-nA whose gate inputs are address signals A1a to A3b which are part of 7b and whose sources are connected to the ground potential.
And six fuses 33-nB each having one end connected to the drain of the NMOSFET 33-nA. Each of the six fuses 33-nB is such that, for example, a predetermined fuse is blown and a part of the address of the defective memory cell in the main memory area 1 is programmed in advance. The other end of each of the six fuses 33-nB is commonly connected to a node N2L-n. Each of the nodes N2L-n is connected to, for example, a precharge PMOSFET 35-n connected to the power supply voltage VCC and controlled by the clock signal CK12.

Further, in each of the sub-redundant memory selection circuits 31-n, a transmission means 36-n is provided in each of the redundancy selection circuits 32-n in addition to the decoder circuit 34-n.

Each transmission means 36-n outputs a selection signal SmL (m = 0
7) to transmit the redundant signal NRDB mL (m = 0 to 7) to the output node N1 based on the NOR gate 36-nA and the NMO
Two NMOSFETs 37-n are connected to the SFET 36-nB and the decoder circuit 34-n. Here, the NOR gate 36-nA is controlled by the selection signal SmL to output the redundant signal.
The NRDB mL is inverted and output, and the NMOSFET 36-nB is turned on / off by the inverted output to transmit the redundant signal NRDB mL to the output node N1.

Each of the other sub-redundant memory selection circuits 41-n, like the sub-redundant memory selection circuit 31-n, has its own redundancy selection circuit.
42-n and a fuse circuit 43-n, and the redundancy selection circuit 42-n has a decoder circuit 44-n.

Each decoder circuit 44-n is connected to each decoder circuit 34-n.
This is a circuit that functions in the same manner as −n and outputs the selection signals S0R to S7R, and is configured by, for example, a three-input NAND gate.

Each fuse circuit 43-n is a circuit that decodes the address signals A4a to A7b other than the address signals A1a to 3b among the second address signals and outputs the redundant signals NRDB0R to NRDB7R, respectively, and outputs the address signals A4a to A7b. It has eight NMOSFETs 43-nA whose gates are input and whose sources are connected to the ground potential, and eight fuses 43-nB whose one ends are respectively connected to the drains of the eight NMOSFETs 43-nA.

The portion of the address of the defective memory cell in the main memory area 1 other than that programmed by the fuse 33-nB is programmed in advance by, for example, cutting a predetermined fuse. . The other end of each of the eight fuses 43-nB is commonly connected to a node N2R-n. Each of the nodes N2R-n is connected to a precharge PMOSFET 45-n which is connected to, for example, a power supply voltage VCC and controlled by a clock signal CK12.

Further, in each sub-redundant memory selection circuit 41-n, a transmission means 46-n is provided in addition to the decoder circuit 44-n in each redundancy selection circuit 42-n.

Each transmission means 46-n outputs a selection signal SmR (m = 0
7) to transmit the redundant signal NRDBmR (m = 0 to 7) to the output node N1 based on the NOR gate 46-nA and the NMOSF
ET46-nB, and two NMOSFETs 47-n are connected to the decoder circuit 44-n. Where the NOR gate
46-nA is controlled by the selection signal SmR to invert and output the redundant signal SmR, and the NMOSFET 46-nB is ON / OFF controlled by the inverted output to transmit the redundant signal SmR to the output node N1. .

Each sub-redundant memory selection circuit 31 configured as described above
Output sides of -n and 41-n are commonly connected at an output node N1, and the output node N1 is connected to the address decoder 3 and the redundant address decoder 6. Further, a precharge circuit 50 is connected to the output node N1. The precharge circuit 50 has a function of, for example, receiving the supply of the power supply voltage VCC and precharging the output node N1 in synchronization with the clock signal CK12.
It is composed of FET and inverter.

In each of these sub-redundant memory selection circuits 31-n and 41-n, a set of sub-redundant memory selection circuits 31-1 and 41-1 is
The first address signals input to the respective decoder circuits 34-1 and 44-1 are made the same, and the respective fuse circuits 33-1 and 44-1 are used.
The sum of a part of the second address signals input to the first and the second address signals becomes the entire second address signals A1a to A10b. Memory selection circuits 31-3 and 41-3, sub-redundant memory selection circuits 31-4 and 41-4, and sub-redundant memory selection circuits 31-5 and 41
-5, the same applies to the respective sets of the sub-redundant memory selection circuits 31-6 and 41-6, the sub-redundant memory selection circuits 31-7 and 41-7, and the sub-redundant memory selection circuits 31-8 and 41-8.

Therefore, an address signal designating the address of a predetermined one defective memory cell is detected by one of these sets, and the output node N1 always includes the selected decoder circuits 34-n and 44-n. The redundant signals NRDB mL and NRDB mR of the sub-redundant memory selection circuits 31-n and 41-n of the set are configured to be transmitted based on the selection signals SnL and SnR.

 Next, the operation will be described.

For example, in a set of sub-redundant memory selection circuits 31-8 and 41-8, among the hazes provided in the fuse circuits 33-8 and 43-8, the address signals A1b, A2b, A3b, A4b, A4b, A5b, A6b, A7
It is assumed that fuses 33-8B and 43-8B connected to the drains of NMOSFETs 33-8A and 43-8A having b as a gate input are cut.

At this time, assuming that the addresses A1IN to A10IN input to the address buffer circuits 21 and 22 in synchronization with the clock signal CK11 specify the address of the defective memory cell and all the signal levels are "1". The address signals A1a to A3a detected from the address buffer circuit 21 are "1", the address signals A1b to A3b are "0", and the address signals A4a to A10a output from the address buffer circuit 22 are "1".
The address signals A4b to A10b become "0".

Then, in each of the sub-redundant memory selection circuits 31-n and 41-n, the selection signal S among the decoder circuits 34-n and 44-n is selected.
mL and SmR become “0” because the sub-redundant memory selection circuit 34−
8 and 44-8 are only the selection signals S7L and S7R, and all others are "1".

The decoder circuits 34-n and 44-n which output the selection signals SmL and SmR having the signal level "1" are provided by other circuits except the sub-redundant memory selection circuits 31-8 and 41-8, namely, the sub-redundancy. They are memory selection circuits 31-1 to 31-7 and 41-1 to 41-7.
These sub-redundant memory selection circuits 31-1 to 31-7 and 41
In the case of -1 to 41-7, since the selection signals S0L to S6L and S0R to S6R are all "1", the transmission means 36-n and 46-n (n = 1 to 4)
7) In each of the NOR gates 36-nA and 46-nA (n = 1 to
Since the output of 7) is always fixed to “0”, the NMOSFET 36−n
B, 46-nB (n = 1 to 7) is always off, and the redundant signal NRDB m from the fuse circuits 33-n, 43-n (n = 1 to 7).
L and NRDB mR are not transmitted to the output node N1, and their outputs are disconnected from the output node N1.

On the other hand, in the sub-redundant memory selection circuits 31-8 and 41-8 having the decoders 34-8 and 44-8 outputting the selection signals S7L and S7R having the signal level "0", the selection signals S7L and S7R are transmitted by the transmission means.
Input to NOR gates 36-8A and 46-8A of 36-8 and 46-8, respectively. In the fuse circuits 33-8 and 43-8, the clock signal CK12 is generated due to the ON / OFF operation of the NMOSFETs 33-8A and 43-8A and the setting of the cut state of the fuses 33-8B and 43-8B. Signal NRDB whose signal level is "1" by the precharge operation of PMOSFETs 35-8 and 45-8 synchronized with
Outputs 7L and NRDB 7R. This redundant signal NRDB 7L, NRDB 7R
Are the NOR gates 36-8A, 36-8A,
Input to 46-8A.

At this time, in each of the sub-redundant memory selection circuits 31-8 and 41-8, a set of two NMOSFETs 37-8 and two NMOSFETs 47-8
One is on, the other is off, and the redundant signal NRDB 7
The signal level “1” of L, NRDB 7R is strengthened.

The NOR gate 36-8A to which the selection signal S7L having the signal level of "0" is input inverts and outputs the same input redundant signal NRDB 7L, the output of the NOR gate 36-8A becomes "0", and the NMO
SFET36-8B turns off.

Similarly, a selection signal S7R whose signal level is "0" is input.
The NOR gate 46-8A inverts and outputs the same redundant signal NRDB 7R, the output of the NOR gate 46-8A becomes "0", and the NMOSFET 46-8B is turned off.

Thus, the sub-redundant memory selection circuits 31-8, 41-
8, only the redundant signals NRDB 7L and NRDB 7R are transmitted by the transmission means 36.
-8, 46-8 to the output node N1. Therefore, each of the sub-redundant memory selection circuits 31-n and 41-n
A redundant memory activation signal NRDB whose signal level is "1" is generated at output node N1.

The redundant memory activation signal NR generated as described above
DB is input to the address decoder 3 to inactivate the row address decoder 3a and the column address decoder 3b, and is input to the redundant address decoder 6 to input the redundant column address decoder
6a and the redundant row address decoder 6b are activated.

The redundant column address decoder 6a and the redundant row address decoder 6b activated by the redundant memory activation signal NRDB
For example, the address of the redundant memory cell in the redundant memory area 5 is selected based on the address signals A8a to A10b, and the redundant memory cell is activated. Then, by accessing the activated redundant memory cell via the R / W input / output circuit 4, writing of the write data DIN or reading of the read data DOUT can be performed.

As described above, the redundant memory area 5 is selected, and the redundant memory cell in the redundant memory area 5 can be accessed in place of the defective memory cell in the main memory area 1. , The main memory area 1 can be selected by connecting the output node N1 to the ground potential by each of the sub-redundant memory selection circuits 31-n and 41-n.

For this purpose, for example, by programming the address of the defective memory cell according to the cut state of the fuses 33-nA and 43-nB of the fuse circuits 33-n and 43-n, the address input other than the address of the defective memory cell can be performed. , In any one of the sub-redundant memory selection circuits 31-n and 41-n, the combination of the selection signal SmL and the redundancy signal NRDB mL or the combination of the selection signal SmR and the redundancy signal NRDB mR is both " It should be set to 0 ".

By doing so, the corresponding set of transmission means 36-n
The NMOSFET 36-nB and the NMOSFET 46-nB of the transmission means 46-n are turned on, the output node N1 is connected to the ground potential, the redundant address decoder 6 is inactivated, and the address decoder 3
Is activated.

 This embodiment has the following advantages.

(A) In the redundant circuit type semiconductor memory device of this embodiment, one defective memory cell is generated by one of the sets of the sub-redundant memory selection circuits 31-n and 41-n divided for the second address signal. Are detected, and each pair is selected by the decoder circuits 34-n and 44-n.

For this reason, each set of sub-redundant memory selection circuits 31-n,
41-n do not necessarily need to be arranged in the same area, and can be arranged in different areas. Thereby, as shown in the layout example of FIG. 6, for the second address signal, the sub-redundant memory selection circuits 31-1 to 31-8 for inputting the address signals A1a to A3b are arranged adjacently and collectively. However, the sub-redundant memory selection circuits 41-1 to 41-8 to which the address signals A4a to A7b are input can be arranged adjacently and collectively. Therefore, each sub-redundant memory selection circuit 31-n,
For example, the number of wirings in the wiring area for the 41-n address signal lines can be reduced from, for example, 14 to 20 in the past.

Further, in the semiconductor memory device of the redundant circuit type of the present embodiment, the transmission means is provided to each of the sub-redundant memory selection circuits 31-n and 41-n.
36-n and 46-n are provided, and the transmission means 36-n and 46-n transmit the redundant signals NRDB mL and NRDB mR to the output node N1 based on the selection signals SmL and SmR, thereby activating the redundant memory. The signal NRDB is generated. Therefore, at the output side of each of the sub-redundant memory selection circuits 31-n and 41-n, in the wiring area for generating the redundant memory activation signal NRDB,
The eight lines required in the conventional redundant circuit system can be changed to one line of the output node N1.

Therefore, as can be seen from the above, in the semiconductor memory device of the redundant circuit type of the present embodiment, the number of wirings in the wiring area is reduced to 15, for example, as shown in FIG. With the effect of reducing the number of wirings in the wiring region, the chip area of the semiconductor memory device, that is, the chip size can be reduced.

(B) In the case of the present embodiment, although the wiring load on the output node N1 becomes heavy, the provision of the transmission means 36-n and 46-n allows the use of the NMOSFETs 36-nB and 46 when the main memory area 1 is used. −nB
Discharges the output node N1.
Even if the driving capability of OSFETs 36-nB and 46-nB is increased, there is no effect on the address signal lines on the address signal input side of each of the sub-redundant memory selection circuits 31-n and 41-n, and the operation speed is the same as that of the conventional one Can be expected.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. The following are examples of such modifications.

(I) In the redundant circuit type semiconductor memory device of the above embodiment, the configuration of the semiconductor memory device shown in FIGS. 1, 5 and 6 can be modified.

For example, the redundancy circuit 30 divides a second address signal (for example, the address signals A1a to A7b) into two parts, and sets a set of sub-redundant memory selection circuits 31-n and 41-n that respectively input the divided address signals. , Eight addresses are provided to detect an address for designating a defective memory cell and a redundant memory activation signal is provided.
NRDB is generated. But this is the second
The address indicating the defective memory cell may be detected by the plurality of sub-redundant memory selection circuits that respectively input the address signals obtained by dividing the address signal by a plurality of divisions instead of the two divisions. Further, in the above-described embodiment, the case where the number of the sets of the sub-redundant memory selection circuits 31-n and 41-n is eight is exemplified, but the number is not necessarily eight.

As for the address signal, various changes can be made in the number of signals, how to enter the address signal line, and the like.

The sub-redundant memory selection circuits 31-n and 41-n include redundancy selection circuits 32-n and 42-n, fuse circuits 33-n and 43-n, decoder circuits 34-n and 44-n, and precharge circuits. PMOSFET35−
n, 45-n, transmission means 36-n, 46-n, and PMOSFET 37-n, 4
The configuration such as 7-n can be changed, and the configuration of the precharge circuit 50 can also be changed as appropriate.

Further, the layout arrangement of the sub-redundant memory selection circuits 31-n and 41-n and the precharge circuit 50 can be changed as appropriate.

(II) The operation example shown in the above embodiment is merely an example, and can be appropriately changed according to a change in the configuration or the like. Further, the level setting of each signal can be changed according to a modification of the configuration or the like.

(III) The redundant circuit type semiconductor memory device of the present invention
Not limited to dynamic RAM, for example, static RAM
And various semiconductor memory devices including ROMs and the like.

(Effects of the Invention) As described above in detail, according to the first aspect, the plurality of sub-redundant memory selection circuits are provided, and each of the sub-redundant memory selection circuits includes the decoder circuit, the fuse circuit, and the transmission unit. The redundant memory selection circuit of a predetermined combination detects an address designating a defective memory cell, and generates the redundant memory activation signal. Therefore, the predetermined combination of sub-redundant memory selection circuits does not necessarily have to be arranged in the same region, and a discrete layout arrangement is possible.

Further, the output nodes in each of the sub-redundant memory selection circuits are commonly connected, and the redundant signal is transmitted to the output nodes by the transmission means based on the selection signal, thereby generating the redundant memory activation signal. Therefore, the wiring on the output side of each sub-redundant memory selection circuit may be, for example, one of the common connection portions of the output nodes.

Therefore, in the semiconductor memory device of the redundant circuit type according to the present invention, the number of wirings in the wiring area can be reduced, the efficiency of routing can be improved, and the memory chip size can be reduced. Moreover, by providing the transmission means,
At least the same operation speed can be expected with respect to the conventional redundant circuit type semiconductor memory device.

According to the second invention, among the sub-redundant memory selection circuits, a sub-redundant memory selection circuit having a fuse circuit that decodes the same second address signal is arranged adjacently and collectively, so that wiring The efficiency of reducing the number of wires in the region can be promoted, and the routing of wires can be optimized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a semiconductor memory device adopting a redundant circuit system according to an embodiment of the present invention, and FIG. 2 is a schematic structural example of a semiconductor memory device adopting a conventional redundant circuit system. , FIG. 3 is a schematic circuit diagram of the redundant circuit in FIG. 2, FIG. 4 is a diagram showing an example of a layout arrangement of the redundant circuit in FIG. 3, and FIG. 5 is a diagram in FIG. FIG. 6 is a schematic circuit diagram of the redundant circuit shown in FIG. 6, and FIG. 6 is a diagram showing an example of a layout arrangement of the redundant circuit in FIG. 1 ... Main memory area, 3 ... Address decoder, 5 ...
Redundant memory area, 6 Redundant address decoder, 30
Redundancy circuit, 31-1 to 41-8: Sub-redundant memory selection circuit, 33-1 to 43-8: Fuse circuit, 33-1B to 43-8B
... Fuse, 34-1 to 44-8 ... Decoder circuit, 36-
1 to 46-8: transmission means, A8a to A10a, A8b to A10b ... first address signal, A1a to A7a, A1b to A7b ... second address signal, S0L to S7L, S0R to S7R ... selection Signal, NRDB 0
L to NRDB 7L, NRDB 0R to NRDB 7R ... redundant signal, NRDB ...
Redundant memory activation signal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) G11C 29/00 G11C 16/06 G11C 11/401 G11C 11/413

Claims (2)

(57) [Claims] A redundant memory area having a redundant memory cell used in place of a defective memory cell in a main memory area selected by a plurality of address signals; A redundant address decoder for selecting a redundant memory cell in a memory area; and an address signal for designating the defective memory cell, wherein the address decoder for selecting an address of the main memory area is deactivated based on the detection result. And a plurality of redundant memory selection circuits for outputting a redundant memory activation signal for activating the redundant address decoder, wherein each of the redundant memory selection circuits transmits the plurality of address signals to the first and second address signals. A decoder circuit for decoding the first address signal divided into the second address signals and outputting a selection signal; A plurality of fuse circuits each including a fuse circuit for decoding a part of the second address signal using a pre-programmed fuse to output a redundant signal, and a transmitting unit for transmitting the redundant signal to an output node based on the selection signal; A semiconductor memory device comprising: a plurality of sub-redundant memory selection circuits; and a common connection between output nodes in each of the sub-redundant memory selection circuits to generate the redundant memory activation signal. 2. The semiconductor memory device according to claim 1,
Among the sub-redundant memory selection circuits, one having a fuse circuit that decodes the same second address signal,
A semiconductor memory device characterized by being arranged adjacently and collectively.