JPH04209389A - Redundancy circuit system - Google Patents

Abstract

PURPOSE:To reduce a circuit area required for the wiring by providing a redundancy selecting circuit, using a fuse circuit programed beforehand to decode address signals, and transmitting the redundancy signal to an output node. CONSTITUTION:The plural address signals A1IN-A10IN are divided by the redundancy memory selecting circuits 32n, 42n, and the address signals A1a-A3a, A1b-A3b are decoded to output the selecting signals to address decoders 6a, 6b for redundancy column and row. The parts of address signals A4a-A7a, A4b-A7b are decoded by using the fuse circuit 43n programed beforehand to output the redundancy signals. At this stage, the redundancy signals are transmitted to the output node in accordance with the selecting signals. Further, the output nodes are connected in common, and the redundancy memory activating signal is provided to activate the decoder 6. Then, the common connection for output nodes needs only one line, and the arrangement for the selecting circuits 31n, 41n of prescribed combination to the same area is unrequired, thereby the circuit area required for wiring can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is applicable to, for example, dynamic RAM (runtime RAM).
access memory), static RAM, ROM (
In a semiconductor storage device (semiconductor memory device) such as a read-only memory (read-only memory), in addition to a main memory area that has a normal memory cell, for example, a redundant memory area that has redundant memory cells for providing redundancy and its The present invention relates to a redundant circuit system in which a redundant circuit is provided to enable a redundant memory area, and a redundant memory cell in the redundant memory area is used in place of a defective memory cell in a main memory area.

(Prior Art) In recent years, semiconductor memory devices have been trending toward higher integration and larger capacity, and even with the latest technology, it is difficult to manufacture perfectly good products at a high yield. Therefore, in recent semiconductor memory devices such as 16M5 DRAM, in addition to the main memory area having normal memory cells, a redundant memory area is provided to provide redundancy, so that a part of the main memory area is Even if a defective memory cell exists, by programming the address of the defective memory cell to the fuse in the redundant circuit pattern, the defective memory cell in the main memory area will never be read or written, and the memory cell in the redundant memory area will be The redundant memory cells can be read and written.

FIG. 2 is a block diagram schematically showing a configuration example of a semiconductor memory device for explaining a conventional redundant circuit system. Further, FIG. 3 schematically shows an example of the circuit configuration of the redundant circuit in FIG. 2. For example, FIG. FIG. 4 is a diagram showing an example of the layout arrangement of the redundant circuit shown in FIG. 3;

This semiconductor memory device is, for example, a 16MSDRAM, and includes a main memory area 1 in which, for example, a large number of memory cells are arranged in a matrix.

An address buffer circuit 2 is connected to the main memory area 1, and an address decoder 3 is provided between the main memory area 1 and the address buffer circuit 'fp12.

ing. The address buffer circuit B2 supplies addresses AIIN to A in synchronization with the clock signal C1 via the address input line.
This is a circuit that inputs 10F and outputs address signals A1a to A10a and inverted address signals (hereinafter simply referred to as address signals) A1b to A10L+ via address signal lines, and is composed of a plurality of address bars. ing. The attos decoder 3 receives address signals Ala to A.
10a, Alb to -A10b to select the address of a memory cell in the main memory area 1, and is composed of a row address decoder 3a and a column address decoder 3b. Furthermore, a read/write input/output circuit B (hereinafter referred to as an R/W input/output circuit) 4 is connected to the main memory area 1 for inputting and outputting write data DIN and read data DOUT.

A redundant memory area 5 is provided near the main memory area 1 in which a plurality of redundant memory cells are arranged. A redundant address decoder 6 is connected to the redundant memory area, and a redundant circuit &410 is provided between the address buffer circuit 2 and the redundant address decoder 6.

Redundant address decoder 6 receives redundant memory activation signal NR.
DB is activated based on the address signal A8a-, for example.
This circuit decodes A10b to select a redundant memory cell in the redundant memory area 5, and is composed of a redundant column address decoder 6a and a redundant row address decoder 6b. The redundant circuit 10 is a circuit for accessing a redundant memory area instead of the main memory area 1 based on address signals A1a to A10b, and includes a plurality of redundant memory selection circuits 1.
l−n (for example, n=1 to 8, the same applies hereinafter).

Each redundant memory selection circuit 11-n receives an address signal A1a.
- Redundant signals NRDBO - NR based on A10b, respectively
This circuit outputs DB7, and includes a redundancy selection circuit 12-n and a fuse circuit 13-0.

Each redundancy selection port &J12-n is connected to the address signal A8, for example.
Three N-channel type 'J108FETs (hereinafter referred to as NMO8
>12-n, called FET, consists of A'''C'''C''.3
Each NMO5FET12-nA has its source connected to the ground potential, and its drain consists of a P-channel type MO5FET (hereinafter referred to as PMOSFET) and an inverter. The precharge circuit 14-n is connected to the precharge circuit 14-n.

Each fuse circuit 13-n has an address signal Ala, for example.
14 NMO8FET13- with ~A7b as input and each source connected to ground potential
nA and 14 fuses 1B-nB each having one end connected to the drain of the NMO5FET 1B-nA. Here, the 14 fuses l3-nB included in each fuse circuit 13-n are cut in a predetermined combination in order to program the addresses of defective memory cells in the main memory area 1 in advance.

Further, in each redundant memory selection circuit 11-n, the drains of the three NN10SFETs 12-nA of the redundant selection circuit 12-n and the other ends of the 14 fuses 1B-nB of the fuse circuit 13-n are connected to each other. Commonly connected,
Each common connection part is a precharge circuit l2-n.
B and has a configuration in which it is precharged in synchronization with the clock signal CK2. A redundant address circuit 15 is connected to the output side of each of the commonly connected redundant memory selection circuits 11-n via an S-signal line.

The redundant address circuit 15 receives, for example, a redundant signal NFLDBO.
~ Generates a redundant memory activation signal NRDB that deactivates the address decoder 3 and activates the redundant address decoder 6 by taking the logic of NRDB7, and attes the redundant memory activation signal NRDB to the row address decoder of the stepcoder 3. 3a and column address decoder 3b, and the redundant column address decoder 6a and redundant row address decoder 6b of the redundant address decoder 6, the circuit is composed of, for example, an eight-power OR gate 15-1.

Next, the operation will be explained.

For example, among the 14 fuses 13-IB provided in the fuse circuit 13-1 of the redundant memory selection circuit 11-1, the address signals Ala, -A2a, -A3a.

Assume that seven fuses 1B-IB connected to the drain sides of seven XN·10FETs 1B-IA whose gate inputs are A4a, A5a, A6a, and A7a are disconnected. At this time, the addresses AIIN to -A10IN input in synchronization with the clock signal CKI specify the defective memory cells in the main memory area 1, and for example, all of them are at high level (hereinafter referred to as 1°). If so, the address signals A1a to lOa output from the address buffer circuit 2 are all at "1°", for example, and the address signals A1b to A10b are all at a low level (hereinafter referred to as "○"), which is, for example, a ground potential.

).

Then, among the redundant selection circuits 12-n (n=1 to 8), all three NMO8FETI2-nA are turned off and the output side is not connected to the ground potential because of the redundancy selection port 612.
-1 only, other redundant selection port #! 12-2~12-
On the other hand, the fuse circuit 13-1 of the redundant memory selection circuit 11-1 having this redundant selection circuit 12-1 is connected to the fuse 1
3-IB disconnection state and address signal A 1t1. A
2b, A3b.

7 NRs with A4b, A5b, A6b, and A7b as gate inputs)] By all OS FETlB-IAs being turned off, fuse #! 13-1 output (rule does not lead to ground potential.

Therefore, the redundant signal N
Among RDBO to NRDB7, only the redundant signal NRDBO becomes "1 pass", which is taken by the OR gate 13-1 or the logical sum of the redundant signals NRDBO to NRDB7, and its O
The R gate 15-1 outputs a redundant memory speech conversion signal NRDB having a signal level of "°1°" to the address decoder 3 and the redundant address decoder 6.

The address decoders 3 each receiving the redundant memory activation signal N RD B are inactivated, and the redundant address decoder 6 is activated. Activated redundant address decoder 6
, for example, decodes the address signals A8a to A10b and activates a predetermined redundant memory cell in the redundant memory area. Then, for the activated redundant memory cell, R,
-'W If accessed through the input/output circuit 4, write data DIN can be written to the redundant memory cell, or read data DOIIT can be read.

In this manner, in the conventional semiconductor memory device, when an address specifying a defective memory cell in the main memory area 1 is input, each redundant memory selection circuit 11-n detects it, and the detection causes each redundant memory cell to be selected. Memory selection times & 411
For example, the redundant address circuit 15 performs a logical sum on the redundant signals NRDBO to NRDB7 outputted from -n, generates a redundant memory activation signal NRDB as the logical result, and uses the redundant memory activation signal NRDB. A redundant circuit system is adopted in which the address decoder 3 is inactivated, ie, disabled, and the redundant address decoder 6 is activated, ie, enabled.

By adopting such a redundant circuit system, the semiconductor memory device is provided with redundancy, and even if part of the main memory area 1 is not completely good, the semiconductor memory device can be replaced with a part of the redundant memory area. It is possible to obtain a good product as a device. .

(Problems to be Solved by the Invention) However, the above redundant circuit system has the following problems.

As shown in FIG. 4, the conventional redundant circuit 10 of FIG.
For example, when incorporating into a chipped semiconductor memory device, for example, eight redundant memory selection circuits 11-1 to 11-
8 and one redundant address circuit 81 are arranged as shown in the figure, and a wiring area is provided along them. The number of wires constituting this wiring area is the address signal Ala to A10.
20 wires for b, NRDBO to NRDB3 (N
M4 wiring for RDB4 to NRDB7) and one wiring for redundant memory activation signal NRDB, total 25
It becomes a book. However, when the number of wires in the wiring area reaches 25, the circuit surface precision (chip surface @) required becomes large, and, for example, the chip size becomes large.

In addition, in redundant circuit #: 10 shown in FIG. 2, ' is a redundant selection circuit 1 provided in each redundant memory selection circuit F#111-n, as can be seen from FIG.
2-n and the 8-power side of the fuse circuit 13-n are each connected in common, and each connection part is connected to the input side of the redundant address circuit 1 through 8 signal lines. Therefore, the wiring resistance and wiring capacitance, that is, the wiring load, on these connection portions and signal lines become large. In other words, the time constant of the wiring becomes large.

To compensate for this, when using main memory area 1,
That is, all redundant signals NRDBO to NRDB7 ((O11
For the case where NMO3FET12-nA or N
By increasing the dimension of MO3FETI3-nA, redundant signals NRDBO to NRDB7 can be
It is necessary to increase the driving capacity to achieve this. However, this results in an increase in chip size, which in turn leads to an increase in the size of each M
The gate capacitance of the address signal line input to MO512-nA and 13-nA increases, resulting in a heavy load. This provides a redundant route method that solves the problem of requiring a large concave Ft'4 area due to wiring.

- (Means for Solving the Notes) In order to solve the above problem, the first invention provides a redundant memory cell that is used in place of a defective memory cell in a main memory area selected by a plurality of address signals. a redundant memory area having the above '6. a redundant address decoder that selects a redundant memory cell in the redundant memory area by decoding a part of the address signal of the number; and a redundant address decoder that detects the address signal that specifies the defective memory cell, and based on the detection result. ,
A redundant circuit system comprising: a plurality of redundant memory selection circuits that output a redundant memory activation signal that inactivates an address decoder that selects an address in the main memory area and activates the redundant address decoder; Each redundant memory selection circuit selects a first
and a decoder circuit that decodes the first ATTO signal divided into the second ATTO signal and outputs a selected one code;
a fuse circuit that decodes a part of the second attribution signal using a preprogrammed fuse and outputs a redundant signal; and a transmission that transmits the redundant word to the output node I\ based on the selection number 12. and a plurality of sub-redundant memory selection circuits each having a size of 115, and output nodes of each of the sub-redundant memory selection circuits are commonly connected to generate the redundant memory activation signal. be.

A second aspect of the present invention is that, in the first aspect, among the sub-redundant memory selection circuits, those having fuse circuits for decoding the same second address signal are arranged adjacent to each other.

(Operation) According to the first invention, since the redundant circuit system is configured as described above, the decoder circuit of the sub-redundant memory selection circuit divides the plurality of address signals into first and second address signals. It functions to decode the first address signal and output the selection signal.

The fuse circuit decodes a portion of the second address signal using, for example, a fuse in which the address of a defective memory cell in the main memory area is programmed in advance, and the fuse circuit decodes a portion of the second address signal when the address of a defective memory cell in the main memory area is programmed in advance. It works to output a redundant signal indicating whether or not it is part of the specified address.

The transmission means works, for example, to transmit the redundant signal to the output node based on the selection signal, but when the redundancy signal is not transmitted, for example, its output is separated from the outputs of other transmission means.

In a redundant circuit system using a sub-redundant memory selection circuit having a decoder circuit, a fuse circuit, and a transmission means that function as described above, for example, several sub-redundant memory selection circuits are combined to select a predetermined defective memory cell. It works to detect the address signal that specifies the address. Here, if the sub-redundant memory selection circuits of the set are arranged in a discrete layout, the sub-redundant memory selection circuits of the corresponding set.

' is selected by the decoder circuit each has. The selected set of sub-redundant memory selection circuits each output a redundancy signal indicating whether or not each fuse circuit decodes a portion of the second address signal and specifies a defective memory cell; Each redundant signal is transmitted by the transmission means to a commonly connected output node based on the selection signal.

Depending on the configuration, for example, each set of fuse circuits may be
A portion of the second address signal is each decoded, but all the second address signals are decoded in their entirety by the fuse circuits.

As described above, when each redundant signal of the selected set corresponds to a signal indicating the address of a defective memory cell, only the redundant address decoder is activated for the output node to which those redundant signals are transmitted. A redundant memory activation signal is generated.

According to the second invention, the layout of the sub-redundant memory selection circuit works to more effectively reduce the number of wires and shorten the wires in the wiring region.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic configuration block diagram of a semiconductor memory device for explaining a redundant circuit system showing an embodiment of the present invention.
3 is a schematic 4-times diagram showing an example of the configuration of the redundant circuit in FIG. 1, and FIG. 6 is a diagram showing an example of the layout arrangement of the redundant circuit in FIG. In FIG. 1, elements common to those in FIG. 2 are given the same reference numerals.

This semiconductor memory device has a main memory area configured similarly to the semiconductor memory device in FIG. In addition, address buffer time B2
1.22 and redundant episode #! 30.

The address buffer circuits 21 and 22 both function in the same manner as the address buffer circuit B2, and have a structure in which the functions are divided into respective parts. That is, the address buffer circuit 21 inputs the addresses AIIN to A3IN via the address input line in synchronization with the clock signal CK11,
Address signals A1a to A3a,
Inverted address signal (hereinafter referred to as address signal >Alb
The address buffer circuit B22 outputs addresses A41N to A101N via the AT input line in synchronization with the clock signal CK1.1, and outputs address signals A48 to A10a and A3b via the address signal line. Inverted address signals (hereinafter referred to as address signals) A4b to A10
Each address buffer is made up of a plurality of address buffers.

The redundant circuit 30 is a circuit for accessing a redundant memory area instead of the main memory area 1 based on address signals A1a to Al0b inputted via the address buffer circuits 21 and 22, and selects a plurality of sub-redundant memories. circuit 3
1 to n (n=1 to 8), and a plurality of sub redundant memory selection circuits 4l-n (n=1 to 8).

On the other hand, each sub-redundant memory selection circuit &J31-n detects whether or not it is an address specifying a defective memory cell based on the address signals Ala to A3b and A8a to A10b, and specifies the defective memory cell. Redundant signal NRDBOI~NR indicating if it is of the address
This circuit outputs the DB7L to the output node N1, and includes a redundancy selection circuit 32-n and a fuse circuit 33-0.

Each redundancy selection circuit 32-n is a decoder circuit 3.
4-n, and its decoder times #! f34-H
inputs address signals Ala to A7b to first address signals A8a to A10b and second address signals A1a to -A1.
The first address signal A8a to A of the two divided into 0b
10b and outputs selection signals SQL to S7L, for example, "3-manpower NAND game 1 to
It consists of

Each fuse circuit 33-n receives a second analog signal Ala.
The address signals A1a-A3b, which are part of ~A7b, are input to the gate I~, and the sources are connected to the ground potential.
MOS FET 33-n A and its N
Each of the six fuses 33-nB has one end connected to a train of MO3FETs 33-nA. For example, when a predetermined fuse is cut off, the main memory area 1 A part of the addresses of the defective memory cells of 33-nB are programmed in advance.The other ends of each of the six fuses 33-nB are commonly connected to the node N2L-n.
21. -n, respectively, are connected to, for example, a PMOS FET 35-n for precharging which is connected to the power supply voltage CC and controlled by the clock signal CK12.

Further, in each sub-redundant memory selection circuit 31-n, each redundancy selection circuit 32-n has a decoder circuit #134-n.
In addition to the transmission means 36-n, a transmission means 36-n is provided.

Each transmission means 36-n receives a selection signal SmL (m=
NOR gate 3
6-nA and a NOR gate 36-nB, and two NN108FETs 37 are connected between the decoder circuit 34-n and the decoder circuit 34-n.
n is connected. Here, NOR gate 36-
nA is controlled by selection signal SmL and redundant signal NR
DBmL is inverted and output, and the NOR gate 36-nB is controlled on/off by the inverted output to output the redundant signal N.
The RDBml is transmitted to the output node N1.

Each of the other sub-redundant memory selection circuits 41-n, like the sub-redundant memory selection circuit 31-n, has a redundancy selection circuit 42-n and a fuse circuit 43-n, respectively, and its redundancy selection circuit H442-n is , and a decoder circuit 44-n.

Each decoder circuit &444-n functions in the same manner as each decoder circuit 34-n and receives selection signals SOR to S7.
This is a circuit that outputs R, and is composed of, for example, a three-manpower NAND gate.

Each of the fuse circuits 43-n receives address signals A4a to A4a to 3b other than address signals Ala to 3b among the second address signals.
Decipher A7b and generate redundant signals NR, DBOR~NRDBi
There is a WEB that outputs R and Z-L, and eight NMO3FET4B-nA whose gates are input with address signals A4a to A7fi and whose sources are connected to the ground potential.
It has eight fuses 43-nB each having one end connected to the terminals of the eight NMO8FETs 43-nA.

For example, when a predetermined fuse is cut, fuse 4B-nB is programmed with fuse 33-nB among the addresses of defective memory cells in main memory area l.
The parts other than t/"x are programmed in advance. The other ends of each of the eight fuses 4B-nB are commonly connected to the nodes N2R-n.
2R-n are each connected with a PMO3FET 45-n for precharging, which is connected to, for example, a power supply voltage CC and controlled by a clock signal CK12.

Further, in each sub-redundant memory selection circuit 41-n, each redundancy selection circuit 42-n is provided with a transmission means 46-n in addition to a decoder circuit #144-n.

Each transmission means 46-n receives a selection signal SIIIR(
Based on m=c)~7), the redundant signal NRDBmR(m=0
~7) to the output node N1, and NOR
Consisting of gates 1 to 46-nA and NMO5FET46-nB, two MO5Fs are connected between the decoder circuit 44-n and
ET47-n is connected. Here, NOR game 1
46-nA is controlled by the selection signal SmR to invert and output the redundant signal SmR, and the NMO5FET46-n
B is controlled to be turned off by its inverted output and transmits the redundant signal SmR to the output node N1.

Each subredundant memory selection circuit 831 configured as described above
The outputs of -n and 41-n are commonly connected at the output node Nl, and the output node N1 is connected to the address decoder 3 and the redundant address decoder 6. A precharge circuit 50 is connected to the precharge circuit 50. This precharge circuit 50 receives, for example, a power supply voltage CC and a clock signal CK.
It has a function of precharging the output node N1 in synchronization with I2, and is composed of, for example, two PMO5FETs and an inverter.

Each of these sub-redundant memory selection circuits 831-n.

'41-n, the set of sub-redundant memory selection circuits 31-1 and 41-1 is connected to each decoder circuit 34-1.4.
The first address signals inputted by the fuse circuits 3B-1 and 4-1 are the same, respectively.

43-1, or the entire second address signals Ala to Aiob (hereinafter referred to as sub-redundant memory selection circuits 31-2 and 41-2).
Sub-redundant memory selection circuits 31-3 and 41-3, sub-redundant memory selection circuit 3]-4 and 41-4, sub-redundant memory selection circuit 31-5 and 41-5, sub-redundant memory selection circuit &J
31-6 and 41-6, sub-redundant memory selection circuit B51-7
and 41-7, sub-redundant memory selection circuits 31-8 and 41-
The same applies to each set of 8.

Therefore, an address signal specifying the address of one predetermined defective memory cell is detected by one of these sets, and the selected decoder recess B34-n is always delivered to the output node N1.

Based on selection signals SnL and SnR of 44-n, redundant signals NRDBmL and NRDBmR of sub-redundant memories 31-n and 41-n of the set are transmitted.

Next, the operation will be explained.

For example, in a set of sub-redundant memory selection circuits 31-8 and 41-8, a signal is sent to fuse circuits 3B-8 and 43-8.
Among the fuses that have been blown, address signals Ala and A2
a, A3a, -A4a, A5a, A6a, A
N%103FE733-8A with 7a as gate input
, 43-8A, fuse 33 connected to 1~rain.
-8B and 4B-8B are cut.

At this time, address A1 is input to address buffer circuit fi421.22 in synchronization with clock signal CK11.
If iN''-A10IN specifies the address of a defective memory cell and all of its signal levels are "1", then the address signals Ala to A3a output from the address buffer circuit 21 are 1", Address signal A
1b to A3b become "°○'°, and address signals A48 to .A10a are output from the address buffer circuit 22.
or 1, the address signals A/II) to A10t) are "0".
°°.

Then, each sub-redundant memory selection circuit, )Ln.

4i n, each decoder circuit 34-n, 44-
Among the sub redundant memory selection circuits 34-8 and 44-8, the selection signals SmL and SmR are "o".
Only the selection signal 571 and S7R, all others are "
1”.

The decoder circuit 34-old 44-n that outputs the selection signals Sn+L and SmR with a signal level of "1" is included in the circuits other than the sub-redundant memory selection circuit B51-8 and 41-8; that is, the sub-redundant memory These are selection circuits 31-1 to 31-7 and 41-1 to 41-7.These sub redundant memory selection circuits f431-1 to 31-7 and 41-1 to 41-7
Then, select signal SO[~S6L, 5OR-, -86R
are all "°1", so each transmission means 36-n, 46
-n (n=1 to 7), each NOR gate 36-
Since the outputs of nA and 46-nA (n=1 to 7) are fixed at "0", the NOR gates 36-nB and 46-nB
(n=1 to 7) are always off, and the fuse circuit 33
-n, 43-n (n=1 to 7) redundant signal NRD
BmL and NRDBmR are not transmitted to the output node N1 side, and their outputs are separated from the output node N1.

On the other hand, the selection signals S7L and S of the signal level or °゛0°'
A sub-redundant memory selection circuit having a decoder 34-8.44-8 that outputs 7R &J31-8.4]8 is
The selection signals S7L and S7R are the transmission means 36-8°4
The SOR gates 6-8 and 46-8A are manually powered. Also, those fuse times H338, 4
In 3-8, NMO8FET33-8A, 4B-
8A on/off operation and fuse 33 8B, 43
Due to the disconnection state setting of 8B, the clock signal CK1
By the precharging operation of PMOSFET35-8, 45-8 in synchronization with 2, redundant signals NRDB7L and NRDB7R of signal level "1'" are output. These redundant signals NRDB7L and NRDB7R are transmitted to the transmission means 36, respectively.
8.46 8 NOR game l-36-8A.

46-8A.

At this time, each sub-redundant memory selection l1B31-8゜'4
1-8, a set of two NMO5FET378,
In the set of NMOs 547-8, one is turned on and the other is turned off, and the signal level "1°" of the redundant signals NRDB7j and NRDB7R is strengthened.

NO where the selection signal 571 with a signal level of “0°°” is input.
The R gate 36-8A receives the redundant signal NRDB which is also input.
7L is inverted and output, and its NOR game 1"36-8A
The output of NMO5FE T 36-8 B becomes 0".
turns off.

Similarly, the NOR gate 46-8A to which the selection signal S7R with a signal level of "0°" is input inverts and outputs the redundant signal NRDB7R which is also input.
-8A output becomes “0”, NOR gate 46-8B
turns off.

In this way, sub-redundant memory selection circuit 31-8.4
Only the redundant signals NRDB7L and NRDB7R at 1-8 are sent to the output node N by the transmission means 36-8, 46-8.
1. Therefore, each sub-redundant memory selection circuit 83
1-n and 41-n generate a redundant memory activation signal NRDB having a signal level of "1'° at the output node N1.

Redundant memory activation signal NR generated as above
DB is input to the address decoder 3 and inactivates the row address decoder 3a and column address decoder 3b,
The signal is input to the redundant address decoder 6 and activates the redundant column address decoder 6a and the redundant row address decoder 6b.

Redundant column address decoder 6a and redundant row address decoder 6 activated by redundant memory activation signal NRDB
b selects the address of a redundant memory cell in the redundant memory area 5 based on address signals A8a to A10b, for example, and activates the redundant memory cell. Then, by accessing the activated redundant memory cell via the R/W input/output circuit 4, it is possible to write the write data DIN or read the read data DOυ.

As described above, the redundant memory area is selected, and the defective memory cell in the main memory area 1 is replaced by the redundant memory area 5.
Normally, when accessing the raw memory area 1, each sub-redundant memory selection circuit 31-n, 41-n sets the output node N1 to the ground potential. The main memory area 1 can be selected by connecting to the fuse circuit 3B-n.

By programming the address of a defective memory cell according to the disconnected state of fuses 33-nA and 43-nB of 43-n, each sub-redundant memory selection circuit 31 -n,
41-n, the set of the selection signal SmL and the redundant signal NRDBmL or the set of the selection signal SmR and the redundant signal NRDBmH may both be 0°'.

If this is done, the corresponding set of transmission means 36-n
NMO8FET36-nB and N of the transmission means 46-n
MO3FET46 nB turns on and output node N1
is connected to the ground potential, redundant address decoder 6 is inactivated, and address decoder 3 is activated.

This embodiment has the following advantages.

(A> In the redundant circuit system of this embodiment, the sub-redundant memory selection circuit 31-n divided for addresses other than the second address
and 41-n, an address specifying one defective memory cell is detected, and each of the sets is selected by a decoder circuit 34-n, 44-n.

2, each set of sub-redundant memory selection circuit 31-n
, 41-n do not necessarily need to be placed in the same area, but can be placed in different areas. As a result, for example, as shown in the layerer 1 to layout example in FIG. 6, for the second address signal, the address signals Ala to A3
Sub redundant memory selection time Fl! r31-1~
31-8 are placed together and adjacent to each other, and the address signal A
Sub redundant memory selection circuit 41- which inputs 4a to A7b.
1 to 41-8 can be arranged adjacent to each other. Therefore, the number of wires in the wiring area for the address signal lines of each of the →cubic redundant memory selection circuits 31-n and 41-n can be reduced to 14, for example, instead of 20 in the conventional art.

In addition, in the redundant circuit system of this embodiment, each sub-redundant memory selection circuit 31-old 4L-11 is connected to the transmission means 36n, 46-
n, and the transmission means 36-n, 46-n are provided with redundant signals N R, D B m based on the selection signals Sml, SmH.
By transmitting L, NRD B IIIR to the output node N], the redundant memory activation signal NRDB is generated. Therefore, in the wiring area for generating the redundant memory activation signal NRDB on the output side of each sub-redundant memory selection circuit 31-n, 4L-11, eight wirings are required in the conventional redundant circuit system. It can be made into one part of the output node N1.

Therefore, as can be seen from the above, in the semiconductor memory device using the redundant circuit system of this embodiment, the number of wires in the wiring area is reduced to 15 as compared to the conventional 25 trees, as shown in FIG. With the effect of reducing the number of wires in the wiring region, it is possible to reduce the chip area of the semiconductor memory device, that is, the chip size.

(B) In the case of this embodiment, when the main memory area 1 is used, the wiring load of the output node N1 becomes heavy, or the transmission means 36-n and 46-n are provided.
Since the charge at the output node input 1 is discharged by T36-nB and 46-nB, then MO5FET36-+1B
, 46-1] Even if the drive capability of B is increased, there is no effect on the address signal line on the address signal input side of each sub-redundant memory selection circuit &831-1"t, 41-n, and the operation is the same as before. You can expect speed.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(I) In the redundant circuit system of the above embodiment, the configuration of the semiconductor memory device shown in FIGS. 1, 5, and 6 can be modified.

For example, in the redundant circuit 30, the second address signal (for example, the address signals A1a to A7tl) is divided into two,
Eight sets of sub-redundant memory selection circuits 31n and 41-n are provided to each input the divided address signals to detect an address specifying a defective memory cell and generate a redundant memory activation signal NRDB. That's what I do. However, in this case, the address indicating a defective memory cell is detected by the plurality of sub-redundant memory selection circuits each inputting an address signal obtained by dividing the second address signal not into two but into another plurality of sections. You can also do this. Further, in the above embodiment, the case where there are eight sets of sub-redundant memory selection circuits 31-n and 41-n is illustrated, but this need not be eight sets.

Regarding the address signals, various changes can be made in terms of the number of signals, how the address signal lines are inserted, etc.

Further, the sub-redundant memory selection circuits 31-n and 41-n are
Redundant selection circuit 32-n, 42-n, fuse circuit 33-
n, 43n, decoder circuits 34-n, 44-n, precharge PMO3FETs 35-n, 45-n, transmission means 36n, 46-n, and PMO5FETs 37-n, 47
-n etc. can be changed, and the configuration of the precharge circuit 0 can also be changed as appropriate.

Furthermore, sub-redundant memory selection circuits 31-n, 41-1]
The arrangement of the layerer 1 and the precharge circuit 50 can be changed as appropriate. (II) The operation example shown in the above embodiment is a schematic example, and may be modified according to changes in the configuration, etc. It can be changed as appropriate. Further, the level setting of each signal can be changed depending on the modification of the configuration and the like.

(III) The redundant circuit system of the present invention is a dynamic RA
For example, static RAM and ROM
It can be widely applied to various semiconductor memory devices, etc.

(Effects of the Invention) As described above in detail, according to the first invention, the plurality of sub-redundant memory selection circuits are provided, and each sub-redundancy memory selection circuit includes the decoder circuit, the fuse circuit, and the transmission means. A predetermined combination of sub redundant memory selection circuits C3 detects an pulse specifying a defective memory cell and generates the redundant memory activation signal. Therefore, the predetermined combination of sub-redundant memory selection circuits does not necessarily need to be arranged in the same area, and a discrete layout arrangement becomes possible.

Further, the output nodes in each sub-redundant memory selection circuit are connected in common, and the redundant memory activation signal is generated by transmitting the redundant signal to the output node by the transmitting means based on the selection signal. Therefore, the output side wiring of each sub-redundant memory selection circuit only needs to be one wire, for example, the common connection portion of the output node.

Therefore, with the redundant circuit system of the present invention, it is possible to reduce the number of wires in the wiring area and improve routing efficiency.
It is possible to achieve reduction in memory chip size. Furthermore, by providing the transmission means, it is possible to expect an operating speed at least equivalent to that of the conventional redundant circuit system.

According to the second invention, among the sub-redundant memory selection circuits, the sub-redundant memory selection circuits having fuse circuits for decoding the same second address signal are arranged adjacently together, so that wiring It is possible to promote low source efficiency in the number of wiring lines in the area and to achieve convex optimization of wiring routing.

[Brief explanation of the drawing]

Figure 1 is a schematic configuration diagram of a semiconductor memory device for explaining a redundant circuit system showing an embodiment of the invention. Figure 72 and Figure 2 are semiconductor memory devices for explaining a conventional redundant circuit system. A configuration block diagram schematically showing an example of the configuration of
Figure 3 is a schematic UgJ#1 diagram of the redundant circuit in Figure 2,
4 is a diagram showing an example of the layout arrangement of the redundant circuit in FIG. 3, FIG. 5 is a schematic circuit diagram of the redundant circuit in FIG. 1, and FIG.
The figure is a diagram showing an example of the layout arrangement of the redundant circuit shown in FIG. DESCRIPTION OF SYMBOLS 1...Main memory area, 3...Address decoder,...Redundant memory area, 6...Redundant address decoder, 30...Redundant circuit, 31-1 to 41-8...Sub redundancy Memory selection circuit, 33-1 to 43-8...Seuse circuit, 33LB to 4B-8B...Fuse, 34-1
~44-8...decoder circuit, 36-1~46-8...
・Transmission means, A8a to A10a, A8b-, -A1
0b...first address signal, -A1a to A7a,
Alb~A? b...Second address signal, SQL~
S7L, SOR-S7R...selection signal, RDBO
L~NRDB7L, NRDBOR~in RDB7R...
Redundant signal, NRDB...Redundant memory activation signal.

Claims (1)

[Claims] 1) A redundant memory area having a redundant memory cell to be used in place of a defective memory cell in a main memory area selected by a plurality of address signals, and a part of the plurality of address signals being decoded. a redundant address decoder that selects a redundant memory cell in the redundant memory area using a redundant address decoder; and an address decoder that detects the address signal that designates the defective memory cell and selects an address for the main memory area based on the detection result. In a redundant circuit system comprising a plurality of redundant memory selection circuits that output a redundant memory activation signal that deactivates and activates the redundant address decoder, each of the redundant memory selection circuits outputs a redundant memory activation signal that deactivates and activates the redundant address decoder. a decoder circuit that decodes the first address signal divided into first and second address signals and outputs a selection signal; and a decoder circuit that decodes a part of the second address signal using a preprogrammed fuse. A plurality of sub redundant memory selection circuits each having a fuse circuit that outputs a redundant signal and a transmission means that transmits the redundant signal to an output node based on the selection signal, A redundant circuit system characterized in that output nodes are commonly connected to generate the redundant memory activation signal. 2) The redundant circuit system according to claim 1, wherein among the sub-redundant memory selection circuits, those having fuse circuits for decoding the same second address signal are arranged adjacently together.