JP2939783B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display,
The present invention relates to a method for manufacturing a thin film transistor used for an L display or the like.

[0002]

2. Description of the Related Art An example of a conventional method for manufacturing a thin film transistor will be described below with reference to the drawings. FIG.
(c) is a schematic sectional view of a general thin film transistor.
Substrate 1, gate electrode 2, gate insulating film 3, semiconductor film 4,
Highly doped semiconductor film 6, conductive film (including diffusion barrier film)
7 and the upper insulating film 5 are main constituent elements. A Cr film as the gate electrode 2, a silicon nitride film as the gate insulating film 3 and the upper insulating film 5, an amorphous silicon (hereinafter abbreviated as a-Si) film as the semiconductor film 4,

[0003]

## EQU1 ## As the highly doped semiconductor film 6, an n.sup. ^{+ A} -Si film,

As the conductive film 7, a Ti / Al two-layer film (the Ti film is a diffusion barrier layer and contacts a heavily doped semiconductor film) is used.

A manufacturing process for fabricating the above structure is shown in FIG.
This is shown in (a), (b) and (c) and will be described in detail below. First, as shown in FIG. 2A, in one photolithography step, a silicon nitride film of the upper insulating film 5 is formed by wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride, each in a ratio of 1: 6. At this time, in order to reduce the parasitic capacitance (Cgs) caused by the overlap between the gate electrode and the source / drain electrodes, it is common to pattern the upper insulating film 5 to fill the gate width by backside exposure.

After that, as shown in FIG. 2B, the semiconductor film 4 is patterned again by a photolithographic process. This is because it is necessary to remove the a-Si film having a small light transmittance before forming a transparent conductive film (such as an ITO film). This pattern is formed in a shape including the pattern of the upper insulating film 5 formed in the previous step. The etching is a mixture of hydrofluoric acid and nitric acid in the wet etching method, and SF ₆ , Cl ₂ and BCl _{3 in the} dry etching method.
This is performed by a plasma of a gas composed of a combination of the above.

[0007]

Thereafter, as the highly doped semiconductor film 6, an n ⁺ a-Si film is formed by a plasma CVD method or the like, or is formed by an ion implantation method or the like.

Next, as a conductive film 7 (source / drain electrodes), a Ti / Al two-layer film is formed by sputtering or the like and patterned (for example, “Flat Panel Display '90” Nikkei BP, pp. 146-155).

[0009]

In the conventional manufacturing method as shown in the above-mentioned example, in order to pattern the upper insulating film and the semiconductor film, independent photolithographic etching steps are employed, and a total of two times are employed. Requires a photolithographic process and an etching process. However, it is clear that the above two types of patterns are close to each other graphically, and the two-step process is not efficient from the viewpoint of the manufacturing cost and the yield of the process. If the upper insulating film and the semiconductor film can be patterned at one time, the manufacturing process can be significantly shortened, which is effective. In addition, the surface of the semiconductor film is contaminated in the step of removing the resist film, or the surface layer is unnecessarily etched, thereby causing damage such as deterioration of transistor characteristics and variation in ON current of the transistor. There was also a problem. From this point, it can be said that the smaller the number of photolithography steps, the better.

The present invention has been made in view of the above problems, and in a thin film transistor having a gate electrode, a gate insulating film, a semiconductor film, and an upper insulating film, the photolithographic process is reduced by patterning the upper insulating film and the semiconductor film, and the manufacturing process is shortened. It is an object of the present invention to provide a method for manufacturing a thin film transistor in which characteristics are stabilized.

[0011]

In order to solve the above-mentioned problems, a method of manufacturing a thin film transistor according to the present invention is provided on a substrate.
Amorphous as gate electrode, gate insulating film and semiconductor film
Silicon film and silicon nitride film as upper insulating film
Are sequentially formed, and a photoresist of a predetermined pattern is formed thereon.
Is formed, and CF ₄ and CHF ₃ are used as main component gases.
In the plasma containing, the silicon nitride film and the amorphous
Characterized by continuous etching of silicon film
Things.

Further, according to the method of manufacturing a thin film transistor of the present invention , a gate electrode, a gate insulating film and a semiconductor film are formed on a substrate.
Amorphous silicon film and upper insulating film
Silicon nitride films are sequentially formed, and a predetermined pattern is
After forming the photoresist, SF ₆ and CHF ₃
In a plasma containing as a main component gas, the silicon nitride
The amorphous silicon film and the amorphous silicon film successively.
It is characterized by that.

Also, a method of manufacturing the thin film transistor of the present invention
The method uses a gate electrode, a gate insulating film, and a semiconductor film on a substrate.
Amorphous silicon film and upper insulating film
Silicon nitride films are sequentially formed, and a predetermined pattern is
After forming the photoresist, SF ₆ , CF ₄ and
Gas plasma composed mainly of a combination of CHF ₃
Dry etching the silicon nitride film in
When You comprising the step of dry-etching the amorphous silicon film by a plasma of a gas mainly composed of a combination of SF _6, Cl ₂ and BCl ₃ is consists <br/>
Things.

Also, a method of manufacturing the thin film transistor of the present invention
The method uses a gate electrode, a gate insulating film, and a semiconductor film on a substrate.
Amorphous silicon film and upper insulating film
Silicon nitride films are sequentially formed, and a predetermined pattern is
After forming the photoresist, the hydrofluoric acid and
The silicon nitride film is wetted with a mixed solution of monium or the like.
Etching, SF ₆ , Cl ₂ and BCl
By the plasma of the gas whose main component is composed of _three combinations
Dry etching the amorphous silicon film
It is characterized by including a step.

[0015]

According to the present invention, the upper insulating film and the semiconductor film of a thin film transistor having a gate electrode, a gate insulating film, a semiconductor film and an upper insulating film are patterned by a single photolithographic process by the above-described method. Greatly minimizes the exposure of the semiconductor film surface, minimizes the formation of unnecessary oxide films, and suppresses the adsorption and contamination of impurities. Can be formed.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments will be described below in detail with reference to the drawings. 1A and 1B are schematic sectional views of a thin film transistor showing a method of manufacturing the thin film transistor according to one embodiment of the present invention in the order of steps. 11 is a substrate, 12 is a gate electrode, 13 is a gate insulating film, 14 is a semiconductor film, 15 is an upper insulating film, 16 is a highly doped layer, and 17 is a source / drain electrode. As the gate electrode 12, a Cr film, a gate insulating film 13, and an upper insulating film 1
5 is a silicon nitride film, semiconductor film 14 is an amorphous silicon film (a-Si),

[0017]

## EQU3 ## As the highly doped layer 16, an n ⁺ a-Si layer formed by ion implantation,

As the source / drain electrodes 17, a two-layer film of a titanium film and an aluminum film was used.

The upper insulating film 15 is a silicon nitride film formed by a PCVD method, the semiconductor film 14 is an amorphous silicon film formed by a PCVD method, and the source / drain electrodes 17 are titanium films formed by a sputtering method. The manufacturing method in the case of a two-layer film of aluminum and an aluminum film will be described in detail.

First, in the first embodiment, the positive resist O
After forming a predetermined pattern with FPR-800 (manufactured by Tokyo Ohka Co., Ltd.), a parallel plate type dry etching apparatus (RF power source 13.56
MHz), the upper silicon nitride film and the a-Si film were dry-etched. As etching conditions, as shown in (Table 1), 170 sccm of CF _4, 30 SCCM of CHF _3, and He
Was introduced at 100 SCCM, the pressure was set to 0.2 Torr, and 2 kW (0.8 W / cm ² ) was supplied as RF power. The etching rate and uniformity under these conditions are shown in the column of etching characteristics. The etching rate ratio between the upper insulating film SiN film and the underlying a-Si film is about 2. The thickness of the SiN film is 2000 °, a-Si
The thickness of the film was 500 °, and the etching was performed for 250 seconds. N ₂
The state of etching can be monitored by the emission spectrum (337 nm, 674 nm or 715 nm) of the molecule, and the signal level decreases when the etching of the upper silicon nitride film is completed.
It increases again when the etching of the i-film is completed. Therefore, the underlying gate insulating film is not excessively etched by excessive etching. In this embodiment, the emission spectrum (715 nm) is monitored, and after the emission peak decreases and rises again, over-etching is performed for about 20 seconds.

Thereafter, the resist film was peeled off and washed, and phosphorus (P) as an n-type dopant was implanted in an ion doping apparatus (mass non-separable type). The gas used was diluted with H ₂ ,
It was PH ₃ at a concentration of 5%, and was implanted under the conditions of an acceleration voltage of 8 kV and a dose of 2 × 10 ¹⁵ ions / cm ² . Thereafter, the resist was peeled off, a Ti / Al electrode was formed, and the transistor characteristics were measured after annealing at 250 ° C. for 30 minutes. The results are shown in (Table 2).

The numerical values in the table are the average values of 12 evaluation transistors arranged on the entire surface of a 100 mm circular substrate, and the measured values of the transistors manufactured by the conventional manufacturing method are shown for comparison. In the conventional manufacturing method, the silicon nitride film is wet-etched in the first photolithography step,
The a-Si film was wet-etched in the second photolithography step. Others are manufactured by the same method as this example. Among the transistor characteristics, the gate rise voltage (V _t ) is smaller by the manufacturing method of the present invention,
The N current (I _on ) and the OFF current (I _off ) are comparable. In addition, the result that the variation of the mobility μ was substantially the same was obtained.

In the above embodiment, a mixed gas of CF ₄ / CHF ₃ / He was used as the dry etching gas. Of these, He is an inert gas, and although not necessarily required, the shape of the etching It is added for the purpose of controlling the uniformity of etching, the fine structure of the etched surface, the stability of plasma, and the like.

[0024]

[Table 1]

[0025]

[Table 2]

Next, a second embodiment will be described (however, omitted in Tables 1 and 2). It uses SF ₆ instead of a CF ₄ gas as described above, in the same manner as the first embodiment, once the etching the upper silicon nitride film a-
The Si film was etched.

In terms of shape, the contact region of the a-Si film
(Contact length d × channel width w) is an important parameter. In the first and second embodiments, as shown in (Table 2), the contact length d is only about 0.1 μm. This is because CF ₄ (or SF ₆ ) / CH is used as a dry etching gas.
This is because the etching is performed anisotropically due to the mixed gas of F ₃ / He, and the cross-sectional shape is almost vertical.

[0028]

## EQU00004 ## The reason why good transistor characteristics were obtained as a result is that a contact with low contact resistance (n ⁺ a-Si / Ti interface) was realized.

For this purpose, it is important to optimize the ion doping conditions and to select a metal having good contact properties such as Ti, Zr and Hf.

Next, a third embodiment will be described. First, the silicon nitride film as the upper insulating film was dry-etched in the same manner as in the first embodiment. However, the dry etching condition is lower than that of the first embodiment (a-Si
A condition with a high selectivity to the membrane was used.

As shown in Table 1, as an etching gas, CF ₄ was 120 SCCM, CHF ₃ was 30 SCCM, and He was 15 SCCM.
0SCCM was introduced, the pressure was set to 0.2 Torr, and 2 kW (0.8 W / cm ² ) was supplied as RF power. The etching rate and uniformity under these conditions are shown in the column of etching characteristics. The etching rate ratio between the upper insulating film SiN film and the underlying a-Si film is about 3.2. The thickness of the SiN film is 2000 Å, a-S
The thickness of the i-film was set to 500 °, and the etching was performed for 140 seconds. N ₂
The state of etching can be monitored by the emission spectrum of molecules (337 nm, 674 nm, or 715 nm), and the signal level decreases when the etching of the upper silicon nitride film is completed. Therefore, the underlying a-Si film is not excessively etched by excessive etching. In this example, the emission spectrum (715 nm) was monitored, and after the emission peak decreased, about 20
Second over-etching.

Next, Cl ₂ and BC ₂ are placed in the same vacuum apparatus.
The plasma consists gas combinations l _3, and the a-Si film of the semiconductor film is dry-etched. ₃₀ SCCM of Cl ₂ and 240 SCCM of BCl ₃ were introduced as an etching gas, the pressure was set to 0.15 Torr, and RF power was 1.2 kW (0.8 W / c).
m ² ) The etching rate and uniformity under these conditions are shown in the column of etching characteristics. Under this condition, the selectivity with respect to the underlying SiN film is 3 or more, which is better than that of the first embodiment. Therefore, in this embodiment in which etching is performed twice, the number of steps is increased as compared with the case of the first embodiment in which etching is performed once, but there is an advantage that the selectivity with respect to the base can be increased.

Next, a fourth embodiment will be described. First, the silicon nitride film of the upper insulating film was wet-etched with a 1: 6 mixed solution of hydrofluoric acid and ammonium fluoride. After washing and drying, the next plasma composed gas a combination of Cl ₂ and BCl _3, and the a-Si film of the semiconductor film is dry-etched. Cl ₂ as an etching gas
Was introduced at ₃₀ SCCM and BCl ₃ at 240 SCCM, the pressure was set to 0.15 Torr, and 1.2 kW (0.8 W / cm ² ) was supplied as RF power.
Under this condition, the selectivity with respect to the underlying SiN film is 3 or more, which is better than that of the first embodiment. Therefore, in this embodiment in which etching is performed twice, the number of steps is increased as compared with the case of the first embodiment in which etching is performed once, but there is an advantage that the selectivity with respect to the base can be increased.

As shown in Table 2, among the transistor characteristics, the gate rise voltage (V _t ) is larger than that of the first embodiment, the ON current (I _on ) is about the same, and the OFF
The current (I _off ) is rather small. In addition, the variation of the mobility μ was slightly larger than that of the first embodiment and that of the conventional manufacturing method. Further, as shown in Table 2 (Table 2), since the upper insulating film recedes by side etching in the first wet etching, the contact length d can be as large as about 0.5 μm.
This can be controlled to some extent by the over-etching time.

As described in the above embodiments, in the method of manufacturing a thin film transistor according to the present invention, in a thin film transistor having a gate electrode, a gate insulating film, a semiconductor film and an upper insulating film, the upper insulating film and the semiconductor film are formed once. It is characterized in that it is patterned in a photolithographic process.

In the above embodiment, a-S
Although the i film was used, the same effect can be expected even with a polycrystalline silicon film. Further, even if the upper insulating film and the gate insulating film are films other than the SiN film, it can be realized by appropriate selection of the etching method.

[0037]

As described above, according to the present invention, in a thin film transistor having a gate electrode, a gate insulating film, a semiconductor film, and an upper insulating film, the upper insulating film and the semiconductor film are formed in one.
Since patterning can be performed in one photolithographic process, the former photolithographic process can be realized in one place instead of two times in the past, so that the process is greatly simplified and the effect of cost reduction is obtained. Furthermore, the number of times and time the semiconductor film is exposed to an etching solution or a resist stripping solution are reduced, a cleaner semiconductor-metal interface can be formed, and the gate threshold voltage (Vt) can be reduced. It has the effect of improving.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view of a conventional thin film transistor in a process order.

[Explanation of symbols]

11 ... substrate, 12 ... gate electrode, 13 ... gate insulating film,
14: Semiconductor film, 15: Upper insulating film, 16: Highly doped layer, 17: Source / drain electrode.

Claims (4)

(57) [Claims] 1. A on a substrate, a gate electrode, a gate insulating film,
Amorphous silicon film and upper layer as semiconductor film
A silicon nitride film is sequentially formed as an edge film, and
After forming a patterned photoresist, CF ₄ and
And CHF ₃ as a main component gas in a plasma.
Successively etch silicon nitride film and amorphous silicon film
A method for manufacturing a thin film transistor, comprising: A gate electrode, a gate insulating film,
Amorphous silicon film and upper layer as semiconductor film
A silicon nitride film is sequentially formed as an edge film, and
After forming a photoresist with a fixed pattern, SF ₆ and
In plasma containing fine CHF ₃ as a main component gas, the <br/> method of manufacturing a thin film transistor you, characterized in that the silicon film and A molar Fas silicon nitride film are continuously etched. 3. A gate electrode, a gate insulating film,
Amorphous silicon film and upper layer as semiconductor film
A silicon nitride film is sequentially formed as an edge film, and
After forming a photoresist of a constant pattern, SF ₆ , C
Of gas composed mainly of a combination of F ₄ and CHF ₃
Dry etching the silicon nitride film in plasma
And a combination of SF ₆ , Cl ₂ and BCl _3.
Amorphous by the plasma of the constituent gas
Method for manufacturing a thin film transistor you, characterized in that the silicon film comprising the step of dry etching. 4. A gate electrode, a gate insulating film,
Amorphous silicon film and upper layer as semiconductor film
A silicon nitride film is sequentially formed as an edge film, and
After forming a photoresist with a constant pattern,
Silicon nitride with a mixed solution of ammonium nitride, etc.
A step of wet etching the film, the thin film transistor characterized in that the amorphous silicon film by plasma of the main component is composed of a gas in combination with SF _6, Cl ₂ and BCl ₃ comprising the step of dry-etching Production method.