JP2927244B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a buried diffusion layer is formed before a gate oxide film is formed, and a method for securing an effective channel length even if the channel length is short. It is used for a method of manufacturing a nonvolatile memory, particularly a memory using a floating gate transistor.

[0002]

2. Description of the Related Art Conventionally, a method of manufacturing a semiconductor device in which a buried diffusion layer is formed before forming a gate oxide film is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-283721. It is used for manufacturing a nonvolatile semiconductor memory device for forming a buried diffusion layer.

FIG. 5 shows an example of a configuration of a nonvolatile semiconductor memory device having a buried diffusion layer structure. First
The second local bit lines 500 and 501 and the common local source line 502 are configured to use a buried diffusion layer as a wiring.

The first and second local bit lines 500 and 501 are selected by select transistors 503 and 504, respectively, and are connected to global bit lines 505 and 506, respectively.
Connected to. A common local source line 502 is selected by a select transistor 507 and connected to a global source line 508.

The local bit line and the common local source line have a large number of storage elements such as floating gates and floating gates.
A transistor is connected. For example, the transistor 509 in the first column has a drain connected to the first local bit line 500 and a source connected to a common local source line 502.
Is connected to Transistor 510 in second column
Has a drain connected to a second local bit line 501 and a source connected to a common local source line 502.
The control gate of this floating gate transistor is connected to word lines WL0 to WLN.

Next, an example of the structure of a cell portion of a conventional nonvolatile memory device having a buried diffusion layer structure will be described with reference to FIGS. 6A and 6B. FIG. 6A is a plan view, and FIG. 6B is a sectional view thereof. The cell structure is formed between the element isolation films 600.
Two drain buried layers 601 and one source buried layer 6
02 exists. Below the buried layers 601 and 602, a drain diffusion layer 603 and a source diffusion layer 60 are respectively provided.
There are four. These embedded diffusion layers are used as wiring. Drain diffusion layer 603 corresponds to local bit lines 500 and 501 in FIG.
Correspond to the common local source line 502 in FIG. The two silicon dioxide layers 605 correspond to the tunnel films of the two transistors 509 and 510 in FIG. Floating gate 606 and interpoly film 6
07 and the control gate 608 are stacked in this order. The control gate 608 is used as a wiring, and is used as a word line in FIG.

Next, FIGS. 7A to 7D and FIGS.
Is an example of a conventional method for manufacturing a nonvolatile memory device having a buried diffusion layer structure. First, in FIG. 7A, a thin first silicon dioxide layer 701 having a thickness of about 50 nm is formed on the surface of a silicon substrate 700 by a thermal oxidation method, and a thick silicon nitride layer having a thickness of about 300 nm is formed on the surface of the first silicon dioxide layer 701. It is formed by an evaporation method. This silicon nitride layer is patterned by using a lithography process and a dry etching process to form a silicon nitride pattern 702. This silicon nitride pattern 70
2 is used as a mask to perform arsenic ion implantation 703 to form a diffusion layer 704.

Next, referring to FIG. 7B, in order to activate the implanted arsenic, thermal annealing is performed in, for example, a nitrogen atmosphere. At that time, as described later, a high concentration arsenic layer 705 is formed on the surface of the diffusion layer 704.

Thereafter, as shown in FIG. 7C, thermal oxidation is performed using the silicon nitride pattern 702 as a mask to form a thick second silicon dioxide layer 706 of about 100 nm on the diffusion layer 704. Subsequently, the silicon nitride pattern 702 and the thin first silicon dioxide layer 701 are removed by a wet etching process to obtain a shape as shown in FIG. 7D.

Then, as shown in FIG. 8A, a thin third silicon dioxide layer 707 having a thickness of 20 nm or less is formed by a thermal oxidation method.
To form This thin third silicon dioxide layer 707 becomes a tunnel film of the nonvolatile semiconductor memory device.

Then, as shown in FIG. 8B, after depositing a polycrystalline silicon film by, for example, a chemical vapor deposition method of about 150 nm, a polycrystalline silicon pattern 709 is formed by using a lithography process and a dry etching process. This polycrystalline silicon pattern 709 becomes a floating gate of the nonvolatile semiconductor memory device. FIG. 8C shows a top view at the stage of FIG. 8A.

[0012]

In this method, the buried diffusion layer is formed prior to the formation of the gate oxide film. However, when the channel length is short, particularly when the channel length is shorter than 0.4 μm, a sufficient effect is obtained. There was a problem that the channel length could not be secured and normal operation of the transistor was not performed.

That is, in this manufacturing method, when arsenic is activated as shown in FIG. 7B, a thin first silicon dioxide layer 701 is present on the surface of the diffusion layer 704 to inhibit the outward diffusion of arsenic. A high concentration arsenic layer 705 is formed on the surface of the substrate. Therefore, before forming the tunnel film,
As shown in FIG. 7D, this high concentration arsenic layer 705 exists at both ends of the channel region. In a subsequent thermal oxidation step for forming a tunnel film, the high-concentration arsenic layer 705 is acceleratedly oxidized, and as shown in FIG. 8A, a thicker silicon dioxide layer 70 than a thin third silicon dioxide layer 707 (tunnel film).
8 are formed at both ends of the channel. Due to the thick silicon dioxide layer 708 itself and segregation of arsenic occurring during its oxidation (release of arsenic from the thick silicon dioxide layer 708 into the channel region during thermal oxidation), arsenic spreads toward the inside of the channel region. Due to these phenomena, channel narrowing occurs, making it impossible to secure an effective channel length.

That is, the present invention relates to a method of manufacturing a semiconductor device in which a buried diffusion layer is formed before a gate oxide film is formed.
It is an object of the present invention to provide a manufacturing method capable of securing a sufficient effective channel length even when the length is shorter than m.

[0015]

According to the present invention, a dopant is ion-implanted into a semiconductor substrate, and a diffusion layer to be a buried diffusion layer is formed in a subsequent step. And a step of forming, on the surface of the diffusion layer after activation, a thermal oxide film thicker than an oxide film and a gate oxide film provided on the surface when the dopant is implanted to form a buried diffusion layer. In the method of manufacturing a device, the activation step is a step of performing thermal annealing in a state where only the diffusion layer is exposed on the surface of the semiconductor substrate.

Further, according to the present invention, there is provided a step of forming a first insulating film on a surface of a semiconductor substrate, and forming a second insulating film having an opening at a portion for ion implantation on the first insulating film. Performing a step of ion-implanting a dopant to form a diffusion layer; removing the first insulating film present on the surface of the diffusion layer, exposing the diffusion layer to the surface; Thermally annealing the exposed substrate, activating the dopant, thermally oxidizing the surface of the diffusion layer, forming a thermal oxide film, and the first insulating film and the second Removing the second insulating film, and thermally oxidizing the channel portion surface from which the first and second insulating films have been removed, and forming a gate oxide film on the channel portion surface,
Forming a gate electrode on the gate oxide film.

In the present invention, when the implanted dopant is activated by thermal annealing, the surface of the diffusion layer is exposed to the surface for activation. At this time, outward diffusion of the implanted dopant element occurs on the surface of the diffusion layer, and the concentration of the element near the surface decreases. Therefore, gate oxide film (tunnel film)
In the thermal oxidation step (FIG. 2B) for forming GaAs, the accelerated oxidation on the diffusion layer and the amount of segregated implanted elements are suppressed, and the narrowing of the channel is suppressed.

Next, the effect of suppressing accelerated oxidation by exposing the surface of the diffusion layer and activating the diffusion layer according to the present invention will be described with reference to FIG. First, after a silicon dioxide layer is formed to a thickness of 40 nm on a silicon substrate, arsenic atoms are added to 5 × 10 ¹⁵ / c.
A sample having a diffusion layer formed by implanting m ² ions is prepared.
The sample indicated by a white circle in FIG. 3 is obtained by performing activation in a nitrogen atmosphere while keeping the silicon dioxide layer, and then performing thermal oxidation. The sample indicated by a black circle in FIG. 3 is obtained by removing the silicon dioxide layer by wet etching, activating in a nitrogen atmosphere, and then performing thermal oxidation. Activation was performed at 950 ° C. for 60 minutes for both samples.

In FIG. 3, the vertical axis represents the thickness of the silicon dioxide layer on the diffusion layer, and the horizontal axis represents the thickness of the silicon dioxide layer when the same thermal oxidation treatment is performed on a silicon substrate without ion implantation. That is, FIG. 3 shows the degree of acceleration of oxidation. From FIG. 3, it can be seen that removing the oxide film on the diffusion layer reduces the degree of oxidation acceleration. This is because outward diffusion occurs on the surface of the diffusion layer and the arsenic concentration on the surface of the diffusion layer is reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The substrate used in the present invention is a substrate on which an insulating film can be formed by thermal oxidation, and is preferably a silicon substrate.

The first insulating film (the film on the diffusion layer to be removed) can be formed of silicon dioxide which can be formed in a thermal oxidation step, silicon dioxide containing nitrogen atoms, or the like. The second insulating film may be a film that functions as a mask at the time of ion implantation, and can be formed using a material such as silicon nitride with an appropriate thickness.

The method of removing the film on the diffusion layer is not limited to wet etching, but may be dry etching.

The dopant material used to form the diffusion layer by ion implantation is not limited to arsenic, and other dopants such as phosphorus that cause accelerated oxidation and segregation like arsenic and cause channel narrowing problems Then, the present invention can be effectively applied.

The gate oxide film (tunnel oxide film) may be formed of a silicon oxide layer containing nitrogen atoms. This is because a film can be formed by a thermal oxidation process substantially similar to that of silicon dioxide.

The present invention is used for manufacturing a nonvolatile memory as shown in FIG. 5, particularly a memory using a floating gate transistor. However, the present invention is not limited to this. The present invention can be applied to any semiconductor manufacturing method that causes a problem of channel narrowing.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to FIGS. 1A to 1D and 2A to 2D.

First, referring to FIG.
The first silicon dioxide layer 1 having a thickness of about 50 nm on the surface 1
01 (first insulating film) is formed by thermal oxidation, and a thick silicon nitride layer (second insulating film) of about 300 nm is formed on the surface of the first silicon dioxide layer 101 by chemical vapor deposition. This silicon nitride layer is patterned using a known lithography process and a dry etching process to form a silicon nitride pattern 102.

Using the silicon nitride pattern 102 as a mask, arsenic ion implantation 103 is performed to form a diffusion layer 104. Prior to the activation of the implanted arsenic, the first silicon dioxide layer 101 on the diffusion layer 104 is removed by a known wet etching process to obtain a shape as shown in FIG. 1B.

Next, as shown in FIG. 1C, in order to activate arsenic in the diffusion layer 104, thermal annealing is performed in a nitrogen atmosphere. At this time, since the surface of the diffusion layer 104 is exposed on the substrate surface, outward diffusion of arsenic 105 occurs, and the concentration of arsenic on the surface of the diffusion layer 104 decreases.

Thereafter, as shown in FIG. 1D, thermal oxidation is performed using the silicon nitride pattern 102 as a mask to form a thick second silicon dioxide layer 106 of about 100 nm on the diffusion layer 104.

Subsequently, the silicon nitride pattern 102 and the thin first silicon dioxide layer 101 are removed by a known wet etching process to obtain a shape as shown in FIG. 2A.

Thereafter, as shown in FIG. 2B, a thin third silicon dioxide layer 107 (tunnel film) having a thickness of about 10 nm, which is the same as a normal level, is formed as a gate oxide film by a thermal oxidation method. At this time, since the arsenic concentration at both ends of the channel region is low, the accelerated oxidation is suppressed, and the silicon dioxide layer 108 at both ends of the channel does not enlarge, and the arsenic segregation at the time of oxidation also spreads in the lateral direction. By being small, narrowing of the channel is suppressed.

Then, as shown in FIG. 2C, after depositing a polycrystalline silicon film by, for example, a chemical vapor deposition method of about 150 nm, a polycrystalline silicon pattern 109 (floating gate) is formed by using a known lithography process and a dry etching process. Form. FIG. 2D shows a top view at the stage of FIG. 2B.

FIG. 4 is a comparison of the effective channel length between the method according to the present invention and the conventional method. The vertical axis of FIG. 4 represents the effective channel length, and the horizontal axis represents the channel length as a design value. FIG. 4 shows that the present invention can secure an effective channel length even with a short channel length of 0.4 μm or less.

[0035]

According to the present invention, in the step of forming a thermal oxide film, channel narrowing is suppressed and an effective channel length is ensured.
Even if it is shorter than m, the effective length can be secured. Therefore, according to the present invention, high integration of a semiconductor device manufactured by a manufacturing method of forming a buried diffusion layer prior to formation of a gate oxide film can be achieved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a diagram showing the effect of suppressing accelerated oxidation by exposing a diffusion layer to the surface.

FIG. 4 is a diagram showing a comparison of the effective channel length between the present invention and the conventional method.

FIG. 5 is a diagram showing a configuration of a nonvolatile semiconductor memory device having a buried diffusion layer structure.

FIG. 6 is a diagram showing a structure of a cell portion of a nonvolatile semiconductor memory device having a buried diffusion layer structure according to a conventional technique.

FIG. 7 is a flowchart showing a method for manufacturing a nonvolatile semiconductor memory device having a buried diffusion layer structure according to a conventional technique.

FIG. 8 is a flowchart showing a method for manufacturing a nonvolatile semiconductor memory device having a buried diffusion layer structure according to a conventional technique.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 silicon substrate 101 silicon dioxide layer 102 silicon nitride pattern 103 ion implantation 104 diffusion layer 105 outward diffusion 106 silicon dioxide layer 107 gate oxide film (silicon dioxide layer (tunnel film)) 108 silicon dioxide layer at both ends of channel 109 polycrystalline silicon pattern (Floating gate)

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 29/792 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336 H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A step of ion-implanting a dopant into a semiconductor substrate and forming a diffusion layer to be a buried diffusion layer in a later step, a step of thermally annealing the implanted dopant and activating the implanted dopant, On the surface of the diffusion layer,
Oxide film and gate oxidation provided on the surface during punt implantation
Forming a thermal oxide film thicker than the film to form a buried diffusion layer, wherein the activating step exposes only the diffusion layer to the surface of the semiconductor substrate surface. A method for manufacturing a semiconductor device, comprising a step of performing thermal annealing in a state. 2. A step of forming a first insulating film on a surface of a semiconductor substrate; and a step of forming a second insulating film having an opening at a portion to be ion-implanted on the first insulating film; A step of ion-implanting a dopant to form a diffusion layer; a step of removing the first insulating film present on the surface of the diffusion layer to expose the diffusion layer to the surface; a substrate having the diffusion layer exposed to the surface Thermally activating the dopants, thermally oxidizing the surface of the diffusion layer to form a thermal oxide film, and the first insulating film and the second insulating film existing on the surface of the channel portion. Removing the first and second insulating films, thermally oxidizing the surface of the channel portion to form a gate oxide film on the surface of the channel portion, and forming a gate electrode on the gate oxide film. And a method of manufacturing a semiconductor device.