JP2733972B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly, to a silicon oxide film, a silicon nitride film, and a silicon oxide film as interlayer insulating films between polycrystalline silicon films. The present invention relates to a method for manufacturing a semiconductor integrated circuit device using an insulating film having a three-layer structure with a film.

[Summary of the Invention]

The present invention includes a first polycrystalline silicon film, an insulating film provided on the first polycrystalline silicon film, and a second polycrystalline silicon film provided on the insulating film, A semiconductor integrated circuit in which the insulating film includes a first silicon oxide film, a silicon nitride film provided on the first silicon oxide film, and a second silicon oxide film provided on the silicon nitride film In the device manufacturing method, the second silicon oxide film is formed thick by thermally implanting oxygen into the silicon nitride film and then thermally oxidizing the silicon nitride film to form the second silicon oxide film. It is something that can be done.

[Conventional technology]

EPROM (Erasable and Programmable Read Only Memor
y) and EEPROM (Electrically Erasable and Programmabl
The memory cell portion of eRead Only Memory has a structure in which a control gate (Control Gate) is provided on a floating gate (Floating Gate) via an interlayer insulating film. As a material of the floating gate and the control gate, a polycrystalline silicon (Si) film doped with an impurity is usually used.

As described above the interlayer insulating film, and a polycrystalline Si film of silicon oxide formed by thermal oxidation on the surface of the (SiO ₂₎ film, the SiO ₂
In some cases, a so-called ONO having a three-layer structure composed of a silicon nitride (SiN) film formed on the film and a SiO ₂ film formed on the surface of the SiN film by thermal oxidation is used. In this case, SiO ₂ formed on the surface of this SiN film
The thicker the film, the lower the ONO leakage current and the longer the life until the dielectric breakdown occurs.
ielectric Breakdown) is known from the measurement.

[Problems to be solved by the invention]

By the way, when manufacturing EPROM or EEPROM using the above ONO, in order to simplify the manufacturing process,
It is desirable that the above-described thermal oxidation of the SiN film be performed simultaneously with the thermal oxidation for forming the gate oxide film of the transistor of the peripheral circuit.

However, since the oxidation rate of the SiN film is extremely low, it is not possible to form a sufficiently thick SiO ₂ film on the surface of the SiN film with the oxidation time required to make the gate oxide film of the transistor in the peripheral circuit a predetermined thickness. It was difficult.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device capable of forming a thick SiO ₂ film on the surface of a SiN film.

[Means for solving the problem]

In order to solve the above problems, the present invention provides a first polycrystalline silicon film (FG), an insulating film provided on the first polycrystalline silicon film (FG), and a first polycrystalline silicon film (FG) provided on the insulating film. A first silicon oxide film (5), and a silicon nitride film (6) provided on the first silicon oxide film (5). Silicon nitride film (6)
In a method for manufacturing a semiconductor integrated circuit device comprising a second silicon oxide film (8) provided thereon, thermally oxidizing the silicon nitride film (6) after ion-implanting oxygen into the silicon nitride film (6). To form a second silicon oxide film (8).

[Action]

According to the above-described means, the oxidation rate of the silicon nitride film (6) is increased by the presence of oxygen ion-implanted into the silicon nitride film (6). The silicon oxide film (8) can be formed thick.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all drawings of the embodiment, components having the same function are denoted by the same reference numerals.

Embodiment I FIGS. 1A to 1F show an EPROM according to Embodiment I of the present invention.
The manufacturing method of is shown.

In this embodiment I, as shown in FIG. 1A, first, a surface of a semiconductor substrate 1 such as a p-type Si substrate is coated with SiO _2.
After selectively forming a field insulating film (not shown) such as a film to perform device isolation, a surface of an active region surrounded by the field insulating film is coated with, for example, SiO 2 having a thickness of about 100 °.
An insulating film 2 such as _two films is formed. Next, the insulating film 2
After a polycrystalline Si film 3 is formed thereon by, for example, CVD, the polycrystalline Si film 3 is doped with an impurity such as phosphorus (P) to reduce the resistance. Thereafter, a resist 4 having a predetermined shape is formed on the polycrystalline Si film 3 by lithography.

Next, using the resist 4 as a mask, the polycrystalline Si film 3 is anisotropically etched in a direction perpendicular to the substrate surface by, for example, reactive ion etching (RIE) to form a floating gate FG as shown in FIG. 1B. I do. Next, after removing the resist 4, an SiO ₂ film 5 is formed on the upper surface and side surfaces of the polycrystalline Si film constituting the floating gate FG.

Next, as shown in FIG. 1C, an SiN film 6 having a thickness of, for example, about 200 ° is formed on the entire surface by, for example, CVD.
A resist 7 is applied on the entire surface of the N film 6. Thereafter, oxygen (O) is ion-implanted over the entire surface. In this case, the conditions of the ion implantation, the thickness of the resist 7 and the like are selected so that O does not substantially enter the semiconductor substrate 1 and a sufficient amount of O is implanted into the SiN film 6. As a specific example, when the energy of O ion implantation is 40 keV, the thickness of the resist 7 may be about 3000 °. O is added to the SiN film 6 by 40k.
the projected range of O in the case of ion implanted at an energy of eV R _p
And the projection standard deviation ΔR _p are 593 ° and 220 °, respectively.

Next, after removing the resist 7, as shown in FIG. 1D, the SiN film 6 is patterned by etching to leave only on the upper surface and the side surface of the floating gate FG.

Next, thermal oxidation is performed in an oxidizing atmosphere to form a SiO ₂ film 8 on the surface of the SiN film 6 as shown in FIG.
To form At the same time, a gate oxide film of a transistor of a peripheral circuit not shown is also formed. In this case, Si
Since O is ion-implanted in the N film 6, oxidation is promoted by the presence of O, and the oxidation rate is increased. Therefore, even when the oxidation time is selected so that the gate oxide film of the transistor of the peripheral circuit has a predetermined thickness, this Si
The O ₂ film 8 can be formed sufficiently thick. SiO ₂ film 5
, The SiN film 6 and the SiO ₂ film 8 constitute ONO.

Next, a second-layer polycrystalline Si film is formed on the entire surface, the polycrystalline Si film is doped with impurities to reduce the resistance, and then the polycrystalline Si film is patterned into a predetermined shape by etching. As shown in FIG. 1F, a control gate CG is formed. Thereafter, the steps are advanced in accordance with the same manufacturing process as before to complete the target EPROM.

As described above, according to the embodiment I, the SiN film 6
Since the SiO ₂ film 8 is formed by thermally oxidizing the SiN film 6 after ion implantation, the oxidation rate of the SiN film 6 increases, and therefore, the SiO ₂ film 8 can be formed sufficiently thick. it can. As a result, the film quality of the ONO is improved, so that the leak current of the ONO can be reduced and the life of the ONO leading to dielectric breakdown can be extended.
In addition, since the gate oxide film of the transistor of the peripheral circuit is formed at the same time as the formation of the SiO ₂ film 8, the number of thermal oxidation steps can be reduced by one, thus simplifying the manufacturing process. be able to.

Embodiment II FIGS. 2A to 2D show EPROMs according to Embodiment II of the present invention.
The manufacturing method of is shown.

In this embodiment II, as shown in FIG. 2A, first, an insulating film 2, an impurity-doped polycrystalline Si film 3 and an SiO ₂ film 5 are sequentially formed on the entire surface of a semiconductor substrate 1.

Next, as shown in FIG. 2B, a SiN film 6 is formed on the SiO ₂ film 5.
Is formed, O is ion-implanted into the SiN film 6.

Next, the SiN film 6, the SiO ₂ film 5 and the polycrystalline Si film 3 are sequentially patterned by etching to obtain a shape as shown in FIG. 2C.

Next, the side surface of the floating gate FG made of the polycrystalline Si film thus formed is thermally oxidized to form the SiO ₂ film 5 on the side surface of the floating gate FG as shown in FIG. 2D. I do. Note that a gate oxide film of a transistor in a peripheral circuit is also formed by this thermal oxidation. Next, after forming the control gate CG, the process proceeds according to the same manufacturing process as before,
Complete the EPROM.

According to the embodiment II, the same advantages as those of the embodiment I are obtained. In addition, since the patterning of the SiN film 6 and the patterning for forming the floating gate FG are collectively performed, the lithography process and the etching are performed. There is also an advantage that the number of steps is reduced by one each, so that the manufacturing steps can be further simplified accordingly.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, the conditions for implanting O ions into the SiN film 6 can be selected as needed. In the above-described embodiments I and II, the SiO ₂ film 8 is formed on the surface of the SiN film 6 and the gate oxide film of the transistor of the peripheral circuit is formed at the same time. However, these need not always be formed simultaneously. .

Further, in Examples I and II described above, the present invention
Although the case where the present invention is applied to the manufacture of a ROM has been described, the present invention can be applied to the manufacture of various other semiconductor integrated circuit devices as well as an EPROM. For example, the present invention relates to a stacked capacitor cell (St) as shown in FIG.
Dynamic RAM with acked Capacitor Cell (Ran
dom Access Memory). In this case, the second layer polycrystalline Si film 9 and the third layer polycrystalline
The interlayer insulating film 11 between the Si film 10 is ONO. The third
In the figure, reference numeral 12 denotes a field insulating film, reference numeral 13 denotes a gate insulating film, reference numerals 14 and 15 denote a source region and a drain region, for example, n ⁺ type diffusion layers, reference numeral 16 denotes an insulating film, and reference numeral WL.
_{1 to} WL ₃ are word lines made of, for example, a first polycrystalline Si film,
Symbol BL indicates a bit line.

〔The invention's effect〕

As described above, according to the present invention, the second silicon oxide film is formed by thermally oxidizing the silicon nitride film after ion implantation of oxygen into the silicon nitride film. The oxidation rate of the silicon nitride film is increased, so that the second silicon oxide film can be formed thick.

[Brief description of the drawings]

1A to 1F are cross-sectional views showing a method of manufacturing an EPROM according to Example I of the present invention in the order of steps, and FIGS. 2A to 2D are views showing a method of manufacturing an EPROM according to Example II of the present invention. FIG. 3 is a sectional view showing the order of steps, and FIG. 3 is a sectional view for explaining a modification of the present invention. Description of main reference numerals in the drawings 1: semiconductor substrate, 3: polycrystalline Si film, 5, 8: SiO ₂ film, 6: SiN
Film, FG: floating gate, CG: control gate.

Claims (1)

(57) [Claims] 1. A semiconductor device comprising: a first polycrystalline silicon film; an insulating film provided on the first polycrystalline silicon film; and a second polycrystalline silicon film provided on the insulating film. A semiconductor integrated circuit in which the insulating film includes a first silicon oxide film, a silicon nitride film provided on the first silicon oxide film, and a second silicon oxide film provided on the silicon nitride film In the method for manufacturing a circuit device, the second silicon oxide film is formed by thermally oxidizing the silicon nitride film after ion-implanting oxygen into the silicon nitride film. Manufacturing method.