JP2925333B2 - Push button signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a push button signal generating circuit (hereinafter referred to as a PB signal generating circuit) in a push button dial type telephone or the like.

[0002]

2. Description of the Related Art Generally, a push-button dial type telephone has twelve buttons arranged in four rows and three columns, and each time the button is pressed, a push-button signal (PB) corresponding to the button is generated by a PB signal generating circuit. Hereinafter, a PB signal is transmitted. That is, when the button is pressed, the PB signal generation circuit sends out a PB signal including two audio frequency signals of a high group frequency and a low group frequency.

In this type of PB signal generation circuit, for example, signals of a plurality of frequencies can be realized using one digital / analog conversion circuit (hereinafter, referred to as a D / A conversion circuit). In this D / A conversion circuit, after dividing a signal of a plurality of frequencies, the result of the division is converted into an analog signal and transmitted to a telephone line.

However, when the input digital signal changes, the D / A conversion circuit may generate a very large spike called "glitch" in the output due to the operation time difference of the internal circuit or the like, thereby causing other spikes. Peripheral circuits may malfunction.

In order to remove such glitches, for example, Japanese Unexamined Patent Publication (Kokai) No. 61-205023 has proposed a glitch removal circuit for D / A conversion output.

FIG. 2 is a block diagram showing a configuration of a conventional D / A conversion output glitch removal circuit described in the above-mentioned document.

This glitch elimination circuit includes a D / A conversion circuit 1 which divides a digital signal Si, converts the frequency into an analog signal S1, and outputs a timing signal TS, and has a switched capacitor low-pass filter on its output side. (Hereinafter, referred to as a switched capacitor LPF) 2 and a clock synchronization circuit 3.

The switched capacitor LPF2 samples an analog signal S1 including a high frequency component output from the D / A conversion circuit 1 in response to the clock signal CLK2, and outputs an analog signal S2 obtained by removing the high frequency component from the analog signal S1. Circuit. This analog signal S2 is transmitted to the telephone line as a PB signal.

[0009] The clock synchronizing circuit 3 generates a timing signal T
S and a clock signal C synchronized with the timing signal TS.
This is a circuit that receives LK1 and outputs another clock signal CLK2 to the switched capacitor LPF2.

FIG. 3 is a signal waveform diagram of FIG.

When a digital signal Si of a predetermined frequency generated by pressing a button is input, D / A
The conversion circuit 1 divides the digital signal Si, converts it into an analog signal S1, outputs the analog signal S1 to the switched capacitor LPF2, and supplies a timing signal TS as shown in FIG. I do.

In the clock synchronization circuit 3, a timing signal TS and a clock signal C synchronized with the timing signal TS are output.
LK1 is received, and a clock signal CLK2 having a lower frequency than the clock signal CLK1 is generated and supplied to the switched capacitor LPF2. Switched capacitor LP
F2 samples the analog signal S1 with the clock signal CLK2 and sends out the analog signal S2 from which the high frequency component of the analog signal S1 has been removed.

In this glitch removing circuit, since the clock signal CLK2 for operating the switched capacitor LPF2 is synchronized with the output analog signal S1 of the D / A conversion circuit 1, a glitch peculiar to the D / A conversion circuit is removed. Thus, a high-performance PB signal generation circuit can be configured.

[0014]

However, in the conventional PB signal generating circuit, the switched capacitor LPF2
Requires the clock synchronization circuit 3 to operate. Further, the clock synchronization circuit 3 must newly generate the clock signal CLK2 for the switched capacitor LPF synchronized with the timing signal TS from the D / A conversion circuit 1, thereby complicating the circuit configuration and increasing the circuit There has been a problem of enlarging the scale. Especially,
When a signal of a plurality of frequencies is realized by one D / A conversion circuit 1 like a PB signal generation circuit, the clock synchronization circuit 3 becomes more complicated.

[0015] The present invention solves the problem of the prior art that the output of a plurality of signals by a D / A conversion circuit complicates the circuit configuration and increases the circuit scale. Circuit.

[0016]

FIG. 1 is a functional block diagram showing a PB signal generation circuit according to the present invention.

[0017] In this PB signal generating circuit, decodes the button press signal Si10 is a digital signal of a plurality of bits to determine the output frequency _{f o,} n times the frequency _{f o} (where, n; integer) of the frequency nf _o digital signal S10
Is provided. This P
On the output side of the B signal determination circuit 10, a D / A conversion circuit 20
, And a switched capacitor LPF30 is connected to the output side. Further, the output side of the PB signal determination circuit 10 is connected to the switched capacitor LPF30.

The D / A conversion circuit 20 converts the digital signal S
10 divides into 1 / n, a circuit for converting the frequency dividing results in analog signal S20 of a frequency f _o. The switched capacitor LPF30 is a circuit that samples the analog signal S20 using the digital signal S10 as a sampling clock and outputs the analog signal S30 from which high-frequency components have been removed.

[0019]

According to the present invention, since the PB signal generating circuit is constructed as described above, a button is pressed to generate a digital signal as the button pressing signal Si10 when the PB signal is generated.
When the input to the PB signal determination circuit 10, in the PB signal determination circuit 10, decodes the pressing pressure signal Si10, determines the frequency _{f o} of the output PB signal, the determined frequency f
generating a _o digital signal S10 of n times the frequency nf _o of providing the digital signal S10 to the D / A conversion circuit 20 and the switched capacitor LPF 30.

The D / A conversion circuit 20 converts the digital signal S
Upon receiving the 10, after dividing the digital signal S10 to 1 / n, and outputs the switched capacitor LPF30 and converts the division result to an analog signal S20 of a frequency _{f o.} The switched capacitor LPF30 samples the analog signal S20 from the D / A conversion circuit 20 at the timing of the digital signal S10, and removes the high-frequency component of the analog signal S20 from the analog signal S20.
30 is output. By this analog signal S30, PB
A signal is generated and sent to a telephone line or the like.

As described above, since the switched capacitor LPF30 performs the sampling operation with the same signal as the digital signal S10 input to the D / A conversion circuit 20, a conventional clock synchronization circuit for operating the switched capacitor LPF30 is used. Can be omitted. further,
The switched capacitor LPF30 is connected to the D / A conversion circuit 2
Since the sampling operation is performed in synchronization with 0, the D / A
By removing glitches generated at the analog transition point of the conversion circuit 20, a high-performance analog signal S30 with little distortion can be output. Therefore, the above problem can be solved.

[0022]

FIG. 4 is a schematic block diagram of a PB signal generating circuit in a push-button dial type telephone set according to an embodiment of the present invention. Is attached.

[0023] The PB signal generating circuit, 4-bit low group frequencies _{f l} and high group frequency _{f h} of the PB signal S40 a button press signal Si10 to be output by decoding a digital signal respectively determined, the frequency f _l, n times the frequency _nf l of _{f h,} digital signal nf _h S10a, S1
A PB signal determination circuit 10 that outputs 0b is provided. P
The output side of the B signal determination circuit 10 is connected to the low group side D / A conversion circuit 20a and the switched capacitor LPF 30a, and also connected to the high group side D / A conversion circuit 20b and the switched capacitor LPF 30b. Output sides of the switched capacitors LPFs 30 a and 30 b are connected to the adder 40.

The PB signal determining circuit 10 decodes the button pressing signal Si10 to determine the load values S11a and S11b, a low-group multiplier 12a and a high-group multiplier connected to the output of the decoder 11. And the multiplier 12b on the side. Multiplier low group side 12a inputs the load value S11a, a circuit for generating a digital signal S10a of n times the frequency nf _l of low group frequencies _{f l} object in synchronization with the clock signal CLK. The multiplier 12b is
Enter the load value S11b, n of the high group frequency _{f h} of purpose
Digital signal S10b twice the frequency nf _h is a circuit for generating a.

Of the D / A conversion circuits 20a and 20b connected to the outputs of the multipliers 12a and 12b, the D / A
The A conversion circuit 20a is a frequency divider 21a that divides the digital signal S10a to a target low group frequency f _l, and converts the output of the frequency divider 21a into an analog signal to convert the low group frequency f _l
D / A converter 22a that outputs analog signal S20a of
And it is comprised. Similarly, D / A converter circuit 20b of the high group side, high-group digital signal S10b of the frequency _{f h}
A frequency divider 21b for dividing up the frequency _{f h} of the object, the analog signal S2 the output of frequency dividing units 21b high group frequencies _{f h}
And a D / A converter 22b for converting the data to 0b.

The switched capacitors LPF30 connected to the output sides of the D / A conversion circuits 20a and 20b, respectively.
a, 30b, the switched capacitor LP on the low group side
F30a has a function of a low group side digital signal S10a to remove high-frequency components of the analog signal S20a as a sampling clock to output an analog signal S30a of low group frequency _{f l.} Similarly, the high-group side switched capacitor LPF 30b outputs the high-group digital signal S
Analog signal S2 using 10b as a sampling clock
Has a function of outputting an analog signal S30b of the high-frequency component is removed high group frequency f _h of the 0b.

The adder 40 outputs the low group side analog signal S30
a and the high group side analog signal S30b are added to generate a PB signal S40 composed of 16 types of analog signals.
It has a function of transmitting the B signal S40 to the telephone line.

FIG. 5 shows the switched capacitor L in FIG.
FIG. 9 is a circuit diagram illustrating a configuration example of a PF 30a (30b).

The low group switched capacitor LPF30
a and the high-group-side switched capacitor LPF 30b
The circuit configuration is the same, and the capacitors 31, 32, 33
ON by digital signal S10a (or S10b)
Analog switches 34, 35, 36, 37 that operate off
And an operational amplifier 38.

The (−) side input terminal of the operational amplifier 38 includes
An analog switch 34, a capacitor 31, and an analog switch 35 are connected in series.
(+) Side input terminal is connected to the ground. Between the (−) side input terminal and the output terminal of the operational amplifier 38,
When the capacitor 33 is connected,
, An analog switch 36, a capacitor 32 and an analog switch 37 are connected in parallel.

This switched capacitor LPF 30a
(Or 30b) is an external digital signal S10
a (or S10b), the analog switch 34,
35, 36 and 37 perform on / off operations periodically.
Then, for example, the digital signal S10a (or S10
If b) is at “H” level, each analog switch 34
37 are in the state of FIG. 5, and the input analog signal S20a
(Or S20b) is in a hold state where it is not connected to the capacitor 31. The digital signal S10a (or S
If 10b) is at the “L” level, each of the analog switches 34 to 37 is switched to the connection state opposite to the state of FIG. 5, and the input analog signal S20a (or S20b) is in the sample state in which the capacitor 31 is connected.

FIG. 6 is a signal waveform diagram of the digital signal S10a and the analog signal S20a when the frequency division number n = 16. The operation of FIGS. 4 and 5 will be described with reference to FIG.

The PB signal generating circuit shown in FIG. 4 uses the information of the button press signal Si10 consisting of a 4-bit digital signal to determine whether one analog signal among the low-group four-frequency signals and one among the high-group four-frequency signals. An analog signal is selected, and an operation is performed so as to generate a PB signal S40 including 16 types of analog signals obtained by adding each of them.

That is, the 4-bit button pressing signal Si10
Is input to the decoder 11 in the PB signal determination circuit 10, the decoder 11 decodes the button press signal Si10 to determine the load values S11a and S11b, and multiplies the load values S11a and S11b by the multiplier 12a. Give to 12b. In the multiplier 12a on the low group side, the clock signal C is obtained by the load value S11a determined by the decoder 11.
Synchronized with LK, frequency n which is n times the desired low group frequency f ₁
generating a digital signal S10a of f _l. Similarly, multiplier 12b of the high group side, produced by the load value S11b determined, the digital signal S10b of n times the frequency nf _h object of high group frequency _{f h} in synchronization with the clock signal CLK by the decoder 11 I do.

Here, the outputs of the multipliers 12a and 12b may be outputs of four kinds of frequencies on each of the low group side and the high group side. When the multiplier 12a on the low group side is considered, for example, if f ₁ = 697 Hz and n = 16, then 697 × 1
A digital signal S10a of 6 = 11.152 KHz is generated. This digital signal S10a is 89.7 μs
Cycle.

The output of the multiplier 12a is supplied to the D / A conversion circuit 2
Divider 21a in 0a and switched capacitor LPF3
0a. Similarly, the output of the multiplier 12b is D
It is supplied to the frequency divider 21b and the switched capacitor LPF 30b in the / A conversion circuit 20b.

In the low-group D / A converter 20a, the frequency divider 21a outputs the digital signal S1 from the multiplier 12a.
0a to 1 / n divides up the frequency _{f l} of purposes, and sends the division result to the D / A converter 22a. The D / A converter 22a converts the output of the frequency divider 21a into an analog signal,
The analog signal S20a of the period of f _l and outputs the switched capacitor LPF30a. This analog signal S20
The period of a is, for example, assuming that f ₁ = 697 Hz, 1 /
f ₁ = 1/697 = 1434.7 μs. Similarly,
In the high-group D / A conversion circuit 20b, the digital signal S10b from the multiplier 12b is frequency-divided by a frequency divider 21b.
As the division result into an analog signal S20b of the frequency _{f h} in the D / A converter 22b, it gives the analog signal S20b to the switched capacitor LPF30b.

Low-group switched capacitor LPF30
In a, as shown in FIG. 5, the analog signal S20a from the D / A converter 22a is sampled using the digital signal S10a output from the multiplier 12a as a sampling clock.

That is, if the digital signal S10a is at "H" level, the analog signal S20a is
When the digital signal S10a is at the "L" level, the analog switch 34 is turned on, the analog signal S20a is connected to the capacitor 31, and the sample state SS is set. That is, as shown in FIG. 6, the changing point of the analog signal S20a output from the D / A converter 22a is set to the hold state HS.
And the stable point after the change is defined as a sample state SS.

Then, since the glitch G generated at the changing point of the analog signal S20a output from the D / A conversion circuit 20a is not input to the switched capacitor LPF30a, the switched capacitor LPF30a has low distortion and high performance. The analog signal S30a from which the high frequency component of the signal S20a has been removed is output to the adder 40. That is, in the switched capacitor LPF 30a, the digital signal S10a input to the frequency divider 21a
Since the sampling operation is performed by the same signal as the above, a filter operation without distortion becomes possible.

The cut-off frequency _{f c} of the switched capacitor LPF30a is given by the following equation (1).

[0042]

(Equation 1)

For example, if nf ₁ = 32 × 697 Hz, C 31 = C 32 = 1, and C 33 = 3.3, then from equation 1, f _c = 1.5 × 697 Hz, and the desired low group frequency f ₁ = 697 Hz 1 Frequencies higher than .5 times can be attenuated. The same applies to the case of outputting other frequencies. An analog signal S3 output from such a switched capacitor LPF 30a
0a is supplied to the adder 40.

High-group side switched capacitor LPF30
b, the low-group switched capacitor LPF30
As in the case of a, the analog signal S20b output from the D / A converter 22b is sampled using the digital signal S10b output from the multiplier 12b as a sampling clock, and the analog signal S30b obtained by removing the high-frequency component of the analog signal S20b. Is output to the adder 40.

In the adder 40, the analog signals S30a and S30b are added, and a P signal comprising 16 types of analog signals is added.
A B signal S40 is generated, and the PB signal S40 is transmitted to a telephone line.

This embodiment has the following advantages.

(1) D / A conversion circuits 20a and 20b
Output analog signals S20a and S20b obtained by dividing the digital signals S10a and S10b output from the PB signal determination circuit 10 by 1 / n, respectively.
Signals of a plurality of frequencies, such as the PB signal S40, are also converted into signals with little distortion, and the D / A conversion circuits 20a, 20b
Respectively.

(2) Digital signals S10a and S10b input to D / A conversion circuits 20a and 20b, respectively
Since the switched capacitors LPF 30a, 30b are operated using the same signal as the sampling clock, the switched capacitors LPF 30a, 30b are operated.
In order to operate Ob, a clock synchronization circuit as in the related art is not required, thereby simplifying the circuit and reducing the circuit size.

(3) Switched capacitor LPF30
Since the operations of a and 30b are completely synchronized with the operations of the D / A conversion circuits 20a and 20b, a high-performance filter operation with less distortion is possible even for signals of a plurality of frequencies. Moreover, this switched capacitor LPF30
Since a and 30b have a function of removing glitches generated in the D / A conversion circuits 20a and 20b, stable operations can be expected.

The present invention is not limited to the embodiment shown in FIG. 4. For example, the PB signal determination circuit 10 may be constituted by another circuit, or the switched capacitors LPFs 30a and 30b
Can be variously modified, for example, by using a circuit other than that shown in FIG.

[0051]

As described above in detail, according to the present invention, the switched capacitor LPF is operated using the same signal as the digital signal from the PB signal determination circuit input to the D / A conversion circuit as a sampling clock. Therefore, a clock synchronization circuit for generating a clock for operating the switched capacitor LPF as in the related art can be omitted, thereby simplifying the circuit configuration and reducing the circuit size.

Further, since the operation of the switched capacitor LPF is always synchronized with the operation of the D / A conversion circuit,
A high-performance filter operation with little distortion can be expected for signals of a plurality of frequencies. In addition, the switched capacitor LPF can remove a glitch generated in the D / A conversion circuit, so that stable operation can be expected.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a PB signal generation circuit of the present invention.

FIG. 2 is a circuit diagram of a conventional glitch removal circuit for D / A conversion output.

FIG. 3 is a signal waveform diagram of FIG.

FIG. 4 is a schematic configuration block diagram of a PB signal generation circuit showing an embodiment of the present invention.

FIG. 5 is a circuit diagram of a switched capacitor LPF in FIG. 4;

FIG. 6 is a signal waveform diagram of FIG.

[Explanation of symbols]

Reference Signs List 10 PB signal determination circuit 11 Decoder 12a, 12b Multiplier 20, 20a, 20b D / A conversion circuit 21a, 21b Divider 22a, 22b D / A converter 30, 30a, 30b Switched capacitor LPF 40 Adder Si10 Button press signal f _o frequency f _l low group frequencies f _h high frequency group S10 digital signal S20, S30 analog signal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04M 1/50 H03H 19/00 H04M 19/02 H04Q 1/45

Claims (1)

(57) [Claims] 1. Decoding a button press signal and outputting an output frequency f
Determine the _o, n times the frequency f _o (where, n; integer) and the push button signal determination circuit for outputting a digital signal of the frequency nf _o of the output of the push-button signal determination circuit to 1 / n min A digital / analog conversion circuit for converting the frequency division result into an analog signal of a predetermined frequency;
Pushbutton signal generating circuit, characterized in that the switched capacitor low pass filter for removing high frequency components by sampling the output of the digital / analog converter in the frequency nf _o, with the.