JP2914043B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2914043B2
JP2914043B2 JP26098792A JP26098792A JP2914043B2 JP 2914043 B2 JP2914043 B2 JP 2914043B2 JP 26098792 A JP26098792 A JP 26098792A JP 26098792 A JP26098792 A JP 26098792A JP 2914043 B2 JP2914043 B2 JP 2914043B2
Authority
JP
Japan
Prior art keywords
film
wiring
insulating film
metal film
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP26098792A
Other languages
Japanese (ja)
Other versions
JPH06112329A (en
Inventor
淳 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP26098792A priority Critical patent/JP2914043B2/en
Publication of JPH06112329A publication Critical patent/JPH06112329A/en
Application granted granted Critical
Publication of JP2914043B2 publication Critical patent/JP2914043B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多層配線の形成方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a multilayer wiring.

【0002】[0002]

【従来の技術】一般に、LSIの配線材料としてはアル
ミニウムが多用されている。これは安価で加工性がよく
電気抵抗が低いなどの理由からである。ところが、最近
のLSIの配線に対する高集積度,高電流密度,高信頼
性の要求をアルミニウム配線で満足させることが困難と
なってきた。このため、フォトレジスト膜又は電子ビー
ムレジスト膜(以下レジスト膜と記す)に設けた配線形
成用パターンを有する溝内にめっき法により貴金属膜を
堆積して配線を形成する技術が提案されている。例え
ば、配線材料として金を用いた場合にはアルミニウムに
比べ様々な利点を持っている。即ち、金配線はアルミニ
ウム配線に比べて約20%も比抵抗が低く、ストレスマ
イグレーション,エレクトロマイグレーション寿命が数
十倍長い。また、アルミニウム配線はアルミニウム膜を
スパッタ法にて堆積したのち、通常のフォトリソグラフ
ィー技術とRIE(リアクティブイオンエッチング)法
などの異方性エッチング技術を組合せることで所望のパ
ターン形状に形成されるが、スパッタ法に起因したステ
ップカバレッジの低下やRIE法に起因したサイドエッ
チングによる配線細りなどの不具合が発生し、信頼性を
低下させることが多い。これに対して貴金属配線はレジ
スト膜をマスクとしためっき法により形成されるため、
前述の不具合は発生しない。
2. Description of the Related Art Generally, aluminum is often used as a wiring material for LSIs. This is because they are inexpensive, have good workability, and have low electric resistance. However, it has become difficult to satisfy the recent requirements for high integration, high current density, and high reliability for the wiring of LSI with aluminum wiring. Therefore, there has been proposed a technique of forming a wiring by depositing a noble metal film by plating in a groove having a wiring forming pattern provided in a photoresist film or an electron beam resist film (hereinafter referred to as a resist film). For example, when gold is used as a wiring material, there are various advantages as compared with aluminum. That is, the gold wiring has a specific resistance about 20% lower than that of the aluminum wiring, and the life of stress migration and electromigration is several tens times longer. The aluminum wiring is formed into a desired pattern shape by depositing an aluminum film by a sputtering method and then combining an ordinary photolithography technique and an anisotropic etching technique such as RIE (reactive ion etching). However, inconveniences such as reduction in step coverage due to the sputtering method and thinning of the wiring due to side etching due to the RIE method often occur, thereby lowering reliability. On the other hand, noble metal wiring is formed by plating using a resist film as a mask,
The aforementioned problem does not occur.

【0003】このめっき法による貴金属配線の形成にお
いては、その配線形状、配線ピッチはめっき用マスクと
して用いるレジスト膜の性能に影響される。
In forming a noble metal wiring by the plating method, the wiring shape and the wiring pitch are affected by the performance of a resist film used as a plating mask.

【0004】従来はノボラック系ポジ型レジスト膜が使
用されて来た。しかしながら、ポジ型レジスト膜を用い
てめっき法のマスクパターンを形成すると断面形状は、
ポジ型レジスト膜の特徴として順テーパとなる。この傾
向はレジスト膜の厚さを増すと、より顕著となる。最近
はLSIの高集積化に伴い、配線工程における基板段差
も大きくなってきているため、めっき用マスクとして用
いるレジスト膜も厚くせざるをえず、その断面形状は順
テーパ度が強くなる。従って、このレジスト膜をマスク
として形成される配線の断面形状は逆台形となる。配線
の断面形状が逆台形になると、この配線上に形成される
層間絶縁膜にボイドが発生したり、配線の幅の精度が低
下するという問題点があった。
Conventionally, a novolak-based positive resist film has been used. However, when a mask pattern of a plating method is formed using a positive resist film, the cross-sectional shape becomes
The positive type resist film has a forward taper as a feature. This tendency becomes more remarkable as the thickness of the resist film increases. In recent years, as the level of integration of LSIs has increased, the level difference between substrates in the wiring process has also increased. Therefore, a resist film used as a plating mask has to be thickened, and its cross-sectional shape has a high forward taper. Therefore, the cross-sectional shape of the wiring formed using this resist film as a mask is an inverted trapezoid. If the cross-sectional shape of the wiring is inverted trapezoidal, there is a problem that voids are generated in the interlayer insulating film formed on the wiring and the accuracy of the width of the wiring is reduced.

【0005】この問題を解決するため、最近提案されて
いる化学増幅型ネガレジスト膜を用いることを検討し
た。化学増幅型ネガレジスト膜は、露光によってレジス
ト膜中の酸発生剤から酸が発生し、その酸が触媒となっ
てレジスト膜の不溶化が促進される。その特徴としては
非常に高感度、高解像度であり、更に高ドライエッチン
グ耐性を持つ事があげられる。この化学増幅型ネガレジ
スト膜を用いると、従来のネガレジスト膜の低解像度の
問題を解決でき、しかもその形状はネガ型レジスト膜の
特徴を活かし、断面形状が逆テーパから若干の順テーパ
形状まである程度自由に制御できる。
To solve this problem, the use of a recently proposed chemically amplified negative resist film was studied. In a chemically amplified negative resist film, an acid is generated from an acid generator in the resist film upon exposure, and the acid serves as a catalyst to promote insolubilization of the resist film. Its features include very high sensitivity and high resolution, and high dry etching resistance. By using this chemically amplified negative resist film, the problem of low resolution of the conventional negative resist film can be solved, and its shape takes advantage of the characteristics of the negative resist film, and its cross-sectional shape is from reverse tapered to slightly forward tapered. Can be controlled to some extent.

【0006】図2は従来の半導体装置の製造方法の一例
を説明するための半導体チップの断面図である。
FIG. 2 is a sectional view of a semiconductor chip for explaining an example of a conventional method of manufacturing a semiconductor device.

【0007】図2に示すように、素子及び基本配線等を
形成して表面に凹凸を有する半導体基板1の上に絶縁膜
2を設け、絶縁膜2の上にチタンタングステン膜と金膜
を順次堆積して設けた金属膜3を形成する。ここで、金
属膜3は電気めっき法の給電膜又は無電解めっき法の析
出膜となるもので貴金属膜をめっきする場合には貴金属
膜が望ましい。次に、金属膜3の上に化学増幅型ネガレ
ジスト膜を塗布してパターニングし、配線形成用パター
ンを有するレジスト膜6を形成する。次に、レジスト膜
6をマスクとして金属膜3の上に電気めっき法で金膜7
を堆積し配線を形成する。
As shown in FIG. 2, an insulating film 2 is provided on a semiconductor substrate 1 having an uneven surface on which elements and basic wiring are formed, and a titanium tungsten film and a gold film are sequentially formed on the insulating film 2. A deposited metal film 3 is formed. Here, the metal film 3 serves as a power supply film in an electroplating method or a deposition film in an electroless plating method. When a noble metal film is plated, a noble metal film is preferable. Next, a chemically amplified negative resist film is applied on the metal film 3 and patterned to form a resist film 6 having a wiring forming pattern. Next, a gold film 7 is formed on the metal film 3 by electroplating using the resist film 6 as a mask.
Is deposited to form wiring.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、この従
来の半導体装置の製造方法では、電気めっき用給電膜あ
るいは無電解めっき用析出膜となる金属膜の上に化学増
幅型ネガレジスト膜を塗布してフォトリソグラフィー技
術によりパターニングする際に段差部の凹部で金属膜と
接する部分のレジスト膜が図2の裾部8のように裾を引
き、パターン精度が低下するという問題点があった。
However, in this conventional method for manufacturing a semiconductor device, a chemically amplified negative resist film is applied on a metal film to be a power supply film for electroplating or a deposition film for electroless plating. When patterning by the photolithography technique, there is a problem that the resist film at the portion in contact with the metal film at the concave portion of the step portion is pulled down as shown by the bottom portion 8 in FIG.

【0009】この裾引きの程度は、露光時のパターン像
の結像面からはずれた部分で急激に増大する。従って、
大きな段差があるほど大幅な裾引きが生じてしまう。こ
のように裾を引いたレジスト膜をマスクとして電気めっ
きにより溝内に金属膜を堆積して配線を形成した場合、
配線の断面形状はくびれてしまう。このくびれはこの配
線を含む表面に層間絶縁膜を形成する際にボイドの原因
となるほか、配線が局所的に細くなっているとエレクト
ロマイグレーションが発生しやすくなり信頼性を低下さ
せる問題があった。
[0009] The extent of this skirting sharply increases at a portion deviating from the image plane of the pattern image at the time of exposure. Therefore,
The greater the level difference, the more significant skirting occurs. When a metal film is deposited in the groove by electroplating using the resist film with the tail as a mask as a mask to form wiring,
The cross-sectional shape of the wiring is constricted. This constriction causes voids when an interlayer insulating film is formed on the surface including the wiring, and when the wiring is locally thin, electromigration is likely to occur, and the reliability is reduced. .

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、素子等を形成し表面に凹凸を有する半導体基
板上に第1の絶縁膜を形成し前記第1の絶縁膜上にめっ
き用の給電膜(又は析出膜)となる金属膜を形成する工
程と、前記金属膜の上に塗布法で第2の絶縁膜を形成し
た後、前記第2の絶縁膜をエッチバックして前記金属膜
の凹部にのみ前記第2の絶縁膜を残して他の部分の前記
金属膜を露出させる工程と、前記第2の絶縁膜を含む金
属膜の表面に化学増幅型ネガレジスト液を塗布してパタ
ーニングし配線形成用パターンを有するレジスト膜を形
成する工程と、前記レジスト膜をマスクとして前記第2
の絶縁膜を除去する工程と、再度前記レジスト膜をマス
クとしてめっき法により前記金属膜の表面に貴金属膜を
堆積して配線を形成する工程とを含んで構成される。
According to a method for manufacturing a semiconductor device of the present invention, a first insulating film is formed on a semiconductor substrate having an element or the like having an uneven surface, and plating is performed on the first insulating film. Forming a metal film to be a power supply film (or a deposition film) for forming a second insulating film on the metal film by a coating method, and then etching back the second insulating film to form the second insulating film. Exposing the other portion of the metal film while leaving the second insulating film only in the concave portion of the metal film; and applying a chemically amplified negative resist solution to the surface of the metal film including the second insulating film. Patterning to form a resist film having a wiring forming pattern; and forming the second resist film using the resist film as a mask.
And a step of forming a wiring by depositing a noble metal film on the surface of the metal film by plating again using the resist film as a mask.

【0011】[0011]

【実施例】本発明の経緯は、最初平坦な基板を用いて化
学増幅型ネガレジスト膜の貴金属膜上での形状改善を試
み、レジスト膜の透明度、酸発生剤の量、プリベーク温
度、PEB(Post Exposure Bake:
露光後ベーク)の温度を適切に選ぶことで裾引きのない
形状を得た。しかしながら素子を形成した段差のある半
導体基板上で実験してみると、凹部において大きく裾を
引いてしまい、レジスト膜の形成条件の調整では解決出
来ない事が分った。そこで化学増幅型レジスト膜の形状
が基板材質により大きく変化するという性質を利用する
ことを考え、各種材質の膜に対するレジスト膜断面形状
の変化を調査した。その結果、SOG膜,ポリイミド
膜,プラズマ酸化膜,プラズマ窒化膜,Ti膜,TiN
膜では裾引きが軽減され、特にSOG膜では裾引きが全
くない事が分かった。つまり、貴金属膜に比べてレジス
ト膜中に発生した酸を吸収し易い材質の膜を選べば良い
ことが判明した。そこで貴金属膜全面に厚さ10nm程
度の薄いSOG膜を形成した後、化学増幅型ネガレジス
ト膜を塗布し、パターニングしたところ段差の凹部にお
いても裾引きのない形状を得た。しかしながら、今度は
平坦部において逆にレジスト膜形状がくびれてしまった
のである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The background of the present invention is as follows. First, an attempt was made to improve the shape of a chemically amplified negative resist film on a noble metal film using a flat substrate, and the transparency of the resist film, the amount of an acid generator, the prebake temperature, the PEB ( Post Exposure Bake:
By appropriately selecting the temperature of (post-exposure bake), a shape without tailing was obtained. However, when an experiment was performed on a semiconductor substrate having a step on which an element was formed, it was found that the bottom was largely drawn in the concave portion, and it could not be solved by adjusting the conditions for forming the resist film. In view of the fact that the shape of the chemically amplified resist film greatly changes depending on the material of the substrate, changes in the cross-sectional shape of the resist film with respect to films of various materials were investigated. As a result, SOG film, polyimide film, plasma oxide film, plasma nitride film, Ti film, TiN
It was found that the tailing was reduced in the film, and there was no tailing in the SOG film in particular. That is, it has been found that a film made of a material that can easily absorb the acid generated in the resist film as compared with the noble metal film may be selected. Then, a thin SOG film having a thickness of about 10 nm was formed on the entire surface of the noble metal film, and then a chemically amplified negative resist film was applied and patterned. However, this time, the shape of the resist film was narrowed in the flat portion.

【0012】この問題の解決のため、貴金属膜上に形成
される酸吸収膜を塗布法により利用して部分的に形成す
ることを工夫した。すなわち、塗布法により形成された
SOG膜には平坦部より凹部で膜厚が厚くなる。従っ
て、SOG膜を全面エッチバックした場合平坦部におい
ては貴金属膜を露出させ、凹部にのみSOG膜を残すこ
とができる。基板にこのような構造を持たせたところ、
形成されたレジストパターンは基板凹部においてはSO
G膜の効果により裾引きが抑えられ、平坦部においては
貴金属膜が露出していることから、裾引きもくびれもな
いレジスト膜の形状を得ることができた。またSOG膜
ばかりでなく、塗布法で形成されるポリイミド膜を用い
ても同様な効果が得られることが分った。
In order to solve this problem, it has been devised to partially form an acid absorption film formed on a noble metal film by using a coating method. That is, the thickness of the SOG film formed by the coating method is larger in the concave portion than in the flat portion. Therefore, when the entire surface of the SOG film is etched back, the noble metal film is exposed in the flat portion, and the SOG film can be left only in the concave portion. After having such a structure on the substrate,
The formed resist pattern has SO
The footing was suppressed by the effect of the G film, and the noble metal film was exposed in the flat part, so that a resist film shape without footing and constriction could be obtained. It was also found that similar effects can be obtained by using not only an SOG film but also a polyimide film formed by a coating method.

【0013】次に、本発明の一実施例について図面を参
照して説明する。
Next, an embodiment of the present invention will be described with reference to the drawings.

【0014】図1(a)〜(c)は本発明の一実施例を
説明するための工程順に示した半導体チップの断面図で
ある。
FIGS. 1A to 1C are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

【0015】先ず、図1(a)に示すように素子等を形
成して段差を有する半導体基板1の上に設けた絶縁膜2
の上に厚さ30〜100nmのチタンタングステン膜と
厚さ30〜100nmの金膜をスパッタ法により順次堆
積して積層した金属膜3を形成する。ここで、チタンタ
ングステン膜は絶縁膜2と金膜との密着性を保つ役割を
果たす。次に、金属膜3の上にSOG液を塗布して焼成
し厚さ10〜30nmのSOG膜4を形成する。このS
OG膜4は凹部5において平坦部より膜厚が厚くなる。
First, as shown in FIG. 1A, an element or the like is formed, and an insulating film 2 provided on a semiconductor substrate 1 having a step is provided.
A titanium tungsten film having a thickness of 30 to 100 nm and a gold film having a thickness of 30 to 100 nm are sequentially deposited thereon by sputtering to form a laminated metal film 3. Here, the titanium tungsten film plays a role in maintaining the adhesion between the insulating film 2 and the gold film. Next, an SOG liquid is applied on the metal film 3 and baked to form an SOG film 4 having a thickness of 10 to 30 nm. This S
The OG film 4 is thicker in the recess 5 than in the flat portion.

【0016】次に、図1(b)に示すように、SOG膜
4をエッチバックして凹部5以外のSOG膜4を除去
し、平坦部の金属膜3の表面を露出させる。
Next, as shown in FIG. 1B, the SOG film 4 is etched back to remove the SOG film 4 other than the concave portions 5, exposing the surface of the metal film 3 in the flat portion.

【0017】次に、図1(c)に示すように、凹部5の
金属膜3の上に残した薄いSOG膜4を含む金属膜3の
上に化学増幅型ネガレジスト液(例えば東京応化社製i
N−200に若干の色素を加えたもの)を1.6μmの
厚さに塗布した後、フォトリソグラフィー工程によって
パターニングし、レジスト膜6を形成する。次に、レジ
スト膜6をマスクとして金属膜3上に残されたSOG膜
4をO2 +CHF3 プラズマを用いたRIE法により除
去する。
Next, as shown in FIG. 1C, a chemically amplified negative resist solution (for example, Tokyo Ohkasha Co., Ltd.) is applied on the metal film 3 including the thin SOG film 4 left on the metal film 3 in the recess 5. Made i
N-200 to which a slight amount of dye is added) is applied to a thickness of 1.6 μm, and then patterned by a photolithography process to form a resist film 6. Next, using the resist film 6 as a mask, the SOG film 4 remaining on the metal film 3 is removed by RIE using O 2 + CHF 3 plasma.

【0018】ここで、凹部5の金属膜3上に残されたS
OG膜4が発生した酸を吸収することで凹部5でのレジ
スト膜6の裾引きが抑えられ、パターン精度が向上す
る。なお、このSOG膜4の代りに塗布焼成されたポリ
イミド膜を用いても同様の効果を得ることができる。
Here, the S remaining on the metal film 3 in the recess 5
By absorbing the acid generated by the OG film 4, the footing of the resist film 6 in the concave portion 5 is suppressed, and the pattern accuracy is improved. The same effect can be obtained by using a polyimide film coated and baked instead of the SOG film 4.

【0019】次に、レジスト膜6をマスクとし金属膜3
を給電膜又は析出膜として金属膜3の上に電気めっき法
又は無電解めっき法で金膜7を堆積し配線を形成する。
Next, using the resist film 6 as a mask, the metal film 3
Is deposited on the metal film 3 by an electroplating method or an electroless plating method as a power supply film or a deposition film to form a wiring.

【0020】なお、金属膜3上に直接SOG膜4あるい
はポリイミド膜を塗布形成すると、これらの膜と貴金属
膜との密着性は成膜条件によって低下し、形成したSO
G膜4あるいはポリイミド膜が金属膜3上から剥離する
場合がある。このような欠点を克服するため、金属膜3
上にプラズマCVDにより窒化シリコン膜を密着膜とし
て厚さ10nm程度形成した後、SOG膜あるいはポイ
リミド膜を形成することにより密着性を向上できる。
When the SOG film 4 or the polyimide film is directly formed on the metal film 3 by adhesion, the adhesion between these films and the noble metal film is reduced depending on the film formation conditions, and the formed SO
The G film 4 or the polyimide film may be peeled off from the metal film 3. To overcome such disadvantages, the metal film 3
After forming a silicon nitride film as an adhesion film with a thickness of about 10 nm by plasma CVD thereon, an adhesion can be improved by forming an SOG film or a polyimide film.

【0021】[0021]

【発明の効果】以上説明したように本発明は、めっき用
給電膜に生じた凹部の表面に選択的に絶縁膜を形成する
ことにより、レジスト膜に設けたパターンの断面形状の
欠陥を無くし、微細貴金属配線の信頼性を向上できると
いう効果を有する。
As described above, the present invention eliminates defects in the cross-sectional shape of a pattern provided in a resist film by selectively forming an insulating film on the surface of a concave portion formed in a power supply film for plating. This has the effect of improving the reliability of the fine noble metal wiring.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を説明するための工程順に示
した半導体チップの断面図。
FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

【図2】従来の半導体装置の製造方法を説明するための
半導体チップの断面図。
FIG. 2 is a cross-sectional view of a semiconductor chip for describing a conventional method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 絶縁膜 3 金属膜 4 SOG膜 5 凹部 6 レジスト膜 7 金膜 8 裾部 Reference Signs List 1 semiconductor substrate 2 insulating film 3 metal film 4 SOG film 5 concave portion 6 resist film 7 gold film 8 foot

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 素子等を形成し表面に凹凸を有する半導
体基板上に第1の絶縁膜を形成し前記第1の絶縁膜上に
めっき用の給電膜(又は析出膜)となる金属膜を形成す
る工程と、前記金属膜の上に塗布法で第2の絶縁膜を形
成した後、前記第2の絶縁膜をエッチバックして前記金
属膜の凹部にのみ前記第2の絶縁膜を残して他の部分の
前記金属膜を露出させる工程と、前記第2の絶縁膜を含
む金属膜の表面に化学増幅型ネガレジスト液を塗布して
パターニングし配線形成用パターンを有するレジスト膜
を形成する工程と、前記レジスト膜をマスクとして前記
第2の絶縁膜を除去する工程と、再度前記レジスト膜を
マスクとしてめっき法により前記金属膜の表面に貴金属
膜を堆積して配線を形成する工程とを含むことを特徴と
する半導体装置の製造方法。
1. A first insulating film is formed on a semiconductor substrate on which an element or the like is formed and has an uneven surface, and a metal film serving as a power supply film (or a deposition film) for plating is formed on the first insulating film. Forming and, after forming a second insulating film on the metal film by a coating method, etching back the second insulating film to leave the second insulating film only in the concave portion of the metal film. Exposing the other portion of the metal film, and applying a chemically amplified negative resist solution to the surface of the metal film including the second insulating film to form a resist film having a wiring forming pattern. A step of removing the second insulating film using the resist film as a mask, and a step of forming a wiring by depositing a noble metal film on the surface of the metal film by plating using the resist film as a mask again. Manufacture of a semiconductor device characterized by including Construction method.
【請求項2】 第2の絶縁膜がSOG膜又はポリイミド
膜である請求項1記載の半導体装置の製造方法。
2. The method according to claim 1, wherein the second insulating film is an SOG film or a polyimide film.
【請求項3】 第2の絶縁膜が窒化シリコン膜上にSO
G膜又はポリイミド膜を堆積した2層構造を有する請求
項1記載の半導体装置の製造方法。
3. The method according to claim 1, wherein the second insulating film is formed on the silicon nitride film by using SO.
2. The method according to claim 1, wherein the semiconductor device has a two-layer structure in which a G film or a polyimide film is deposited.
JP26098792A 1992-09-30 1992-09-30 Method for manufacturing semiconductor device Expired - Lifetime JP2914043B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26098792A JP2914043B2 (en) 1992-09-30 1992-09-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26098792A JP2914043B2 (en) 1992-09-30 1992-09-30 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH06112329A JPH06112329A (en) 1994-04-22
JP2914043B2 true JP2914043B2 (en) 1999-06-28

Family

ID=17355499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26098792A Expired - Lifetime JP2914043B2 (en) 1992-09-30 1992-09-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2914043B2 (en)

Also Published As

Publication number Publication date
JPH06112329A (en) 1994-04-22

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