JP2911172B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a very shallow junction is formed in a SiLSI (silicon semiconductor integrated circuit) device.

(Prior Art) FIG. 2 is a process sectional view for explaining a conventional method of manufacturing a MOS type semiconductor device. As shown in FIG. 2A, the surface of the Si substrate 101 is separated into an active region 102 and a field region 103 by using a selective oxidation method (LOCOS method) (here, below the oxide film of the field region 103). The step of channel stop doping is omitted.)

Next, as shown in FIG.
In order to form an LDD (Lightly Doped Drain Structure) structure after forming a gate oxide film 104 and a gate electrode 105, lightly-doped ion implantation (for n ⁺ type, As ⁺ or P ⁺ , P type) B ⁺ , BF ₂ ⁺ )
After the ion implantation layer 106 is formed, a sidewall 107 of a silicon oxide film is formed by a normal pressure CVD method or the like.

Next, as shown in FIG. 1 (c), after a high dose source / drain ion implantation 108 is performed, a source / drain region 109 is formed by appropriate heat treatment.

Hereinafter, although omitted in the drawings, an LSI element is completed by depositing an intermediate insulating film, patterning contacts, and wiring.

(Problems to be Solved by the Invention) However, in the above-described method for manufacturing a MOS type semiconductor device, it has become extremely difficult to form a very shallow junction as the LSI becomes finer.

In particular, this tendency is remarkable when forming a P-type MOS type semiconductor device using B as a dopant of a diffusion layer, and is 0.1 μm.
It is very difficult to form a high-concentration junction of m or less.

This invention is one of the problems of the prior art.
An object of the present invention is to provide a method of manufacturing a semiconductor device which solves a difficulty in forming a high-concentration shallow junction.

For (SUMMARY for a) the present invention to solve the above problems, in the method of manufacturing a semiconductor device, after forming a gate electrode on the active region on the semiconductor substrate, a TiSi _x layer to a predetermined thickness The step of depositing and performing a heat treatment in N ₂ or NH ₃ to form a TiN layer is introduced.

(Operation) According to the present invention, in a method of manufacturing a semiconductor device,
By introducing the above process, heat treatment of TiSi _x layer in N ₂ or NH ₃ forms Si in TiSi _x layer as polycrystalline Si on field oxide film under TiN layer However, on Si such as a source and a drain, epitaxial growth is performed as single crystal Si.

Thereafter, when TiN and Si are etched, due to the difference in etch rate between the polycrystalline Si and the single-crystal Si, even after the polycrystalline silicon on the field oxide film is etched, the single-crystal Si
Are all left unetched and the remaining single-crystal Si
When ion implantation and heat treatment are performed from above, a shallow junction can be effectively formed, and the above problem can be eliminated.

(Example) Hereinafter, an example of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. 1 (a) to 1 (d) are process cross-sectional views of one embodiment, and are process cross-sectional views when applied to a method of manufacturing a MOS semiconductor device.

First, in FIG. 1A, the surface of a Si substrate 201 is separated into an active region 202 and a field region 203 by using a selective oxidation method (LOCOS method) (here, a channel stop under a field oxide film). Doping is omitted).

Next, in the active region 202, after forming a gate oxide film 204 and a gate electrode 205 on the Si substrate 201, the LDD
In order to form a structure, lightly-doped ion implantation (As ⁺ or P ^{+ for} n-type, B ⁺ , BF ₂ ^{+ for} P-type) is performed to form an ion implantation layer 206. Next, a sidewall 207 is formed.

Next, as shown in FIG. 1B, a TiSi _x layer 208 is formed on the structure formed in FIG. 1A. TiSi at this time
The thickness of the _x layer 208 depends on the depth of the source / drain junction formed last. Further, the thickness of the TiSi _x layer 208 varies depending on the composition ratio of Ti and Si TiSi _x layer 208. As an example, stoichiometry (literally, in the sense of chemical theory, here means that the ratio of the constituent atoms matches the composition ratio of the following compound.
(It means that only Si ₂ is included and does not include TiSi or TiSi ₃ ). Consider the case of TiSi ₂ as an example. Where T
The description will be given on the assumption that the iSi ₂ layer 208 is deposited for about 2000 °.

Next, as shown in FIG. 1 (c), in N ₂ or NH ₃
Heat treatment at a temperature of 900 to 1000 ° C. in the TiSi ₂ layer 20
8 is converted to TiN. At this time, Si in TiSi ₂
iO ₂ on field oxide 203 or gate electrode 205
Above (high melting point metal silicide such as WSi ₂ , MOSi ₂ or polycrystalline
In the case of Si), a polycrystalline Si layer 210 is formed, and on single crystal Si (source / drain region), a single crystal Si layer 211 is formed.

At this time, the thicknesses of the polycrystalline Si layer 210 and the single-crystal Si layer 211 are set to the thickness of TiSi ₂ when the unit thickness “1” is changed to TiSi ₂ , ie, “2.5”
When converted from “1” and the thickness of the consumed silicon “2.27”, it is about 2000 × 2.27 / 2.51 = 1808Å.

Thereafter, as shown in FIG. 1D, the TiN layer 209 and the polycrystalline Si layer 210 are etched. At this time, single crystal Si on Si
Layer 211 has a lower etch rate than polycrystalline Si layer 210,
The difference can be made about 1 / 1.5 to 1/2 by controlling the etching conditions.

Here, assuming that the etch rate is 1/2, after the TiN layer 204 and the polycrystalline Si layer 210 are completely etched off, a single-crystal Si layer 212 of about 900 ° remains in the source / drain portion.

Thereafter, source / drain ion implantation 213 is performed and heat treatment is performed, so that source / drain regions 214 are formed. In the source / drain region 214, the effective diffusion depth has increased by 900 mm.
When forming the source / drain, the heat treatment margin is increased.

(Effects of the Invention) As described above, according to the present invention, a TiSi _x layer is formed before forming a source / drain region, and when the TiSi _x layer is formed into a TiN, the Ti field is formed on the Si field region under the TiN and the Due to the above difference in crystallinity, single-crystal Si is left only on Si during etching, so that the region to be diffused can be made longer effectively when forming source / drain regions. In addition, the implantation energy margin and the heat treatment margin in the formation of the shallow source / drain, which are problems, are alleviated. In particular, it becomes easy to form the source and drain of a PMOS using boron as an impurity.

In addition, when the same implantation conditions and heat treatment are used, the junction depth to be formed can be changed depending on the composition ratio and thickness of the TiSi _x layer to be formed first, thereby increasing the degree of freedom in the process.

[Brief description of the drawings]

1 (a) to 1 (d) are process cross-sectional views for explaining one embodiment of a method for manufacturing a semiconductor device according to the present invention.
2 (a) to 2 (c) are process sectional views of a conventional method for manufacturing a MOS semiconductor device. 201: Si substrate, 202: Active region, 203: Field region, 204: Gate oxide film, 205: Gate electrode, 206, 213: Ion implantation layer, 207: Side wall, 208: TiSi _x layer , 209: TiN layer; 210, 212: polycrystalline Si layer; 211: single crystal Si layer; 214: source / drain region.

Claims (2)

(57) [Claims] A step of sequentially forming a gate insulating film and a gate electrode in the active region after separating the semiconductor substrate into an active region and a field region; and forming a TiSix layer on the entire surface of the structure formed by the above step. Performing the step of: nitriding the TiSix layer; removing the TiN layer formed by the above step; removing the polycrystalline Si layer formed under the TiN layer; and performing ion implantation on the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, further comprising the step of forming a sidewall on a side wall of said gate electrode.