JP2909502B2 - Test method and test apparatus for frame memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method and a test apparatus for a frame memory, and more particularly to a means for dramatically improving the test efficiency and test accuracy of a defect of a frame memory employing a double buffer system. is there.

[0002]

2. Description of the Related Art Information to be displayed on a display by a user is converted into dot information on a screen by a drawing control unit, and is written into a frame memory while being controlled by a frame memory interface circuit. The data written in the frame memory is input to the random access memory D / A converter RAMDAC as display data.
The RAMDAC includes a color look-up table for converting digital color information into a display color on a screen and a digital lookup table.
An analog converter or D / A converter;
The display data is converted into RGB signals and supplied to a display. The display displays information required by the user in color.

When displaying on a display, if the frame memory has a defect, normal display cannot be performed. The conventional test method for the defect of the frame memory includes, for example, (1) a test method of displaying display data of the frame memory as an image on a display and visually diagnosing the display data. (2) display data and display data input to the RAMDAC. Or a test method for comparing with a reference value (JP-A-63-28
2785, JP-A-1-173123).

[0004]

In the first test method, since the test pattern displayed on the display is visually checked, the operator is easily tired, the judgment is inaccurate, and the test speed does not increase. .

In the second test method, when the display data input to the RAMDAC is read and tested, the operation speed of the test register is low, so that the frame memory interface circuit and the RAMDAC which are peripheral circuits of the frame memory are used. It is necessary to lower the operating clock of the device, increase the number of test timing generation circuits, and have the drawback that dynamic tests cannot be performed in real time, which is essential.

SUMMARY OF THE INVENTION It is an object of the present invention to execute a test of a plurality of frame memories constituting a double-buffer type frame memory under the exact same conditions as the actual operation, without relying on visual confirmation or the like. A test method and a test apparatus are provided.

[0007]

The present invention achieves the above object.
In order to create a multi-port VRAM,
Frame memory for storing image data for multiple screens
The image data is switched and displayed on the display.
Test Method for Double Buffer Type Frame Memory
In testing one frame memory, the other
Use the frame memory as a test buffer
From the VRAM that constitutes the frame memory, the same
Display data to be output in the same frame constitutes the other frame memory
Input to the VRAM, and the contents of one frame memory
Compare the contents of the other frame memory and
Frame that collects information on defective locations of VRAMs
We propose a test method for memory.

More specifically, a plurality of multi-port VRs
Frame memory consisting of AM and storing image data
For multiple screens, switch these image data
Double-buffer frame display on the display
In Mori's test method, one frame memory test
The other frame memory as a test buffer
Use n videos that make up one frame memory
Serial access method of random access memory VRAM
Display data output from the memory SAM under the same conditions as actual operation
To the S of n VRAMs constituting the other frame memory
AM, and the contents of one frame memory and the other frame memory
Comparing the contents of the frame memory and configuring the frame memory
To collect information on defective parts of n VRAMs
Memory memory test method.

At the time of testing the other frame memory,
In contrast to the above method, the above one frame memory
The other frame memory.
Display data output from the VRAM to be generated under the same conditions as actual operation
Data to VRAM that constitutes one frame memory
And the contents of the other frame memory and one frame memo
And compares the contents of the
The information on the defective portion of the VRAM is collected.

According to the present invention, in order to achieve the above object, a frame memory comprising a plurality of multiport VRAMs for storing image data is provided for a plurality of screens, and these image data are switched and displayed on a display. In the test method of the double buffer type frame memory,
When testing one frame memory, the other
Using the memory as a test buffer, the image data before writing to the other frame memory is compared with the image data that has passed through the frame memory and the one frame memory to which the image data has been transferred. A test method for a frame memory that determines whether all are good or at least one is bad is proposed.

According to the present invention, in order to achieve the above object, a frame memory comprising a plurality of multiport VRAMs for storing image data is provided for a plurality of screens, and these image data are switched and displayed on a display. In a double-buffer frame memory tester, when testing one frame memory,
Means for writing the test pattern data to the other frame memory using the memory pattern memory as a test buffer, means for transferring the test pattern data from the test buffer to one frame memory, and means for transferring the test pattern data from the test buffer to the one frame memory. Means for comparing the test pattern data with the test pattern data to judge the quality of the frame memory .
You.

This test apparatus may include a test buffer select circuit for designating any one of the plurality of frame memories as the test buffer.

[0013]

[Action]Not confirmed to be good at the start of the test
Brought several frame memories at random
If How to make sure that good products
Do you accept If it happens to be bad,
How to determine goodness Happens to be bad
How to determine which is good
If everything happens to be bad, how do you know it?
Do you accept Good quality for subsequent test work
It is not necessary to have the frame memory for which the
Whether Good products based on memories on different chips
If you can use it as, select it first
If the subsequent tests should go smoothly,
When multiple frame memories are arranged in a chip
In the case of the mutual comparison method in the chip,
The problem is whether the problem does not always follow.

I happened to know that good products were available
To check whether at least one of the frames
The same correct contents as the test pattern are written to the memory
Test results show that both frame memories
If they match, it can be confirmed as a good product. (RAM part
The contents can be read and confirmed. It happens to be bad
If so, how do you identify which one is bad?
In other words, there are only two frame memories
If the frame memory is not good,
Good products cannot be identified.

If it happens to be defective,
Test how to identify good products.
At the stage where only two frame memories are executed, one
If the frame memory is not good, the good memory cannot be identified.
No.

If everything happens to be bad,
See the frame memo for how to check this.
The contents read from the memory must match the test pattern
If not, it is bad. (Check the contents of the RAM
Wear. ) Confirm that the product is good for the subsequent test work.
There is no need to have a recognized frame memory as a reference product
Confirm that the product is good
Test algorithm must be a good one.
It is not necessary to have the frame memory confirmed. However
By having good products as standards, the work efficiency of testing
Rate improvement and identification of defective products in the above cases
Is advantageous.

[0017] Reference is made to memories on different chips.
If you can use it as a good product, select it first.
By the way, subsequent tests should go smoothly,
Multiple frame memories are arranged in the same chip
In the case of the mutual comparison method within the chip,
As for whether or not the problem of
Although it is difficult to identify whether the frame memory is defective,
When multiple frame memories are arranged in one chip
If at least one is bad, the chip
It becomes a defective product as a body, and as a nonstandard product
Because it is sorted, whether it is a good product or not according to the above
If it can be confirmed, it is considered sufficient.

In testing the frame memory according to the present invention ,
When one frame memory of the double buffer system is used as a test buffer, the contents of the other frame memory are copied to the test buffer. Therefore,
If a comparison test is performed between the contents of one frame memory, that is, the test buffer and the contents of the other frame memory, a defective portion of the frame memory can be diagnosed.

At this time, the frame memory operates under exactly the same conditions as the actual clock frequency and the like, so that there is no need to separately provide a test timing generation circuit, and a real-time dynamic test is realized.

Further, it is not necessary to visually check the test pattern itself displayed on the display, and the operator only has to wait for the determination result to be obtained. As a result, fatigue of the operator is eliminated, an accurate determination result is always obtained, and the test speed is dramatically improved.

[0021]

FIG. 2 is a diagram showing the system configuration of an example of a display employing a double buffer type frame memory. The user can directly write data from the application according to the purpose of use.
For example, the user designates necessary graphic data such as a start point and an end point of a line segment, center coordinates of a circle, a radius, and the like, and a range 202 to be displayed on a display 207 such as a color CRT. The graphics processor 203 sequentially reads out the designated contents, and executes coordinate conversion and clipping, that is, cutout processing. The drawing control unit 205 stores the extracted data 20
4 is converted into dot information on the screen. The dot information is written into the double buffer type frame memory 206 while the writing / reading is controlled by the frame memory interface circuit 109. A frame memory 206 of the double-buffer method, since storing one dot of data per pixel on the screen in one plane, the frame memory if eight planes, and 2 ⁸ colors, that 256-color display.

Double buffer type frame memory 20
The content of No. 6 is input to the RAMDAC 111 including a color look-up table and a D / A converter for converting digital color information into display colors on a screen, converted into RGB signals, and supplied to the display 207. The display 207 displays a graphic or the like specified by the RGB signal.

FIG. 3 is a diagram showing a schematic configuration of the VRAM. VRAM is a random access memory RAM10
5 and the SAM 107, and the data in the RAM 105 is transmitted to the RAM 105 via the random data input / output port I / O 301.
AM107 data is serial data input / output port SI
This is a DRAM having a multi-port configuration capable of independently and asynchronously writing / reading via / O306.

The RAM 105 and the SAM 107 have a data transfer function capable of exchanging data bidirectionally. When the row address signal RAS 303 falls, the data transfer / output enable signal DT / OE 309 is low, and the data transfer operation is performed. Become. In this state, when the write enable signal WE302 is Low, data is transferred from the SAM 107 to the RAM 105, that is, the RAM 10
5 and the WE signal 302 becomes H
At the time of "high", a read transfer operation is performed in which the data is transferred from the RAM 105 to the SAM 107, that is, the data is read from the RAM 105.

The data transfer operation is performed by the SI / O 306
Determine the input and output of. During read transfer operation, SI /
O306 is a serial read operation, accessed in synchronization with the rising edge of the serial clock signal SC308, and the data of the SAM 105 is output from the SI / O306. At this time, the serial enable signal SE307
Is High, SI / O 306 is High-Z
However, the internal pointer is incremented by the rising edge of the SC signal 308. On the other hand, at the time of the write transfer operation, the SI / O 306 becomes a serial write operation, and is accessed in synchronization with the rising edge of the SC signal 308 to fetch the data of the SI / O 306 into the data register, as in the serial read operation. At this time, if the SE signal 307 is set to High, the data of the SI / O 306 is not fetched, but the internal pointer is incremented.

FIG. 1 is a block diagram showing the configuration of an embodiment of a test apparatus for a double buffer type frame memory according to the present invention.

The test buffer select circuit 112 uses a designated frame memory as a test buffer at the time of a test, and sets the operation of the VRAM constituting the test buffer to a write transfer operation, that is, a serial write operation in which data is written from SI / O. Circuit. Test buffer select circuit 112 decodes WE signal 114, test mode signal 115, and test buffer designation signal 106, and outputs WE signal 117 and WE signal 118. W
An E signal 114 determines a read transfer operation or a write transfer operation, a test mode signal 115 indicates that a test is being performed, and a test buffer designation signal 106 indicates which of the frame memory 101 and the frame memory 102 Is specified. The WE signal 117 is
The read / write transfer operation of the frame memory 101 is determined, and the WE signal 118 determines the read / write transfer operation of the frame memory 102.

When testing the frame memory 101,
During a data transfer operation, the WE signal 117 becomes High,
SI / O enters a serial read operation state. Meanwhile, WE
The signal 118 goes low, and the SI / O enters a serial write operation state. The test data is written to the RAM 105 of the VRAM 103 via the data bus 121, and is further transferred to the SAM 107 by a read transfer operation. The display data 124 read from the SAM 107 by the serial read operation is written to the SAM 108 of the VRAM 104 connected by the serial bus 122 by the serial write operation, and further transferred to the RAM 106 by the write transfer operation.

Therefore, in the present invention, the RAM 106
Is read out via the data bus 121, and the frame memory interface circuit 109 executes, for each bit, a comparison test for calculating an exclusive OR of the written data and the read data, for example. The result is
It is reported to the CPU 110 as error information 113,
Collect data on AM failures. Further, when there is data indicating a defective portion, a method of displaying a warning or an error message on a display or performing automatic selection may be adopted.

When testing the frame memory 102, the same operation as described above can be achieved by setting the WE signal 117 to Low and the WE signal 118 to High during the data transfer operation.

In this embodiment, an example is shown in which the frame memory comprises two frame memories 103 and 104. However, it is apparent that the number of frame memories may be larger. In this case, a method of using any one frame memory as a test buffer and testing the remaining frame memories, or a method of dividing the whole into two and applying the test method of the above embodiment to these sections is adopted. it can.

Further, by comparing the image data before writing to one frame memory with the image data passing through the one frame memory and the other frame memory to which the image data has been transferred, the total of both frame memories can be obtained. It is also possible to determine whether the quality is satisfactory , that is, whether all are good or at least one is bad .

[0033]

According to the present invention, when testing one frame memory of the double buffer type frame memory,
Use the other frame memory as a test buffer,
SA of n VRAMs constituting one frame memory
The display data output from M under the same conditions as the actual operation is input to the SAMs of n VRAMs constituting the other frame memory, and the contents of one frame memory are compared with the contents of the other frame memory. Since information on defective portions of the n VRAMs constituting the frame memory is collected, it is not necessary to separately provide a test timing generation circuit, and a real-time dynamic test is realized.

Further, it is not necessary to visually check the test pattern itself displayed on the display, and the operator only has to wait for the determination result to be obtained. As a result, fatigue of the operator is eliminated, an accurate determination result is always obtained, and the test speed is dramatically improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a test apparatus for a double buffer type frame memory according to the present invention.

FIG. 2 is a diagram showing a system configuration of an example of a display employing a double buffer type frame memory.

FIG. 3 is a diagram showing a schematic configuration of a VRAM.

[Explanation of symbols]

 101 frame memory 102 frame memory 103 VRAM 104 VRAM 105 RAM 106 RAM 107 SAM 108 SAM 109 frame memory interface circuit 110 CPU 111 RAMDAC 112 test buffer select circuit 113 error information 114 WE signal 115 test mode signal 116 test buffer designation signal 117 WE signal 118 WE signal 120 Data bus 121 Data bus 122 Serial data bus 123 Transfer signal 124 Transfer signal 201 Logical space segment buffer 202 Range to display 203 Graphics processor 204 Cut out data 205 Drawing control unit 206 Double buffer frame memory 207 Display 301 Random data input / output port I / O 3 2 WE signal 303 RAS signal 304 Ai signal 305 CAS signal 306 SI / O 307 SE signal 308 SC signal 309 DT / OE signal

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI G11C 29/00 675 G11C 29/00 675D (72) Inventor Takehiko Nishida 5-2-1 Omika-cho, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi, Ltd. Inside the Omika Plant (72) Inventor Kunio Suzuki 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Process Computer Engineering Co., Ltd. (72) Masahiro Yokoyama 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture No. Hitachi Process Computer Engineering Co., Ltd. (56) References JP-A-3-92893 (JP, A) JP-A-3-58088 (JP, A) JP-A-63-282785 (JP, A) Hei 2-16629 (JP, A) Actual opening Hei 2-107193 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G09G 5/00-5/40 G 06F 11/22 G06F 12/16 G11C 29/00

Claims (6)

(57) [Claims] 1. A having a plurality of screens divided frame memory for storing image data of a plurality of multi-port VRAM, in the test method of the frame memory of the double buffer method for displaying by switching these image data to the display, whereas When testing one frame memory, the other
The memory is used as a test buffer, and the operation is performed from the VRAM that constitutes the one frame memory.
Display data output under the same conditions as
Input to the VRAM constituting the memory, and the contents of the one frame memory and the other frame are input.
The contents of the memory are compared with each other, and information on defective portions of the VRAM constituting the frame memory is obtained.
A frame memory test method, which collects information. 2. A having a plurality of screens divided frame memory for storing image data of a plurality of multi-port VRAM, in the test method of the frame memory of the double buffer method for displaying by switching these image data to the display, whereas When testing one frame memory, the other
Memory as a test buffer, and the n video runs forming the one frame memory
Serial access memory of dumb access memory VRAM
Display data output from SAM under the same conditions as actual operation
S of n VRAMs constituting the other frame memory
AM and the contents of the one frame memory and the other frame
Compare the contents of the memory and determine the number of defective VRAMs that constitute the frame memory.
A method for testing a frame memory, comprising collecting information on places . 3. The method for testing a frame memory according to claim 1 , wherein said method includes the steps of:
Conversely, a test buffer one frame memory above
Production from the VRAM to use, constitutes the other frame memory
Display data output under the same conditions as
And the contents of the other frame memory and the one frame.
Compare the contents of the memory and determine the number of defective VRAMs that constitute the frame memory.
A method for testing a frame memory, comprising collecting information on places . 4. Have multiple screens min frame memory for storing image data of a plurality of multi-port VRAM, in the test method of the frame memory of the double buffer method for displaying by switching these image data to the display, whereas When testing one frame memory, the other
The memory is used as a test buffer, and the image data before writing to the other frame memory, the frame memory and the image data are transferred.
Comparing the image data having passed through the frame memory of the one, at least one or all good that the two frame memories
A test method for a frame memory, which determines whether or not the frame memory is defective . 5. Have multiple screens min frame memory for storing image data of a plurality of multi-port VRAM, the test device of the frame memory of the double buffer method for displaying by switching these image data to the display, whereas When testing one frame memory, the other
Means for writing test pattern data to the other frame memory memory as the test buffer, the test pattern data of the test buffer Meanwhile
And means for forwarding the frame memory, wherein the test pattern data from the test buffer
Comparing the test pattern data from one frame memory, the test device of the frame memory, comprising the means for determining the quality of the frame memory. 6. The frame memory test apparatus according to claim 5, further comprising: a test buffer select circuit for designating any one of the plurality of frame memories as the test buffer. Testing equipment.