JPH05216448A - Test method and test device for frame memory - Google Patents

Abstract

PURPOSE:To provide a test method and a test device for a frame memory which can automatically execute a test of a frame memory composing a frame memory of double buffer system in the quite same conditions as the actual operations without depending on visual confirmation or the like. CONSTITUTION:When a frame memory 101 of one of a double buffer system is tested, the other frame memory 102 is used as a test buffer, display data outputted from a SAM 107 of a VRAM 103 of n pieces which composes the frame memory 101 in the same conditions as the actual operation is inputted to a SAM 108 of a VRAM 104 of n pieces which composes the frame memory 102, contents of the frame memory 101 is compared with contents of the frame memory 102, and information about malfunction parts of the VRAM 103 of n pieces which composes the frame memory 101 is collected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory test method and test apparatus, and more particularly to a means for dramatically improving the test efficiency and test accuracy of defects in a frame memory employing a double buffer system. is there.

[0002]

2. Description of the Related Art Information to be displayed on a display by a user is converted into dot information on a screen by a drawing control unit and written in a frame memory while being controlled by a frame memory interface circuit. The data written in the frame memory is input to the random access memory D / A converter RAMDAC as display data.
This RAMDAC is a color lookup table that converts digital color information into display colors on the screen and a digital
Including an analog converter or D / A converter,
The display data is converted into RGB signals and supplied to the display. The display displays the information required by the user in color.

If there is a defect in the frame memory when displaying on the display, normal display cannot be performed. The conventional test method for the defect of the frame memory includes, for example, (1) a test method in which the display data of the frame memory is displayed as an image on a display and visually diagnosed. (2) the display data and the display data input to the RAMDAC. Alternatively, a method test comparing with a reference value (Japanese Patent Laid-Open No. 63-2
82785, JP-A-1-173123, etc.).

[0004]

In the first test method, the test pattern displayed on the display is visually confirmed, so that the operator is easily tired, the judgment becomes inaccurate, and the test speed cannot be increased. ..

In the second test method, when the display data input to the RAMDAC is read and tested, the operation speed of the test register is low, so that the frame memory interface circuit and the RAMDAC which are peripheral circuits of the frame memory. It is necessary to lower the operation clock of, the test timing generation circuit has to be added, and moreover, there is a drawback that the dynamic test in the essential real time cannot be performed.

An object of the present invention is to test a plurality of frame memories constituting a double-buffer type frame memory automatically under the same conditions as the actual operation without any visual confirmation. A test method and a test apparatus are provided.

[0007]

The above object is to configure one frame memory by using the other frame memory as a test buffer when testing one frame memory in a double buffer type frame memory.
Display data output from the serial access memory SAM of the video random access memories VRAM under the same conditions as the actual operation, and n V constituting the other frame memory.
This is achieved by inputting to the SAM of the RAM, comparing the contents of one frame memory with the contents of the other frame memory, and collecting information on the defective portion of n VRAMs forming one frame memory. ..

At the time of testing the other frame memory, contrary to the above method, one frame memory is used as a test buffer, and the SAMs of n VRAMs constituting the other frame memory are operated under the same conditions as the actual operation. The display data to be output is input to the SAMs of the n VRAMs forming one frame memory, the contents of the other frame memory are compared with the contents of the one frame memory, and the n pieces of the other frame memory are formed. Information on defective parts of the VRAM will be collected.

That is, in order to achieve the above-mentioned object, the present invention has a plurality of frame memories for storing image data, which are composed of a plurality of multiport VRAMs, and display these image data by switching them. In a double buffer type frame memory test method, an arbitrary one frame memory is used as a test buffer for the remaining frame memories, and a frame memory test method for determining the quality of the remaining frame memories is proposed.

More specifically, the display data read from the SAM of the VRAM forming one arbitrary frame memory is the SA of the VRAM forming the remaining frame memory.
2 VRA
This is a method of comparing the contents of M and determining the quality of the frame memory.

It is also possible to reverse the direction of data transfer between the arbitrary one frame memory and the remaining frame memories, and determine the quality of the arbitrary one frame memory.

In order to achieve the above object, the present invention also provides the image data before being written in the arbitrary one frame memory and the image that has passed through this frame memory and the other frame memory to which the image data has been transferred. The present invention proposes a method for testing a frame memory, which compares the data with data and judges the overall quality of both frame memories.

The invention further provides a plurality of multiport VRs.
In a double-buffer type frame memory test device that is composed of AM and has a plurality of frame memories for storing image data, and switches these image data to display on a display, any one frame memory is used as a test buffer. The means for writing the test pattern data to this frame memory, the means for transferring the test pattern data from the test buffer to the remaining frame memory, the test pattern data from the test buffer and the test pattern data from the remaining frame memory are compared. The present invention proposes a frame memory test apparatus having means for determining the quality of the remaining frame memories.

This test apparatus can also be provided with a test buffer select circuit for designating any one of a plurality of frame memories as the test buffer.

[0015]

In the frame memory test, when one frame memory of the double buffer system is used as the test buffer, the contents of the other frame memory are copied to the test buffer. Therefore, if the contents of one frame memory, that is, the test buffer and the contents of the other frame memory are compared and tested, the defective portion of the frame memory can be diagnosed.

At this time, since the frame memory operates under exactly the same conditions as the clock frequency and the like, it is not necessary to separately provide a test timing generation circuit, and a real-time dynamic test is realized.

Further, the work of visually confirming the test pattern itself displayed on the display becomes unnecessary, and the operator only has to wait for the determination result to come out. As a result, operator fatigue is eliminated, accurate judgment results are always obtained, and the test speed is dramatically improved.

[0018]

FIG. 2 is a diagram showing a system configuration of an example of a display adopting a double buffer type frame memory. The user can directly write from the logical space segment buffer 2 according to the purpose of use.
In 01, necessary graphic data such as a start point, an end point of a line segment, a center coordinate of a circle, a radius, and the like, and a range 202 to be displayed on a display 207 such as a color CRT are designated. The graphics processor 203 sequentially reads the designated contents, and executes coordinate conversion and clipping, that is, clipping processing. The drawing control unit 205 uses the extracted data 20.
4 is converted into dot information on the screen. This dot information is written in the double buffer type frame memory 206 while being controlled by the frame memory interface circuit 109 for writing / reading. Since the double buffer type frame memory 206 stores data of 1 dot per pixel on the screen in 1 plane, if the frame memory is 8 planes, 2 ⁸ colors, that is, 256 colors are displayed.

Double buffer type frame memory 20
The content of 6 is input to the RAMDAC 111 including a color lookup table and a D / A converter that converts digital color information into a display color on the screen, converted into an RGB signal, and supplied to the display 207. The display 207 displays a graphic or the like designated by the RGB signal.

FIG. 3 is a diagram showing a schematic structure of the VRAM. VRAM is a random access memory RAM10
5 and the SAM 107, and the data in the RAM 105 is transferred to the S via the random data input / output port I / O 301.
The data of AM107 is serial data input / output port SI
A DRAM having a multi-port configuration capable of independent asynchronous write / read operations via / O306.

The RAM 105 and the SAM 107 have a data transfer function capable of bidirectionally exchanging data. When the row address signal RAS 303 falls, the data transfer operation is performed when the data transfer / output enable signal DT / OE 309 is Low. Become. In this state, when the write enable signal WE302 is Low, data is transferred from the SAM 107 to the RAM 105, that is, the RAM 10
The write transfer operation of writing to 5 is performed, and the WE signal 302 becomes H.
When it is high, the read transfer operation is performed in which data is transferred from the RAM 105 to the SAM 107, that is, read from the RAM 105.

The data transfer operation is performed by the SI / O 306.
Determine the input and output of. SI / during read transfer operation
O306 is a serial read operation, is accessed in synchronization with the rising edge of the serial clock signal SC308, and the data of the SAM 105 is output from the SI / O306. At this time, the serial enable signal SE307
Is set to High, SI / O306 becomes High-Z.
However, the internal pointer is incremented by the rising edge of the SC signal 308. On the other hand, during the write transfer operation, the SI / O 306 becomes a serial write operation, and similarly to the serial read operation, the SI / O 306 is accessed in synchronization with the rising edge of the SC signal 308 and fetches the data of the SI / O 306 into the data register. At this time, if the SE signal 307 is set to High, the data of SI / O 306 is not taken in, but the internal pointer is incremented.

FIG. 1 is a block diagram showing the configuration of an embodiment of a double buffer type frame memory test apparatus according to the present invention.

During the test, the test buffer select circuit 112 uses the designated frame memory as a test buffer, and the operation of the VRAM forming the test buffer is a write transfer operation, that is, a serial write operation in which data is written from SI / O. Circuit. Test buffer select circuit 112 decodes WE signal 114, test mode signal 115, and test buffer designation signal 106, and outputs WE signal 117 and WE signal 118. W
The E signal 114 determines whether it is a read transfer operation or a write transfer operation, the test mode signal 115 indicates that a test is in progress, and the test buffer designation signal 106 determines which of the frame memory 101 and the frame memory 102 is the test buffer. Specify whether to The WE signal 117 is
The read / write transfer operation of the frame memory 101 is determined, and the WE signal 118 determines the read / write transfer operation of the frame memory 102.

When testing the frame memory 101,
During the data transfer operation, the WE signal 117 becomes High,
SI / O is in a serial read operation state. On the other hand, WE
The signal 118 becomes Low, and SI / O becomes the serial write operation state. The test data is written in the RAM 105 of the VRAM 103 via the data bus 121 and further transferred to the SAM 107 by the read transfer operation. The display data 124 read from the SAM 107 by the serial read operation is written in the SAM 108 of the VRAM 104 connected by the serial bus 122 by the serial write operation, and further transferred to the RAM 106 by the write transfer operation.

Therefore, in the present invention, the RAM 106
Is read out via the data bus 121, and the frame memory interface circuit 109 executes, for each bit, a comparison test for calculating an exclusive OR of the written data and the read data. The result is
The error information 113 is reported to the CPU 110 and VR
Collect data on defective parts of AM. Further, when there is data indicating a defective portion, a method of displaying a warning or error message on a display or automatically selecting may be adopted.

When testing the frame memory 102 side, if the WE signal 117 is set to Low and the WE signal 118 is set to High during the data transfer operation, the same operation is performed.

In this embodiment, the example in which the frame memory is composed of the two frame memories 103 and 104 is shown, but it is obvious that the number may be larger. At that time, an arbitrary one frame memory is used as a test buffer and the remaining frame memory is tested, or a method of dividing the whole into two and applying the test method of the above-mentioned embodiment to these divisions is adopted. it can.

By comparing the image data before being written in one of the frame memories with the image data that has passed through the one frame memory and the other frame memory to which the image data has been transferred, the total data of both frame memories is compared. It is also possible to determine whether the quality is good or bad.

[0030]

According to the present invention, when testing one frame memory of the double buffer type frame memory,
Use the other frame memory as a test buffer,
SA of n VRAMs constituting one frame memory
Display data output from M under the same conditions as the actual operation is input to the SAMs of n VRAMs forming the other frame memory, the contents of one frame memory are compared with the contents of the other frame memory, and Since the information on the defective portion of the n VRAMs constituting the frame memory is collected, it is not necessary to separately provide a test timing generation circuit, and a dynamic test can be realized in real time.

Further, the work of visually confirming the test pattern itself displayed on the display becomes unnecessary, and the operator only has to wait for the determination result to come out. As a result, operator fatigue is eliminated, accurate judgment results are always obtained, and the test speed is dramatically improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a double-buffer type frame memory test apparatus according to the present invention.

FIG. 2 is a diagram showing a system configuration of an example of a display that employs a double buffer type frame memory.

FIG. 3 is a diagram showing a schematic configuration of a VRAM.

[Explanation of symbols]

 101 frame memory 102 frame memory 103 VRAM 104 VRAM 105 RAM 106 RAM 107 SAM 108 SAM 109 frame memory interface circuit 110 CPU 111 RAMDAC 112 test buffer select circuit 113 error information 114 WE signal 115 test mode signal 116 test buffer designation signal 117 WE signal 118 WE signal 120 data bus 121 data bus 122 serial data bus 123 transfer signal 124 transfer signal 201 logical space segment buffer 202 range to display 203 graphics processor 204 clipped data 205 drawing control unit 206 double buffer type frame memory 207 Display 301 Random data input / output port I / O 3 2 WE signal 303 RAS signal 304 Ai signal 305 CAS signal 306 SI / O 307 SE signal 308 SC signal 309 DT / OE signal

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location G11C 29/00 303 E 9288-5L (72) Inventor Mamoru Sueoka 5-2 Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Incorporated company Hitachi Ltd. Omika factory (72) Inventor Takehiko Nishida 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Incorporated Hitachi Ltd. Omika factory (72) Inventor Kunio Suzuki Omika Hitachi City, Ibaraki Prefecture 5-2-1, Machi, Hitachi Process Computer Engineering Co., Ltd. (72) Inventor, Masahiro Yokoyama 5-2-1, Omika-cho, Hitachi City, Ibaraki Prefecture

Claims (6)

[Claims] 1. A double buffer type frame memory test method comprising a plurality of frame memories for storing image data, each frame memory comprising a plurality of multiport VRAMs, and switching these image data to display on a display. One of the frame memories is used as a test buffer for the remaining frame memories, and the quality of the remaining frame memories is determined. 2. A double-buffer type frame memory test method comprising a plurality of frame memories for storing image data, each frame memory comprising a plurality of multiport VRAMs, and switching these image data to display on a display. Display data read from the SAM of the VRAM forming one of the frame memories is transferred to the remaining SAM of the VRAM forming the frame memory as write data and copied, and the contents of the two VRAMs are compared, A method of testing a frame memory, comprising determining whether the frame memory is good or bad. 3. The frame memory test method according to claim 1, wherein the direction of data transfer between the arbitrary one frame memory and the remaining frame memory is reversed, and the arbitrary one frame memory is tested.
A method of testing a frame memory, characterized by determining the quality of one frame memory. 4. A double buffer type frame memory test method comprising a plurality of frame memories for storing image data, each frame memory comprising a plurality of multiport VRAMs, and switching these image data for display on a display. The image data before being written in any one frame memory is compared with the image data passing through the frame memory and the other frame memory to which the image data has been transferred, and the overall quality of both frame memories is judged. A method for testing a frame memory, which is characterized in that 5. A double-buffer type frame memory test device having a plurality of frame memories for storing image data, the frame memory including a plurality of multiport VRAMs, and switching these image data for display on a display. A unit for writing test pattern data into the frame memory using one of the frame memories as a test buffer; a unit for transferring the test pattern data in the test buffer to the remaining frame memories; and a test pattern data from the test buffer. A test device for a frame memory, comprising: means for comparing the test pattern data from the remaining frame memory with each other to determine the quality of the remaining frame memory. 6. The frame memory test apparatus according to claim 5, further comprising a test buffer select circuit that specifies any one of the plurality of frame memories as the test buffer. Test equipment.