JPH0275086A - Picture processor - Google Patents

Abstract

PURPOSE:To increase the efficiency of a picture processing without generating the rise of the cost by constituting a picture memory of a dual port DRAM for a picture and a standard DRAM and corresponding to a picture displaying area and a buffer area. CONSTITUTION:A picture memory is composed of a dual port DRAM 14 for a picture and a standard DRAM 15 and the dual port DRAM 14 for the picture corresponds to a picture displaying area and the standard DRAM 15 corresponds to a buffer area. Based on the address when information is written in a memory for a picture, one of the picture displaying area or the buffer area is discriminated, the prescribed writing sequence corresponding concerning respective DRAM 14 and 15 is respectively and separately selected from the discriminated result and the writing to the memory for the picture is executed. Thus, even at the time of the picture memory to mix the dual port DRAM 14 for the picture and the standard DRAM 15, the optimum writing system is respectively selected and without generating the cost rise, the efficiency of the picture processing can be increased.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art (Figure 4.5) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems One Embodiment of the Invention ( Figures 1 to 3) Effects of the invention ((Existing) Regarding image processing device 2. Dual baud for images) Improving the efficiency of a memory system in which DRAM and standard DRAM coexist and providing a low-cost image processing device. The purpose is to.

A video RAM is used as an image memory, and the video RAM
In an image processing device that performs image processing by storing necessary image information in M, the image memory is composed of an M with an image DARBO+-DR and a standard DRAM, and the DRAM for images is configured in an image display area. Correspond and mark #
The DRAM corresponds to the buffer area, and also has an area determination means for determining either the image display area or the buffer area based on the address when writing information to the image memory, and an image dual port based on the output of the determination means. 1- select corresponding predetermined write sequences for DRAM and standard pDRAM, respectively;
a write control means for controlling writing to the image memory;
The system is configured to provide the following.

[Industrial Application Field] The present invention relates to an image processing device, and more particularly, to an image processing device in which a dual-port image DRAM and a standard DRAM are used to improve the efficiency of a mixed memory system.

Reflecting the recent remarkable development of LSI technology, the use of ■-5SI has been actively studied in the field of image processing as well. The major feature of the image signal is that pixels with a number of bits representing 25 shades and tones are arranged in a two-dimensional manner.
There are so many data stars to process.

(Prior art) In a general frame memory, all of the video No. 413 for one side (including synchronization signals, etc.), or at least the entire range of the video signal that is actually displayed (excluding the blanking period, etc.) The video RAM used for image processing has a memory area larger than one screen, and a portion of it is often allocated to the actual screen.

This is because the information contained in the video signal can be used effectively.

The first type of video RAM used is an image DRAM (or DRAM (sometimes simply called a dual port DRAM)). This D
RAM is a random baud 1- for normal reading and writing,
It has a serial port that can read data serially at high speed for video display. Also, the second
There is a standard Y$DRAM, which is not developed for image use, but is a general-purpose RAM.

When video RAM is used in a graphics device, not all areas of video RAM may need to be displayable. The non-displayable area is used as a buffer area, and in some cases, it may have a buffer area that is 8 times or more than the display area, or J2 times. Even if the display area is configured with an image dual-port DRAM, the buffer area may be configured with a standard DRAM. This is because standard DRAMs are cheaper. Therefore, in image processing apparatuses, a dual port 11) RAM for images and a standard DRAM have been used in combination as video RAM.

(Problem to be solved by the invention) However, in such an image processing device,
Imaging D-Arbor-1-D RAM Marked ij [I
Because it was configured to use both RAM and RAM,
In particular, since both write sequences are responsible, there is a problem in that the efficiency of image processing is low.

That is, when writing only to a specific bit position in one word of a standard DRAM, first read one word of the address to be occupied, change the value of only the specific bit position of the read data, and write the data. The sequence must be executed to write the result to the original address. On the other hand, in a dual-port image DRAM, writing can be performed at a specific bit position in one word by inputting a write mask specifying the bit position to be written and write data after multi-breathing.

Figure 4.5 shows the timing of each write sequence. Figure 4 shows the case of an image differential 6 Albor I DRAM, in which the rask address and write mask are input at the falling edge of the RAS signal, and the column address, data, and WE signal ( write enable signal). WE=0 indicates a write cycle.

On the other hand, FIG. 5 shows the case of a standard DRAM, which requires two write cycles. In the first read cycle, Rask address 1, column at 1/s, and WE multiplication signals are input in synchronization with the RAS and CAS signals. WE=
1 indicates a read cycle. Data is read out after a certain period of time after CAS=O. After the read data is processed externally, the processing results are written in the next memory cycle. For writing, the rask address, column address, and WE multiplication signals are input in synchronization with the RAS and CAS signals.

Dual-port DRAM for images can also perform the same write sequence as standard DRAM, so it is always possible to perform the same write sequence as standard DRAM.
If the write sequence as M is executed, there will be no functional difference, but the write speed will be reduced. Shimata is...
Signpost t? Dual port DRAM for DRAM and images
If you want to efficiently write and perform 7j on the ubiquitous video RAMs, you will need a means to select a 9-in/out sequence suitable for each DRAM. Conventionally, there was no means to select a write timing suitable for each, resulting in a decrease in efficiency.

On the other hand, if the configuration is made up of only a dual-baud DRAM for images, the processing efficiency will be improved, but the cost will be significantly increased by 1, which is not preferable.

Therefore, the present invention provides an image dual baud 1-1) RAM
The purpose is to improve the efficiency of a memory system in which DRAM and standard DRAM coexist, and to provide a low-cost image processing device.

[Means to solve the problem]

The image processing device according to the present invention achieves the purpose of IXI music,
A video RAM is used as an image memory, and the video R
In an image processing device that performs image processing by storing necessary image information in AM, the 11;I2 image memory is composed of a dual-baud 1-D RAM for images and a standard DRAM; RAM corresponds to the image display area, and RAM corresponds to the buffer area, and is an area for determining either the image display area or the buffer area based on the address when writing information to the image memory. a determining means; a writing control means for separately selecting corresponding predetermined 3-input sequences for the image dual port RAM and standard DRAM based on the output of the determining means and controlling writing to the image memory; ing.

[Effect]

In the present invention, the image memory is an image dual baud 1/DR
It is composed of AM and standard fDRAM, and the dual-baud (image) DRAM corresponds to the image display area, and the standard DRAM
M corresponds to the buffer area. Then, one of the image display area or the buffer area is determined based on the address used when writing information to the image memory, and based on this determination result, the image display area (dual baud) DRAM and standard DRAM
Two corresponding predetermined writing sequences for M are selected separately and written into the image memory (7).

Therefore, image data 1-T') RAM
Even if the image memory includes a mixture of point sources z=D RAM, the optimal embedding system is selected for each, and the efficiency of image processing is increased without causing an increase in cost.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing embodiments of an image processing apparatus according to the present invention. First, the configuration will be explained. FIG. 1 is an overall configuration diagram of an image processing apparatus. In this figure, 1 is the host CP tJ, and the host cpT,J 1 manages the entire device to perform the control necessary for image processing, and sends the control commands to the drawing address calculation circuit 3 and the display area via the host path 2. output to the display area lower limit register 4 and display area lower limit register 5. The drawing address calculation circuit 3 generates addresses, write masks, and write data for areas corresponding to images to be drawn, such as straight lines, circles, rectangles, etc., and sends each data to buses 6 to 6.
The detailed circuit configuration will be described later. The write mask indicates which pin I/position of word F41 is to be written.

The drawing address calculation circuit 3 also generates display addresses.

The display area 1-1 limit register 4 holds the upper limit of the address of the display area, and the display area lower limit register 5 similarly holds the lower limit of the address and outputs the held addresses to the magnitude comparison circuits 9 and 10. . Note that although data is transferred via a bus, only the lotus (1), which is required to correspond to a symbol, will be explained, and parts that can be clearly understood will be omitted to avoid redundant explanations.

The magnitude comparison circuit 9 compares the at 1/s output from the drawing address 5 I calculation VgJ path 3 with the upper limit address held by the display area "- limit I register 4 to determine the magnitude relationship, and calculates the magnitude relationship. It is output to the input control circuit 11. Also,
Similarly, the magnitude comparison circuit 10 compares the address output from the drawing address correction circuit 3 with the lower limit address destination held by the display area lower limit 1/register 5 to determine the magnitude relationship, and writes the result to the control circuit 11 Output to. -h writing both F address meter tγ circuit 3, display area upper limit register 4, display area lower limit L register 5, and magnitude comparison circuit 9.10 constitute area determination means 18 as a whole.

The write control circuit (corresponding to write control means) 11 calculates control values for executing different write sequences based on the comparison results of the magnitude comparison circuit 9.10, and sends the necessary address and data to the bus I2.13. The detailed circuit configuration will be described later. , the writing sequences are different because the configurations of the memo January 1.15 are different, and the optimal sequence is given to each. The display memo 4 corresponds to the displayable memory area, and is composed of a dual port DRAM for images, its random port is connected to the write control circuit 11, and its serial port is connected via the bus 16. Shift for video output! /
It is connected to register 17. On the other hand, the buffer memory 15
corresponds to a memory area used as a buffer, and is composed of an inexpensive general-purpose standard DRAM. Each memory 14, 15 corresponds to a so-called image memory and each operates with a different write sequence. The shift I register 17 outputs the data sent from the display memory 14 in units of 1 word in units of 1 bit, and outputs the data as a video output.

Next, the drawing address calculation circuit 3 and the write control circuit 1
The detailed circuit configuration of No. 1 will be explained. First, the drawing address calculation circuit 3 will be explained using FIG. In FIG. 2, the drawing address calculation circuit 3 is the linear coordinate calculation circuit 21.
, control circuit 22, memory width register 23, adder 24,
The pattern register 25 is composed of a 4-bit counter 26, a selector 27, a linear address register 28, and a bit decoder 29, and each element is connected by a bus.

A linear coordinate calculation circuit 21 calculates the coordinates of a straight line and outputs changes in the coordinates of the straight line as 4-bit movement information. When drawing a straight line with points, the change in the X coordinate, yP + y, when moving from one point to the next is either O, + 1, or -1, and this amount of movement can be expressed as follows: It is converted into a 4-pino l□ code and sent to the control circuit 22.

Table 1 However, U2, * does not mean ignored.

The linear address register 28 is an I register that holds the address of the drawing point on the graph ink screen, and the point (
The linear address of x, y) is defined as follows.

LA=LAO+x+y-wL6 However, 1 word - 16 bits.

LA, L,, AO are 20 pits.

LAO: Linear address of origin W; Width of graph ink screen (unit: word) In this case, linear address LA (upper 16 bits/7 of A),
is used as a word address to select one word of memory, and the lower 4 bits are used as a bit address to select 16 bits in one word.

Furthermore, the memory width specifies the width of the graphic screen on the memory. For example, in the case of W..5, the relationship between the screen and the word address is as follows.

Table 2 For example, if the linear address is 82 in hexadecimal, -
This means that the third bit from the left of word address 8 in Table 1 is specified.

The control circuit 22 generates a control value for updating the linear address register 28 based on the movement information υ received from the linear coordinate calculation circuit 21, and changes the rear address register 23 by changing x, y.・, Update the value as follows.

x←−x±l <=> I−A ←L A±1
y=y:→-1<=> LA Cow-LA! :w
-16 The control circuit 22 also performs control to update the pattern read position every time one point is drawn.

The pattern register 25 specifies a pattern for drawing a straight line, and the pattern register 25 ((KIint
16 bits are input to the selector 27, and the selector 27 selects and outputs 1 bit from the 16 bits.The selection is based on the value of the 4-bit counter 26 (,
The 4-bit counter 26 is set to 1 based on the output of the control circuit 22.
Counts up every time a point is drawn.

The output of the selector 27 is expanded by connecting the lotus F- in the part A in the figure to 16 bits, and becomes 16-bit write data. The focus decoder 29 decodes which bit in 1 word F' the bit address part of the rear address register 28 refers to, and in reality it is a 4-bit input/16-bit input. This is an output decoder, and this 16-bit output becomes a write mask.

On the other hand, the detailed circuit configuration of the write control circuit 11 is shown in FIG. In FIG. 3, the S-inclusive control circuit 11
control unit 31, address register 32, mask register 33, data register 34, merge unit 35
, an output register 36, an input register 37, and buffers 38 to 40, and each element is connected by a lotus. The control unit 31 receives each comparison result I and ■ from the magnitude comparison circuit 9.10, and writes it to the display memo January 4 when both the comparison results I and ■ are "1". If not, the buffer memo will be filled in on January 5, 9. Output to.

The output from the drawing address calculation circuit 3 is input to an address register 32, a mask register 33, and a data register 34, respectively. The address register 32 sets an address, the mask register 33 sets a write mask, and the data register 34 sets the write date. Also, the address register 32 is the buffer 1
Atto L/S for reading the value of memory 15 for
-The data read from the buffer memory is input to the manual register 37. The merge unit 35 merges the values of the input register 37 and the data register 34 and outputs the result to the output 1/.zoster 3[;, and the output register 36 outputs the merged output. Merging is done as follows.

di'=mi-di4-mi-xi (i=0.],..., n) where di: 1 bit of Din xi: 1 bit of X I mi: 1 pin of X 1~ ai': 1 bit of Dout - That is, when the mask (M) input is a "0" bit, Din is output as is, and pin 1 of 'J' outputs X. The value of the output register 36 is sent to the buffer memory 39 through the buffer 39 and is filled in. Similarly, the value of the mask register 33 and the value of the data register 34 are sent to the buffer 38 and the buffer 34, respectively. 40 as a data output to an external display memo or a memory for a sofa.The address at the start of the X-input recycle is given from the address register 32, and in the first half of the write cycle the value of the mask register 33 is through the buffer 38 (output to the data register 34 in the latter half)
The value of is outputted to the outside through the buffer 40, and the write sequence ends.

Next, the effect will be explained.

Marked as image memory? , cost can be reduced by mixing QDRAM and image dual-baud 1-DRAM.
However, although it can function as an image memory, the R-inclusive sequence is different, resulting in a decrease in efficiency.

Therefore, in this embodiment, we focused on the fact that the addresses of the buffer area made up of standard DRAM and the display area made up of image channel hDRAM are different, and we monitored the address at the time of writing and checked the address. The speech sequence is determined by determining which region it is. The following two methods can be considered for determining the area.

(a) Determination in units of 3 write cycles Check the memory address for each memory write and select the write sequence. It depends on the case, but in general, the speed of 9-in and 7-j is reduced due to address monitoring.

(b) Judgment for each drawing command Judgment is made for each -l cloak such as straight line drawing, circle drawing, rectangular area transfer, etc. Monitor only the memory address of the drawing command starting point. Although the operation speed does not decrease due to address monitoring, even if the memory address of the drawing command start point is in the display area, the drawing point may move beyond the display area and into the buffer area during the execution of the drawing command. .

In that case, care must be taken because writing within the buffer area may not be performed normally.

In this embodiment, method (n) above is used.

That is, the specific drawing process is performed as follows.

(1) Initial jtJl setting The host CPU 1 sets the upper limit of the display area address in the display area upper limit register 4 and the lower limit in the display area lower limit register 5.

(n) At the start point of the drawing operation +-CP tJ 1, four drawing commands are provided to the drawing address calculation circuit 3.

(III) Drawing operation The drawing at 1/s calculation circuit 3 calculates the memory address of the figure to be drawn and the bit position within the word. The calculated results are output as an address and indentation mask. Data to be written at the same time is also output.

(IV) Address Check The address output from the drawing address calculation circuit 3 is checked by the magnitude comparison circuit 9.10 to see if it is within the display area using the following equation.

Display area lower limit≦address≦display area upper limit If this formula is established, the address to which writing is attempted will be within the display area.

(V) Inclusion of V into the memory Depending on the comparison result from the magnitude comparison circuit 9.10, the embedding control circuit 11 distinguishes between the display area and the buffer area, and performs the embedding operation according to the area as follows. It will be done.

1) In the case of the display area, the S-included mask and the included data are output as multiple breaths and written to the display memories 1 and 4.

be included. The bit position to be inserted is selected using the display memory 14.
Writing is completed within one memory cycle.

ii) In the case of a buffer area, the word specified by the address is read into the write control circuit 11, and of the read data, only the bits whose write mask is "1" are rewritten as occupying data as shown below.

Table 3 After that, the leftover message is output to the buffer memory 15, and the contents of the buffer memory 15 are replaced.

On top of this, in this example, dual baud for images) r)
The memory area of the RAM and the memory area of the standard DRAM are determined based on the address, and from the results of this determination, the optimal write sequence is selected for each of the display memory 14 and the sofa memory 14. Therefore, even in a memory system in which a dual-baud DRAM for images and a standard DRAM coexist, it is possible to improve the efficiency of image processing while avoiding an increase in cost.

〔Effect of the invention〕

According to the invention, dual baud 1-D RAM for images
Even if the image memory contains a mixture of DRAM and DRAM, the optimal filling sequence for each can be selected to increase the efficiency of image processing without increasing costs.
I can do two things.

[Brief explanation of the drawing]

Figures 1 to 3 are diagrams showing an embodiment of the image processing apparatus according to the present invention. Figure 1 is an overall configuration diagram thereof, Figure 2 is a detailed circuit diagram of its drawing address calculation circuit, and Figure 3 Figure 4 is a detailed circuit diagram of the write control circuit, Figure 4 is a diagram showing the write sequence of the image D1Arbor-1-D RAM, and Figure 5 is a diagram showing the write sequence of the standard DRAM.
(This is a diagram. 1... Host CPU. 3... Drawing address calculation circuit (writing control means), 4... Display area 1 unit limit register, 5... ...
・Display area lower limit register, 6 to 8.12.13.1G・
... Bus, 18 ... Area determination means. 71″4:=X-=■2■:C Yonini 6Y-knee data ---C2 #2 Figure 11A shows the standard DRAM write sequence.
figure

Claims (1)

[Claims] An image processing device that uses a video RAM as an image memory and performs image processing by storing necessary image information in the video RAM, wherein the image memory is a dual-port image DRAM and a standard DRAM. The dual-port image DRAM corresponds to the image display area, the standard DRAM corresponds to the buffer area, and one of the image display area or buffer area is allocated based on the address when writing information to the image memory. A dual-port DRAM for image processing based on the output of the region discrimination means and the discrimination means.
and write control means for separately selecting corresponding predetermined write sequences for the standard DRAM and controlling writing to the image memory.