JPH02257293A - Access circuit for memory for mask - Google Patents

Abstract

PURPOSE:To shorten the access time of a memory for mask by dividing the memory for mask into plural areas and parallelly deciding the writing of mask data concerning the respective areas. CONSTITUTION:A memory 111 for mask is divided into the plural areas and the mask data are stored to the respective areas in order to instruct the display and non-display of a picture element. A write deciding means 141 decides whether the respective address data to be outputted from an address preparing means 131 corresponding to the plural areas are included in a range for the display and non-display of the picture element to be designated by coordinate data to be outputted from a mask area storing means 121 or not. Thus, since the memory 111 for mask is divided into the plural areas and the writing of the mask data is parallelly decided concerning the respective areas, the access time of the memory 111 for mask can be shortened.

Description

[Detailed description of the invention] 〔table of contents〕 overview Industrial applications Conventional technology Problems that the invention aims to solve Means to solve problems action Example I.

■.

■.

Correspondence between the embodiment and FIG. 1 Structure of the embodiment Operation of the embodiment (1) Write data creation operation (ii) Write judgment operation (iii) Mask data write operation ■, Summary of the embodiment ■1 Modification of the invention Effects of the Aspect Invention [Summary] Reduction of the access time of the mask memory, regarding a mask memory access circuit that accesses the mask memory that stores information regarding display/non-display of image data in image processing of computers, etc. For the purpose of Area storage means, address generation means for outputting address data for simultaneously accessing multiple areas of the mask memory, and address data corresponding to the plurality of areas outputted from the address generation means, respectively, from the mask area storage means. It is equipped with a writing determination means for determining whether or not a pixel specified by the output coordinate data is included in the display/non-display range, and writes mask data in parallel to each area in which the mask memory is divided. Configure to perform write processing.

[Industrial application field]

The present invention relates to a mask memory access circuit that accesses a mask memory that stores information regarding display/non-display of image data in image processing by a computer or the like.

[Conventional technology]

2. Description of the Related Art Some recent image processing systems such as computers are equipped with a mask memory for displaying so-called multi-windows or displaying characters overlaid on a natural image or the like.

Each bit data stored in this mask memory corresponds to each display pixel, and whether or not a corresponding pixel is displayed on a display or the like is determined by the bit data in this mask memory.

In this way, the display state (mask state) of a pixel can be changed simply by rewriting the bit data in the mask memory, making it suitable for high-speed processing of moving images and the like.

FIG. 5 shows a conventional mask memory access circuit.

In the figure, 511 is a mask memory, 521 is an access control section, 531 is an address counter, and 541 is a mask area designation register.

Address data created by the address counter 531 and mask area data output from the mask area designation register 541 are supplied to the access control unit 521. The mask area data is data for specifying which part of the display screen is to be masked, that is, which part of the display data is not to be displayed, and the access control unit 521 determines whether the supplied address data is within the mask area. For example, if it is within the mask area, the bit data is “1”, and if it is outside the mask area, the bit data is “0”.
is supplied to the mask memory 511 for writing. A display device (not shown) uses this mask memory 511
The display data is read based on the stored data, and other display data is combined and displayed in the mask area.

[Problem to be solved by the invention]

Incidentally, displays in recent computers and the like have become higher in resolution due to faster processing speeds of central processing units (CPUs), larger capacities of semiconductor memories, and lower costs. Therefore, the number of display pixels tends to increase, and the capacity of the masking memory 511 also increases, resulting in the problem that it takes time to access the masking memory 511.

The present invention was created in view of these points, and an object of the present invention is to provide a mask memory access circuit that reduces access time.

It is configured to perform write processing.

[Means to solve the problem]

FIG. 1 is a principle block diagram of an access circuit for a mask memory according to the present invention.

In the figure, a mask memory 111 is divided into a plurality of regions, and each region stores mask data for instructing display or non-display of pixels.

The mask area storage means 121 stores coordinate data regarding display/non-display ranges of pixels.

Address generation means 131 outputs address data for accessing multiple areas of mask memory 111 simultaneously.

The writing determination means 141 determines whether each address data corresponding to a plurality of areas outputted from the address generation means 131 is included in the display/non-display range of pixels specified by the coordinate data outputted from the mask area storage means 12I. Determine whether or not it is possible.

Therefore, as a whole, the mask memory 111 is divided into a plurality of regions, and the mask data is applied in parallel to each region into which the mask memory 111 is divided.
Mask data for instructing display or non-display of pixels is stored in each area.

Address data output from the address generation means 131 is supplied to the mask memory 111 and the write determination means 141. This address data is stored in the mask memory 11.
The signal is simultaneously supplied to each divided area of 1, and addressing is performed.

Furthermore, the writing determination means 141 compares the address data outputted from the address generation means 131 with the coordinate data regarding the display/non-display range of pixels stored in the mask area storage means 121, and generates address data. Determine whether the part specified by is within or outside this range. This determination is performed in parallel for each divided area of the mask memory 111, and the results of this determination are supplied to each area. In each area of the mask memory 111, mask data is written based on the address data output from the address generation means 131 and each determination result by the write determination means 141.

In the present invention, the mask memory 111 is divided into a plurality of areas, and writing of mask data is determined for each area in parallel.
11 access time can be shortened.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the overall configuration of an embodiment to which the mask memory access circuit of the present invention is applied. Further, FIG. 3 shows a detailed configuration of one embodiment.

Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The mask memory 111 corresponds to the mask memory 2/1.

The mask area storage means 121 corresponds to the mask area designation register 221.

Address creation means 131 corresponds to address counter 231.

The write determination unit 141 includes an access determination control unit 241
corresponds to

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

■-1'' 11 old 1 base In FIG. 2, the computer system of the embodiment includes a processing device 271 that performs overall control regarding mask area designation and image composition, a mask memory 211 that stores mask data, and a mask memory 211 that stores mask data. An access determination control unit 241 that controls writing of mask data to the memo I 7211, an address counter 231 that creates address data for the mask memory 211, and a mask area designation register 221 that stores coordinate data regarding the mask area are introduced. It includes a mask synthesis section 251 that performs mask processing on image data such as a moving image or a still image, and an image synthesis section 261 that synthesizes other image data into a mask area of the image data that has been subjected to mask processing.

The processing device 271 outputs the X coordinates (left end and right end) and X coordinates (top end and bottom end) for specifying the mask area on the display screen. Each of these coordinate data is stored in the mask area designation register 221.

Next, the processing device 271 sends an instruction to the address counter 231, and the address counter 231 starts creating address data in response to this instruction.

This address data is supplied to the access determination control unit 241, and the access determination control unit 241 determines whether the position specified by this address data is within the mask area stored in the mask area designation register 221, Based on this determination result, the mask data in the mask memory 211 is rewritten.

The mask data and image data stored in the mask memory 211 are introduced into the mask synthesis unit 251, and outputs only image data other than the mask area. Therefore, image data in which only the mask area is masked is output.

The image synthesis section 261 also includes this mask synthesis section 251.
The image data output from the processing device 271 and the image data supplied from the processing device 271 are introduced.

The image synthesis section 261 synthesizes the image data output from the processing device 271 with the mask area of the image data output from the mask synthesis section 251 to obtain output image data. This output image data is displayed as a composite image by a display device (not shown).

Further, FIG. 3 shows a detailed configuration of the embodiment shown in FIG. 2.

The address counter 231 is an
It consists of a counter 233 and a Y counter 235 for generating the X coordinate.

The mask area designation register 221 includes X start position data indicating the start position of the X coordinate of the mask area, X end position data indicating the end position of the X coordinate, and Y start position data indicating the start position of the X coordinate. Y end position data indicating the end position of the X coordinate is included.

Furthermore, the mask memory 211 is divided into a plurality of areas. For example, if the number of divisions is "4", each area is divided into areas 1 and 2.
, 3.4. It is assumed that the entire mask memory 211 is divided into four parts by leaving the X coordinate corresponding to the horizontal coordinate of the display screen unchanged and dividing the X coordinate corresponding to the vertical coordinate of the display screen into four equal parts.

Furthermore, the access determination control unit 241 controls the mask memory 2
Data creation unit 281 that creates write data to 11
and a write determination unit 28 that determines writing of mask data to each area of the mask memory 211.
3, and a control signal (row address strobe (RAS) signal 8) necessary for writing data to the mask memory 211.
a control signal generator 285 that generates a column address strobe (CAS) signal, etc.) and four AND gates 291.2.
93, 295, and 297.

Now, the capacity of the mask memory 211 is set to 1024x102.
4 (bits), then the X coordinate of lO bit and 10
It is possible to access the desired mask data (1 bit) using the X coordinate of the bit (actually, the X coordinate is divided into four equal parts, so the X coordinate of each area can be specified using 8 bits). possible).

The 10-bit X coordinate address data output from the X counter 233 is supplied to each of the four divided areas of the data creation section 281 and the mask memory 211. Y
The 10-bit X-coordinate address data output from the counter 235 is supplied to the write determination section 283, and the lower 8 bits of this X-coordinate address data are supplied to each of the four divided areas of the mask memory 211.

Further, the X start position data and the X end position data in the mask area designation register 221 are supplied to the data creation section 281, and the Y start position data and the Y end position data are supplied to the write determination section 283. .

Further, the write data created by the data creation unit 281 is supplied to each divided area of the mask memory 211. Mask memory 211 by write determination unit 283
The determination result corresponding to each divided area is supplied to one end of each of the four AND gates 291 to 297, and the control signal output from the control signal generation section 285 is supplied to the other end of each of the AND gates. ANDGATE 291-29
Each output terminal of 7 is connected to each divided area of the mask memory 211 in one-to-one correspondence.

[[((Company) 1 work Next, the operation of the embodiment of the present invention described above will be explained.

FIG. 4 shows the operation procedure when accessing the mask memory 211 of the embodiment and changing stored data. In the figure, the mask memory 211 is 1024×1024
(bits), and by specifying the X coordinate (horizontal coordinate) and Y coordinate (vertical coordinate), it is possible to change the predetermined mask data.

Now, consider a case where only the bit data in the mask area surrounded by the coordinates (X, , Yl) and (**, Yt) in the mask memory 211 is changed to "1".

Hereinafter, reference will be made to FIGS. 2 to 4.

First, the X counter 233 and Y counter 235 in the address counter 231 sequentially count the coordinate values 0. For example, when creating coordinate values in units of horizontal lines, first, the coordinates (0° 0), (0 ,1),(0,2
), ..., (0°1023) are output. Similarly, sequential coordinates (1°0), (1,1), ..., (2
, O), (2°1), ... are output.

The X coordinate values output from the X counter 233 of the i-level data address counter 231 are sequentially supplied to the data creation section 281. The data creation unit 281 uses this supplied X coordinate value,
Write data is created based on the X start position data X and the X end position data Xl stored in the mask area designation register 221. When the X coordinate value output from the address counter 231 is included in the mask area, bit data "1" is created, and when it is not included, bit data "0" is created.

Since the X coordinates of points a1 and d shown in FIG.
'' is created.Furthermore, the data creation unit 281 creates bit data "1" corresponding to the opposite point and C3.

j The Y coordinate value output from the Y counter 235 of the bias address counter 231 has the lower 8 bits stored in the mask memory 211.
The data is supplied to each of the four areas 1, 2, 3.4, and the 10 bits are supplied as they are to the write determination unit 283. The write determination unit 283 uses this supplied Y
Write determination is made based on the coordinate values and the Y start position data Yl and Y end position data Yt stored in the mask area designation register 221.

Since the Y coordinate data supplied from the address counter 231 to the mask memory 211 is the lower 8 bits of lO bits, for example, when specifying point a, 4
Two points a In a 2+ a 3+ a a are specified. Therefore, in response to a single supply of the Y coordinate to the write determination unit 283, write determination is performed for these four points.

For example, when the address counter 231 outputs the coordinates of point a, the Y coordinate of point a is not included in the Y coordinate range Y, -Y of the mask area, so the writing determination unit 283
supplies a logic "O" signal to the AND gate 291 corresponding to region 1. Also, point a ** a 2+ a 4
Each Y coordinate of is included in the Y coordinate range of the mask area, so
The write determination section 283 supplies a logic "1" signal (enable signal) to the AND gates 293 to 295 corresponding to each of the areas 2.3.4. A writing determination is performed by the determination unit 283.

Table 1 shows how the data creation section 281 creates write data and the write determination section 283 performs write determination, focusing on points a, b, c, and d.

Table 1 In Table 1, the “determination result” is written by the writing determination unit 283.
This shows the write judgment result by ``L'' of this judgment result is a logic ``0'' output signal, and rH is a logic ``1'' output signal.
They correspond to the respective enable signals.

iii At the other end of each of the master thresholds and gates 291 to 297,
A control signal is supplied from the control signal generating section 285, and this control signal has a logic of "I II
(when it is an enable signal), the AND gate 291
~297 is output.

In each corresponding area of the mask memory 211, the write data outputted from the data creation section 281 is written into the coordinate value outputted from the address counter 231 in response to the supply of this control signal.

Therefore, in Table 1, if the write data is "l",
And when the determination result is “H”, the mask memory 211
The bit data at the corresponding position is changed to “III”.

Incidentally, since the above-described operations for the four areas are performed in parallel, the operation of creating coordinate values by the address counter 231 is performed only for one of the areas (for example, area 1).

(2) Conclusion As shown above, the mask memory 211 is divided into four areas, and mask data is written to each of these areas in parallel.

In the data creation unit 281, the X coordinate is
Write data "1" or "O"' is created depending on whether or not it is included in the coordinate range X1 to "X". In addition, in the write determination unit 283, the corresponding 4
Each X coordinate of the point is the Y coordinate range of the mask area Y1 to Y! An enable signal is created when the mask is included in the mask memory 211, and in response to the creation of the enable signal, a control signal output from the control signal generator 285 is supplied to a corresponding area of the mask memory 211.

In the corresponding area of the mask memory 211, write data created by the data creation section 281 is stored in response to the supply of this control signal.

Therefore, by performing write determination of mask data in parallel in each divided area of the mask memory 211, it is possible to shorten the access time of the mask memory 211.

(2) In the embodiment of the present invention described above, the case where the mask memory 211 is divided into four in the X direction is considered, but the same can be considered in the case where the mask memory 211 is divided in the X direction.

Furthermore, in the embodiment, the supply of the control signal is limited by making a write determination on the 0 For example,
The logical product of the output of the data creation section 281 and the output of the write determination section 283 is used as write data, and the control signal generation section 2
This write data is stored in the mask memory 211 in accordance with the control signal output from the mask memory 85.

Furthermore, in ``correspondence between examples and FIG. 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, the access time of the mask memory can be shortened by dividing the mask memory into a plurality of areas and determining whether to write mask data in each area in parallel. This is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a mask memory access circuit of the present invention, FIG. 2 is an overall configuration diagram of an embodiment to which the mask memory access circuit of the present invention is applied, and FIG. 3 is a block diagram of an embodiment of the mask memory access circuit of the present invention. A detailed configuration diagram, FIG. 4 is an explanatory diagram of the operation of one embodiment, and FIG. 5 is an explanatory diagram of a conventional example. 131 is an address generation means, 141 is a write determination means, 211 is a mask memory, 221 is a mask area specification register, 231 is an address counter, 233 is an X counter, 235 is an X counter, 241 is an access determination control unit, 251 is a mask 261 is an image compositing unit, 271 is a processing device, 281 is a data creation unit 283 is a writing determination unit, 285 is a control signal generation unit, 291, 293, 295°. 297 is an AND gate diagram, 111 is a mask memory, 121 is a mask area storage means, Principles of Non-Invention 7'77 Figure 1 Actual '1<7) h45ti 1311 rfJ 4rA Conventional I Column configuration diagram Figure 5

Claims (1)

[Claims] (1) A mask memory (111) that is divided into a plurality of areas and stores mask data for instructing display/non-display of pixels in each area, and coordinate data regarding the display/non-display range of the pixels. a mask area storage means (121) for storing data, and an address generation means (131) for outputting address data for simultaneously accessing multiple areas of the mask memory (111).
), each of the address data corresponding to the plurality of areas outputted from the address generation means (131) displays or hides a pixel specified by the coordinate data outputted from the mask area storage means (121). write determination means (141) for determining whether or not the area falls within the range of , and is configured to perform write processing of mask data in parallel to each area into which the mask memory (111) is divided. A mask memory access circuit characterized by: