JP2908322B2 - CPU system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CPU system, and more particularly to a CPU system for transmitting data by itself and checking a data bus connecting the systems.

[0002]

2. Description of the Related Art Conventionally, as this type of apparatus or system, as disclosed in Japanese Patent Application Laid-Open No. 2-133848, for example, a plurality of data transfer sections and data reception sections, these data transfer sections and data reception sections are disclosed. There is a system in which a service processor for diagnosing is connected by a common data bus and a maintenance bus, and performs data transfer to a lower device in accordance with an instruction from a higher device. FIG. 8 is a block diagram of such a conventional system. The data transfer units 50, 51, the data reception units 52, 53, and the service processor 54 are connected to a data bus 65 and a maintenance bus 66, and are respectively stored in storage means (memory, etc.) 55, 57, 58, 59, 60.
And indicating means 56, 61, 62, 63, 64.

The service processor 54, the data transfer units 50 and 51, and the data reception units 52 and 53
The inspection data is circulated to detect a fault location on the data bus. That is, the test data is transmitted from the service processor 54 to the data transfer unit 50 using the data bus 65.
From the data transfer unit 50 to the data transfer unit 51, from the data transfer unit 51 to the data reception unit 52, from the data reception unit 52 to the data reception unit 53, and from the data reception unit 53 to the service processor 54, the inspection data is sequentially transmitted. Is transferred, and if the same data as the test data sent out first by the service processor 54 returns, the data bus 65 is determined to be normal. If the returned data does not match the transmitted inspection data, it is considered that the data bus is abnormal. Therefore, the maintenance bus 66 is used between the service processor 54 and each of the data transfer / reception units 50 to 53. Then, the inspection data is checked and the location where the data bus becomes abnormal is grasped.

[0004]

SUMMARY OF THE INVENTION As described above, the conventional C
In the PU system, the data bus is checked by using the test data to find an idle time when the data bus is not used in the system, so the test data needs to be specially prepared. In addition, it is necessary to perform a special operation only for checking the data bus. Further, the maintenance bus is used in place of the data bus. However, if an abnormality occurs in the data bus during the operation of the system, there is a problem that there is no remedy.

The present invention has been made to solve such a problem, and there is no need to prepare special inspection data in the system or to perform a special operation for checking. It is an object of the present invention to provide a CPU system which can always check the data bus during operation and can continue the operation of the data bus without affecting the operation of the system even if an abnormality occurs in the data bus.

[0006]

In the CPU system according to the present invention, a CPU section, a memory section, and a collating section are connected on a data bus, and the collating section stores program data and other data used in the system. A memory in which the same data as the stored memory of the memory unit is stored; and a collation circuit, and the collation unit uses an address output from a CPU unit via an address bus to read data from the memory unit. The same data is read from the memory, and the data from the memory unit sent via the data bus is compared with the data read from the memory of the matching unit by the matching circuit to check the normality of the data bus. It is characterized by having means for determining.

Further, the CPU unit, the memory unit, and the collating unit are connected to a plurality of data buses via respective data bus selecting circuits, and abnormality is found in the data bus used in the collating circuit. In this case, a means for operating the respective data bus selection circuits in the matching circuit and simultaneously switching the data bus to be used is provided.

[0008] Further, it has a CPU having a CPU and a RAM used as a local memory thereof, and a memory for storing program data for starting the CPU, and writes the program data stored in the memory to the RAM. In a CPU system in which the system operates,
A CPU unit 10 having a CPU 11, a RAM 12, and a data bus selection circuit 13, a memory unit 20 having a memory 21 storing program data 6 for operating the system, and a data bus selection circuit 23; A memory 31 having contents, a matching circuit 30 having a matching circuit 32 and a data bus selecting circuit 33 are connected to a plurality of data buses A (1) and B (1) via data bus selecting circuits 13, 23 and 33, respectively. When the CPU 11 of the CPU unit 10 reads the contents of the memory 21 of the memory unit 20, the system uses the same address as the read contents sent to the data bus. The content of the memory 31 of the collation unit 30 to be read is collated by the collation circuit 32 to determine the normality of the data bus used. To.

When an abnormality is detected in the data bus used in the collation of the collation circuit 32, the collation circuit 3
2 outputs a bus switching signal 41 and operates the data bus selection circuits 13, 23, and 33 to switch the data bus to be used, so that the CPU section 10 and the memory section 2 are switched.
0, characterized by maintaining bus access between the matching units 30.

Further, a bus switching signal 41 output from the collating circuit 32 is a signal for designating one of the used data buses in which an abnormality is detected in units of one, and the data bus selecting circuits 13 and 23 are used. , And 33, respectively, to which switching bus selection control ports 14, 24, and 34 are added, and data bus switching is performed in units of one bus.

The CPU system of the present invention has the above-described configuration, so that when the CPU 11 (system) of the CPU section 10 starts up, the program data 6 on the data bus A (1) or B (2) is The collation unit 30 can collate the data 7 designated at the same address with the collation unit 30. Therefore, if the collation does not match and an error occurs, the currently accessed bus cycle is not terminated as in the past, but is currently used. Outputs a bus switching signal to switch the data bus, switches the data bus to be used, terminates the currently accessed bus access normally, and continues the subsequent bus access to enable the system to start and operate normally Becomes

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a CPU system according to an embodiment of the present invention. As shown in FIG. 1, a CPU system according to the present invention includes a CPU unit 10 having a CPU and a RAM used as a local memory thereof, It comprises a memory unit 20 for storing program data for activation and a collating unit 30 for collating program data. Hereinafter, each unit will be described. Reference numeral 10 denotes a CPU unit. The CPU unit 10 includes a CPU 11, a RAM 12 used as a local memory thereof, and a data bus C (3) in the CPU unit 10 connected to an external data bus A (1) or a data bus B (2). ) Data bus selection circuit 1
3 is comprised. Reference numeral 20 denotes a memory unit. The memory unit 20 includes a memory 21 in which program data 6 for activating the CPU 11 is stored, and an external data bus A (1) via the internal data bus D (4). Alternatively, it is constituted by a data bus selection circuit 23 connected to one of the data buses B (2).

Reference numeral 30 denotes a collating unit. The collating unit 30 includes a memory 31 for storing the same program data 7 as the program data 6 and an external data bus A (1) or data bus B.
A data bus selection signal is transmitted to the respective data bus selection circuits 13, 23, 33 via a bus switching signal 41 and a data bus selection circuit 33 for connecting any of (2) to the internal data bus E (5). At the same time, the matching is performed by the control signal 40 from the CPU 11 (that is, the program data transmitted by either the data bus A (1) or the data bus B (2) selected by the data bus selection circuits 13, 23, 33). 6 and a matching circuit 32 for matching the program data 7 from the memory 31). Although not shown in FIG. 1, each data bus A (1), B (2), C
(3), D (4) and E (5) usually have a bus width of 7 to 8 buses respectively.

Next, the operation will be described with reference to FIGS. FIG. 2 shows that the CPU 11
FIG. 3 is a diagram showing a data flow at the time of starting using the program data 6 in FIG. 3, and FIG. 3 is a diagram showing a data flow after switching the data bus A (1) to the data bus B (2) and restarting the CPU 11 starting operation It is. CPU 11 of CPU unit 10
However, when reading the contents of the memory 21 of the memory unit 20, the CPU 11 reads the program data 6 from the memory 21 using the data bus A (1), and reads the contents into the RA.
Write to M12. At the same time, the address of the memory 31 is designated by the CPU 11 and the program data 7 having the same content as the program data 6 of the memory 21 is output to the collating circuit 32. Data bus A input through
(1) It is compared with the above program data 6. Collation unit 30
Determines that the data bus A (1) is normal if the collation in the collation circuit 32 matches, and determines that an abnormality has occurred if the collation does not match.

When an error (mismatch) occurs in the collation of the collation circuit 32, the collation circuit 32 first switches the data bus used in the system to the data bus B (2), and outputs a bus switching signal 41 to each data bus. Selection circuits 13, 2
3, 33, and each data bus selection circuit 13, 23,
Reference numeral 33 designates a data bus to be used simultaneously from A (1) to B (2).
Switch to Then, when the data bus used in the system is switched, the program data is read in the flow as shown in FIG. FIG. 7 is a flowchart showing the above operation.

The switching timing of the data bus will be described with reference to the timing chart of FIG. CP
U11 is the address AD3 and the memory unit 20 and the matching unit 3
0, the collation circuit 32 detects an abnormality in one of the data buses A (1) A0 at time T1, and the collation circuit 32 outputs the data before the end of the bus access of the address AD3. A bus switching signal 41 is transmitted to each of the data bus selection circuits 13, 23, 33. At the next time T2, each of the data bus selection circuits 13, 23, and 33 completes the switching of the data bus, and the CPU 11 uses the data bus B (2) to send the address AD3 to the memory unit 20 and the comparison unit 30. Continue access. In this way, after the switching of the data bus A (1) including the data bus A0 detected as abnormal is completed, the bus access ends normally.
In this way, even if a data collation error occurs in the collation unit 30, the data bus A (1) including the data bus A0 detected as abnormal as described above is substituted for the data bus B (2),
The PU activation operation can be performed normally.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment, when an abnormality occurs in the data bus, the switching operation is performed for each data bus A (1) having a width of 7 to 8 lines. Ports 14, 24, 3
4, the data bus is switched one by one. Hereinafter, the operation of the second embodiment will be described with reference to FIGS. The CPU unit 10
In addition to the CPU 11 and the RAM 12, a bus switching signal 41 which is converted into a code (coded) and transmitted through three (F0, F1, F2) buses
, A switching bus selection control port 14 for switching the data bus A (1) in units of A0 to A7, and a switching signal which is decoded and output from the switching bus selection control port 14 and specifies one bus to be switched 15, the bidirectional bus selection buffers 130 to 137 for connecting any one of the data buses A0 to A7 and the data buses B0 to B7.
And a data bus selection circuit 13 composed of

The memory unit 20 includes a memory 21, a switching bus selection control port 24 that performs the same operation as the switching bus selection control port 14, and a bidirectional bus selection buffer 130 to 137. And a data bus selection circuit 23 comprising bidirectional bus selection buffers 230 to 237 for operation. The collating unit 30
Performs the same operations as those of the memory 21, the matching circuit 32, the switching bus selection control port 34 performing the same operation as the above-described switching bus selection control port 14, and the bidirectional bus selection buffers 130 to 137 described above. Data bus selection circuit 3 comprising bidirectional bus selection buffers 330 to 337
The CPU unit 10, the memory unit 20, and the collation unit 30 are connected by a data bus A (1), a data bus B (1), and a bus switching signal 41, respectively.

Each of the eight switching signals 15 output from the switching bus selection control port 14 is represented by X0, X1,... X7, and similarly, each of the switching signals 25 is represented by Y0, Y1,.・ Y7
Similarly, let the signals of the switching signal 35 be Z1, Z2,... Z7. In each of the data bus selection circuits 13, 23, 33, the signal
When X0 to X7, Y0 to Y7, and Z0 to Z7 are at the H level (logic = 1), the data bus A (1) is selected and the L level (logic = 0) is selected.
, Inverters 160 to 167, 260 to 267,
The data bus B (2) is selected by 360 to 367.

When the CPU 11 is started, the bus selection buffers 130 to 137 of the CPU 10 connect the data bus A0 and the data bus C0, the data bus A1 and the data bus C1... The data bus A7 and the data bus C7, respectively. The bus selection buffers 230 to 237 include a data bus A0 and a data bus D0, a data bus A1 and a data bus D1, respectively.
A7 is connected to the data bus D7, and the bus selection buffers 330 to 337 of the collating unit 30 connect the data bus A0 to the data bus E0, the data bus A1 to the data bus E1,. I have.

When the collation circuit 32 of the collation unit 30 detects, for example, an abnormality in the data bus A0, the collation circuit 3
2 transmits the bus switching signal 41 to each of the data bus selection circuits 13 and 2
3 and 33. Here, for example, in order to perform an operation of switching only the data bus A0 of the data bus A (1) to the data bus B0, three buses (F0, F1, F2) are used. For example, one of the eight signals is specified and transmitted as the coded 3-bit binary signal [0, 0, 0] in the switching signal 41.

The switching bus selection control ports 14 in the data bus selection circuit 13 receiving the bus switching signal 41
Recognize that the bus to be switched by decoding the signal of (F0, F1, F2) is the data bus A0, and transmit the signal of, for example, X0 = 0 only to the bus selection buffer 130 that switches between the data bus A0 and the data bus B0. Data bus C0 and data bus B0
Connect to The same operation is performed in the memory unit 20, and the signal of Y0 = 0 is transmitted only to the bus selection buffer 230, the data bus D0 is connected to the data bus B0, and the program data output to the data bus A (1) is output. No. 6, only the data bus A0 is switched to the data bus B0 and output.

Similarly, the collating unit 30 similarly transmits a signal of Z0 = 0 only to the bus selection buffer 330, connects the data bus E0 to the data bus B0, and connects the data bus A0 other than the data bus A0.
The program data 6 is sent from (1) and the data bus B0 to the matching circuit 32 through the data bus selecting circuit 33, and is compared with the program data 7 sent from the memory unit 31 by the matching circuit 32. In this manner, one of the buses used in the system is switched from the data bus A0 to the data bus B0, and the data bus in which no abnormality is detected is used as it is. Note that when two or more data buses fail simultaneously in a certain bus cycle when the CPU 11 is started, the collation circuit 32 first switches one data bus, and then detects failures one by one in order. In order to switch the data bus, a bus switching signal 41 is sent out, and after all the buses in which an abnormality has been detected have been switched, the bus cycle ends normally.

In the first and second embodiments described above, the case where the data bus is checked by the collating unit using the program data at the time of starting the system is mainly described. It goes without saying that the data bus transmitted from the memory unit 20 to the data bus and the same data 7 output from the memory 31 via the same address bus are collated by the collation circuit 32 to check the data bus. In the above-described second embodiment, the case where the bus width of each of the data buses A (1) and B (1) is eight is described. However, since these bus widths differ depending on the system, In accordance with the bus width, the number of identification codes (codes) of the bus switching signal 41 output from the matching circuit 32 and each switching bus selection control port 1
Switching signals 15, 25, 3 output from 4, 24, 34
The number 5 may be adjusted. Further, in the first and second embodiments, the bus to be selected is the data bus A (1).
And the data bus B (2) are shown. However, if the number of data buses to be selected is increased, the selectable range of buses that can be switched is widened and the reliability of the system can be improved accordingly.

[0025]

As described above, in the CPU system of the present invention, when the system is started, only the CPU checks the data bus in the collating unit using the program data read from the memory unit, and the data bus in the system operation is operated. Since the checking is performed by using the data sent from the memory unit to the data bus in the collating unit, the data bus can be checked without affecting the operation of the system at all. Also, the system is provided with a plurality of data buses in parallel, and when an error occurs in the data bus being used, the data bus selection circuit is operated in units of the data bus width or in units of one bus to switch. Even if an abnormality occurs in the data bus, it is not necessary to stop part or all of the system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a CPU system according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the first embodiment.

FIG. 3 is a diagram for explaining the operation of the first embodiment.

FIG. 4 is a time chart for explaining the operation of the first embodiment.

FIG. 5 is a diagram for explaining the operation of the second embodiment.

FIG. 6 is a diagram for explaining the operation of the second embodiment.

FIG. 7 is a flowchart illustrating the operation of the first and second embodiments.

FIG. 8 is a diagram showing a conventional CPU system of this type.

[Explanation of symbols]

1 Data bus A (comprising data buses A0 to A7) 2 Data bus B (comprising data buses B0 to B7) 3 Data bus C 4 Data bus D 5 Data bus E 6,7 Program data 10 CPU section 11 CPU 12 RAM 13, 23, 33 Data bus selection circuit 14, 24, 34 Switching bus selection control port 15, 25, 35 Switching signal 20 Memory unit 30 Collation unit 32 Collation circuit 21, 31 Memory 40 Control signal 41 Bus switching signal 130 to 137, 230 to 237, 330 to 337 Bus selection buffer 160 to 167, 260 to 267, 360 to 367 Inverter

Claims (4)

(57) [Claims] (1)Each is duplicated via the data bus selection circuit.
Number ofThe CPU, the memory, and the matching unit are connected on the data bus.
The collation unit is connected to a program used in the system.
The memory of the memory unit in which data and other data are stored
The memory that stores the same data asHave  An address bus for reading data from the memory unit;
Using the address output from the CPU unit via the
Read the same data from the memory of the
Data sent from the memory unit via the
And comparing the data read from the memory in the
Means for determining the normality of the data bus by collating withAn error was detected in the data bus used by the above means
In the case, each data bus selection circuit is
A method for simultaneously switching the data bus to be operated and used
Dan,  A CPU system comprising: (2)Used as CPU and its local memory
CPU with RAM to run
It has a memory unit for storing
Writes stored program data to the RAM
In a CPU system in which the system operates, CPU 11, RAM 12, and data bus selection circuit 13
CPU 10 and program for operating the system
21 for storing data 6 and data bus selection circuit
23, and the same as the memory unit 20.
Memory 31 having the same contents, matching circuit 32 and data bus
The matching unit 30 having the selection circuit 33
A plurality of data via the tabus selection circuits 13, 23, 33
The system is connected to buses A (1), B (1),.
And The CPU 11 of the CPU unit 10 is connected to the memory 21 of the memory unit 20.
When reading the contents of
Read using the same address as the read content
The contents of the memory 31 of the matching unit 30 are compared with the matching circuit 3
Check the normality of the used data bus by checking in step 2.
2. The CPU system according to claim 1, wherein
M 3. The method according to claim 1, wherein said matching circuit is used for matching.
When an abnormality of the data bus is detected, the matching circuit 32
A bus switching signal 41 is output and the data bus selection circuit 1
3, 23, 33 to turn off the data bus to be used.
By switching, CPU unit 10, memory unit 20,
Maintaining bus access between the junctions 30
The CPU system according to claim 1. 4. A bus switching signal output by the matching circuit 32.
No. 41 detects an abnormality in the used data bus.
The data bus is a signal that specifies one bus at a time.
Switch selection system for each of the switch selection circuits 13, 23, 33
Control ports 14, 24, and 34 to disconnect the data bus
2. The configuration according to claim 1, wherein the replacement is performed on a bus basis.
Item 4. The CPU system according to any one of Items 3 or 3.