JPH07146802A - Railroad safety system - Google Patents

Abstract

PURPOSE:To respond to the making of a CPU into speedup and multiple function by employing duplex redundant constitution for hardware such as the CPU, etc., comparing data on buses connected to two CPUs respectively with a period near to a processing period by a comparator, and confirming the operation of the CPU. CONSTITUTION:An interruption control circuit 6 generates an interruption signal at every period set as the reference of the processing period set in advance, and sends it to an A system CPU 1, a B system CPU 2, and the oscillator 55 of the comparator 5. When the oscillator 55 receives the interruption signal, the A system CPU 1 and the B system CPU 2 output comparative collation data, and output a comparison command to a data comparison circuit 54 being delayed by a prescribed time decided in advance corresponding to a time until it is held by a latch circuit 51 for positive logic output and a latch circuit 52 for negative logic output as comparison data. The data comparison circuit 54, when receiving the comparison command, reads in the comparison data of positive logic inverted via an inverter 53 from the latch circuit 52 for negative logic output, and compares them bit by bit. An abnormality signal is outputted when even difference of one bit exists.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a railway security device using microelectronics technology, and more particularly to improvement of high safety and high reliability of the device.

[0002]

2. Description of the Related Art In signal security devices such as interlocking devices and blocking devices that have introduced microelectronic technology,
A bus-synchronous dual system comparison is being carried out in order to realize a fail-safe by ensuring the high safety and high reliability of the microcomputer. In the conventional bus-synchronous dual system comparison, two sets of CPUs are operated synchronously, and data such as programs and processing data transferred on two sets of buses for memory access and external input / output are used as machine data. The comparison circuit compares each cycle. When the two sets of data match, the comparison result output is changed to output an alternating signal. When the two sets of data do not match, the comparison result By fixing the output, a DC signal is output and the control signal is fixed on the safe side.

When the bus-synchronous duplex system comparison is performed in this manner, the failure of each component such as the CPU and the memory is reflected on the bus without fail, so that the failure can be surely detected. Further, since the data on the bus is compared and collated for each machine cycle, there is an advantage that the comparison and collation frequency can be increased and a single fault can be quickly detected before a double fault occurs.

[0004]

The progress of CPU is remarkable, and the processing speed and operation timing of each CPU are different due to the increase of data bit length, the increase of speed, the change of architecture and the like. In this way, when the CPU speeds up and the processing speeds and operation timings of the individual CPUs differ, the data read and written by the two sets of CPUs are compared and collated for each machine cycle which is one processing cycle as described above. ,
It becomes impossible for the comparator to absorb the difference in processing speed and operation timing of each CPU. For this reason 2
It is necessary to design and manufacture by combining a set of CPUs and comparators.

On the other hand, since the functions processed by the CPU are also increasing due to the man-machine interface such as operation and maintenance and high performance, a higher speed CPU is required. However, if the CPU and the comparator are combined and designed and manufactured as described above, the comparator also needs to be replaced in correspondence with the CPU when trying to replace it with a higher speed CPU, and it is easily replaced with a high speed CPU. Therefore, it becomes impossible to meet the demand for higher processing speed.

The present invention has been made in order to solve the above disadvantages, and provides a railway security device which can be quickly replaced with a CPU having higher speed and higher performance to quickly meet the demand for higher processing speed. The purpose is to obtain.

[0007]

A railway security system according to the present invention compares two sets of CPUs that operate in synchronization with each other and two sets of data that are connected to a bus line connected to each CPU and an output circuit. In a railway security device having a comparator for comparing and detecting a failure, the comparator has two sets of latch circuits, a data comparison circuit and an oscillator, and the two sets of latch circuits are respectively connected to different bus lines. , The comparison data for every fixed period is held, and the data comparison circuit fetches the data held in the two sets of latch circuits for comparison and verification, and when the two sets of data do not match. A signal that fixes the control output to the safe side is sent to the output circuit, and the oscillator outputs a comparison command to the data comparison circuit in synchronization with the interrupt signal at regular intervals and a latch clear command to each latch circuit. It is characterized by

[0008]

Since the CPU has a high degree of integration and can be operated by software, it is difficult to guarantee the operation with one CPU. Therefore, in the present invention, in order to confirm the operation of the CPU, the hardware such as the CPU has a dual redundant configuration, and the data on the bus connected to each of the two CPUs by the comparator is set as the processing cycle. It is checked whether or not the CPU is operating normally by making comparisons at close intervals. When the comparator compares the data on each bus, the data input / output to / from each CPU
The data is stored in the latch circuit at preset constant intervals, the stored data is compared, and the result of comparison and collation is C
It is possible to prevent the processing speed and operation timing of the PU from being affected.

As described above, assuming that the two sets of CPUs do not become abnormal at the same time, it is easy to configure the outputs of the two sets of CPUs in a hard circuit by a logic circuit so as to provide a fail-safe. Using a simple comparator,
It realizes the CPU fail-safe.

[0010]

1 is a block diagram showing the configuration of an embodiment of the present invention. As shown in the figure, the railroad signal security device that has been made into a microelectronic is a system A CP that operates synchronously.
U1 and B system CPU2, buses 11 and 21 connected to the A system CPU1 and B system CPU2, respectively, for transferring programs and processing data each time memory access or external input / output,
It has a memory 12 connected to each bus 11, a memory 22 connected to the bus 21, an input circuit 3 and an output circuit 4 connected to each of the buses 11 and 21, a comparator 5 and an interrupt control circuit 6. .

The A system CPU 1 and the B system CPU 2 respectively judge the contents of the input data input from the input circuit 3 and manage the output data output from the output circuit 4. Memory 1
Reference numerals 2 and 22 have a ROM and a RAM, which store various processing programs and various data. Comparator 5
Is to determine whether the operating states of the A system CPU 1 and the B system CPU 2 are appropriate by comparing and collating the data input to and output from the A system CPU 1 and the B system CPU 2, and the positive logic output latch circuit 51.
And latch circuit 52 for negative logic output, inverter 53, data
It has a comparator circuit 54 and an oscillator 55.

The positive logic output latch circuit 51 is connected to the bus 11 and compares positive logic data out of positive logic data and negative logic data output from the A system CPU 1 at regular intervals. Hold as data. Latch circuit 52 for negative logic output
Is connected to the bus 12 and holds the negative logic data out of the positive logic data and the negative logic data output from the B-system CPU 2 as comparison data at regular intervals. Inverter 53
Inverts the negative logic comparison data output from the negative logic output latch circuit 52. The data comparison circuit 54 fetches the comparison data held in the positive logic output latch circuit 51 and the comparison data held in the negative logic output latch circuit 52, compares and collates them, and sets two sets of data. Sends a signal for fixing the control output to the safe side to the output circuit 4 when they do not match. The oscillator 55 outputs a comparison command to the data comparison circuit 54 in synchronization with the interrupt signal output from the interrupt control circuit 6, and a latch clear command to the positive logic output latch circuit 51 and the negative logic output latch circuit 5. Is output. The interrupt control circuit 6 sends an interrupt signal to the A-system CPU 1 and the B-system CPU 2 and the oscillator 55 at every constant cycle which is a reference of a preset processing cycle.

An operation for realizing high safety and high reliability with the railway signal security device configured as described above will be described.

The interrupt control circuit 6 generates an interrupt signal for each interrupt cycle serving as a reference of a preset processing cycle and sends it to the A system CPU 1 and the B system CPU 2 and the oscillator 55.
Whenever an interrupt signal is sent, the A system CPU 1 and the B system CPU 2, for example, use the data input / output from the input circuit 3 and the output circuit 4 as comparison and collation data on the buses 11 and 12.
Output to. For example, if the data input / output from the input circuit 3 and the output circuit 4 has a 16-bit length, this A / C CPU 1 and the B system CPU 2 input / output from the input circuit 3 and the output circuit 4, respectively. These data are sequentially added from the beginning of the interrupt processing, the added sum is calculated at the end of the interrupt processing, and the lower 16 bits of the calculated total are output as comparison and collation data. This A system CPU1 and B system CPU
The comparison and collation data output by 2 includes positive logic data and negative logic data.

When the comparison / collation data is sent from the A system CPU 1, the positive logic output latch circuit 51 of the comparator 5 holds only the positive logic data as the comparison data. Further, the negative logic output latch circuit 52 receives the comparison and collation data from the B system CPU 2.
When the data is sent, only negative logic data is held as comparison data. In other words, since it is difficult to check the internal operation of the CPU in detail, it is necessary to invert the comparison data of two sets of CPUs that perform the same operation by inverting only one system and output the control output externally for comparison. I have to.

On the other hand, when the oscillator 55 of the comparator 5 receives the interrupt signal, the A system CPU 1 and the B system CPU 2 output the comparison and collation data, and the positive logic output latch circuit 51 and the negative logic output latch circuit 52. The data is delayed by a predetermined time set in advance according to the time until the comparison data is held.
A comparison command is output to the data comparison circuit 54. When the data comparison circuit 54 receives the comparison command, the positive logic output latch circuit 5
The positive logic comparison data is read from 1, and the inverted positive logic comparison data is read from the negative logic output latch circuit 52 via the inverter 53. After that, the data comparison circuit 54 compares the read two sets of data bit by bit. As a result of comparing the two sets of data, when the respective bits are the same, an alternating signal is output, and the A system CPU 1 and the B system CPU 2
The signal indicating that the operation is normal is output to the output circuit 4. If even one bit is different among the two sets of data, the output of the alternating signal is stopped, and the stopped state is fixed thereafter to indicate that the operations of the A system CPU 1 and the B system CPU 2 are abnormal. Is output to the output circuit 4. The output circuit 4 sends a signal indicating the comparison result from the data comparison circuit 54 to an alarm device (not shown). When a signal indicating the comparison result is sent, the alarm device rectifies the signal and controls the final output relay, and the final output relay outputs the A system CPU1.
And whether or not the operation of the B system CPU 2 is normal or abnormal.

After the oscillator 55 outputs a comparison command to the data comparison circuit 54, the data comparison circuit 54 outputs comparison data from the positive logic output latch circuit 51 and the negative logic output latch circuit 52. When a predetermined time determined according to the reading time has elapsed, a latch clear command is sent to the positive logic output latch circuit 51 and the negative logic output latch circuit 52. Upon receipt of the latch clear command, the positive logic output latch circuit 51 and the negative logic output latch circuit 52 clear the held comparison data and compare and collate data from the A system CPU 1 and the B system CPU 2 in the next interrupt cycle. Wait for the data to be output.

As described above, the comparison and collation data is sent from the A system CPU 1 and the B system CPU 2 at each predetermined interrupt cycle.
Since the comparison and collation data is compared by the comparator 5 at every interrupt cycle, it is possible that the processing speed and operation timing of the A system CPU 1 and the B system CPU 2 influence the result of the comparison and collation. Can be prevented. Therefore, A system CP
The U1 and B system CPU 2 can be easily changed to CPUs having arbitrary processing speeds and operation timings.

Further, since the interrupt period and the timing of the comparison command and the latch clear command are not affected by the processing speed and operation timing of the A system CPU 1 and the B system CPU 2, they can be arbitrarily changed according to programming, and the processing can be changed. Can be optimized.

In the above embodiment, the case where the data input / output from the input circuit 3 and the output circuit 4 is used as the comparison and collation data has been described. However, the data is read from the memories 12 and 22 or the data stored in the memories 12 and 22. By comparing the data to be written, it is possible to confirm whether the memories 12 and 22 are normal or abnormal.

In the above embodiment, the case where the sum of the data input and output from the input circuit 3 and the output circuit 4 is used as the comparison and collation data has been described.
C) or the like may be used.

[0022]

As described above, the present invention provides a CPU.
Hardware such as a dual system with a redundant configuration and a comparator
The data on the buses respectively connected to the CPUs in the group are compared at a cycle close to the processing cycle to check whether the CPUs are operating normally.
It is possible to prevent the processing speed and operation timing of the PU from being affected. Therefore, it is possible to easily change the CPU to be used to a CPU having an arbitrary processing speed and operation timing, and it is possible to quickly adapt to the increase in speed and multifunction of the CPU.

Further, since the processing of the comparator is not affected by the processing speed and operation timing of the CPU, the processing timing of the comparator can be arbitrarily changed in accordance with programming, and the processing can be optimized. .

Furthermore, since the same comparator can be used even if the CPU is changed, it is possible to reduce new circuit design and development costs.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

[Explanation of symbols]

 1 A system CPU 2 B system CPU 3 Input circuit 4 Output circuit 5 Comparator 6 Interrupt control circuit 11,21 Bus 12,22 Memory 51 Positive logic output latch circuit 52 Negative logic output latch circuit 53 Inverter 54 Data Comparator circuit 54 oscillator

Claims (1)

[Claims] 1. Two sets of CPUs operating in synchronization and each CPU
In a railroad safety device having a bus line connected to the output circuit and a comparator connected to the output circuit for comparing and collating two sets of data to detect a failure, the comparator is a set of two latch circuits and a data comparison unit. The latch circuit has a circuit and an oscillator, and two sets of latch circuits are connected to different bus lines, respectively, and hold comparison data for every fixed period. The data comparison circuit holds data held by the two sets of latch circuits. -The data is fetched, compared and collated, and when the two sets of data do not match, a signal that fixes the control output to the safe side is sent to the output circuit, and the oscillator synchronizes with the interrupt signal at regular intervals. -A railway safety device characterized in that it outputs a comparison command to the data comparison circuit and outputs a latch clear command to each latch circuit.