JP2907767B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a built-in capacitive element using a dielectric film having a high dielectric constant or a ferroelectric film as a capacitive insulating film.

[0002]

2. Description of the Related Art In recent years, the speed of microcomputers and the like has been increased,
With the trend toward lower power consumption, consumer electronic devices have become more sophisticated, and semiconductor devices used have been rapidly miniaturized. As a result, unnecessary radiation, which is electromagnetic wave noise generated from electronic devices, has become a major problem. As a measure to reduce this unnecessary radiation, a dielectric having a high dielectric constant (hereinafter simply referred to as a high dielectric) is used as a capacitive insulating film. Attention has been paid to a technology for incorporating a large-capacity capacitive element in a semiconductor integrated circuit device or the like. Also, dynamic RAM
With the increase in integration of semiconductor devices, techniques for using a high dielectric as a capacitor insulating film instead of the conventional silicon oxide or nitride have been widely studied. Further, research and development on ferroelectric films having spontaneous polarization characteristics have been actively pursued with the aim of putting a non-volatile RAM capable of high-speed writing and reading at a low operating voltage unprecedented.

Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to the drawings. FIG. 4 (a) to (d)
3A and 3B are a process cross-sectional view and a process flowchart in a conventional semiconductor device manufacturing process.

First, as shown in FIG. 4A, an isolation oxide film 2, a diffusion region 3 serving as a source and a drain of a transistor, a gate electrode 4 made of polysilicon, and an interlayer made of a silicon oxide film are formed on a silicon substrate 1. An insulating film 5 and the like are formed, and a lower electrode 6a made of a multilayer film of titanium and platinum, a capacitive insulating film 6b made of a ferroelectric film such as PZT or SrBi ₂ Ta ₂ O ₉ and an upper electrode 6c made of platinum are formed thereon. Is formed on the entire surface. Next, each layer is etched into a desired pattern by a dry etching method such as ion milling using argon ions to form the capacitor 6. Next, FIG.
As shown in (b), a protective insulating film 7 for a capacitor is formed on the entire surface, and a contact hole 8 reaching the diffusion region 3, the lower electrode 6a and the upper electrode 6c is formed. Next, FIG.
As shown in FIG. 1, a first wiring layer 9 and a second wiring layer 10 are formed on the entire surface. The first wiring layer is a diffusion barrier layer for suppressing a eutectic reaction between platinum as an electrode material of the capacitor and aluminum as a material of the second wiring layer, and titanium nitride is used. Next, as shown in FIG. 4D, the first wiring layer 9 and the second wiring layer 10 are selectively etched, and then the temperature is increased in a nitrogen atmosphere to reduce stress applied to the capacitor. A heat treatment at 450 ° C. is performed.

[0005]

However, in the semiconductor device manufactured by the above-mentioned conventional manufacturing method, the stress acting on the capacitance element is still very large even by the heat treatment after the formation of the first and second wiring layers. As a result, the leakage current of the capacitor has increased, and the dielectric strength has been further reduced.

The present invention solves the above-mentioned conventional problems. Even if a wiring layer is formed, an increase in leakage current and a decrease in withstand voltage of a capacitive element using a high dielectric or ferroelectric as a capacitive insulating film can be prevented. An object of the present invention is to provide a method for manufacturing a semiconductor device which can prevent such a problem.

[0007]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device having at least a dielectric film or a ferroelectric film having a high dielectric constant as a capacitive insulating film. Forming a first wiring layer on the formed semiconductor substrate; performing a first heat treatment; forming a second wiring layer on the first wiring layer; A step of selectively etching the second wiring layer and a step of performing a second heat treatment.

According to the present invention, it is possible to prevent an increase in leakage current and a decrease in dielectric strength of a capacitive element using a high dielectric or ferroelectric as a capacitive insulating film.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a semiconductor substrate on which a capacitive element using at least a dielectric film having a high dielectric constant or a ferroelectric film as a capacitive insulating film is formed. Forming a first wiring layer;
Performing a second heat treatment, forming a second wiring layer on the first wiring layer, selectively etching the first and second wiring layers, and performing a second heat treatment on the semiconductor substrate. The stress acting on the capacitive element can be reduced by heat treatment after forming each wiring layer, so that the leakage current of the capacitive element using the high dielectric film and the ferroelectric film as the capacitive insulating film is increased. In addition, a decrease in dielectric strength can be prevented.

According to a second aspect of the present invention, the atmosphere of the first heat treatment step is performed with an inert gas such as nitrogen or argon, or a mixed gas thereof, or a vacuum. Can be reduced without increasing the capacitance.

According to a third aspect of the present invention, the temperature of the first heat treatment step is set to 300 ° C. or more and 450 ° C. or less, thereby reducing stress on the capacitor without deteriorating the characteristics of the transistor. can do.

According to a fourth aspect of the present invention, the first heat treatment step is performed by a rapid temperature rise annealing method at a temperature of 450 ° C. or more and 550 ° C. or less. Can be reduced without deteriorating the characteristics of the capacitor.

According to a fifth aspect of the present invention, the first wiring layer is made of titanium nitride, titanium tungsten, a multilayer film of titanium and titanium nitride, or a multilayer film of titanium and titanium tungsten.

According to a sixth aspect of the present invention, the second wiring layer is a metal layer containing aluminum.

According to a seventh aspect of the present invention, the atmosphere of the second heat treatment step is performed with an inert gas such as nitrogen or argon or a mixed gas thereof, or a vacuum.
Thus, stress on the capacitor can be reduced without increasing the resistance of the wiring layer.

According to the present invention, the temperature of the second heat treatment step is set to 300 ° C. or more and 450 ° C. or less, thereby reducing the stress on the capacitor without deteriorating the characteristics of the transistor. can do.

According to a ninth aspect of the present invention, the second heat treatment step is performed by a rapid temperature rise annealing method at a temperature of 450 ° C. or more and 550 ° C. or less. Stress on the capacitive element can be reduced without deteriorating the capacitance.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1E are a process sectional view and a process flowchart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. First, FIG.
And (b), a lower electrode 6a made of a multilayer film of titanium and platinum, and a capacitive insulating film 6 made of SrBi ₂ Ta ₂ O ₉ are formed on a silicon substrate 1 on which a semiconductor integrated circuit is formed.
b and a capacitive element 6 composed of an upper electrode 6c composed of platinum,
The protection insulating film 7 for the capacitor and the contact hole 8 are formed in the same manner as in the conventional example. Next, as shown in FIG. 1C, the entire surface is covered with a first wiring layer 9 made of a laminated film of titanium and titanium nitride, which is a diffusion barrier layer. After that, a first heat treatment is performed in order to reduce stress acting on the capacitor 6. Note that the first heat treatment is performed at 450 ° C. for 6 hours.
Performed in a nitrogen atmosphere for 0 minutes. Next, as shown in FIG. 1D, a second wiring layer 1 of a metal containing aluminum is formed on the entire surface.
0 is formed. Then, as shown in FIG.
Selectively etching the wiring layer and the second wiring layer,
Finally, a second heat treatment is performed. Note that the second heat treatment is performed at 450 ° C. for 60 minutes in a nitrogen atmosphere.

As described above, according to the above embodiment, the first
After the first wiring layer 9 is formed, the first heat treatment is performed, whereby the stress on the capacitor 6 due to only the first wiring layer 9 serving as the diffusion barrier layer can be reduced. further,
By performing the heat treatment in a nitrogen atmosphere, the stress of the capacitor 6 can be reduced without increasing the resistance of the wiring layer and without deteriorating the ferroelectric film.

When the stress after the second heat treatment is compared between the conventional example and this embodiment, for example, when SrBi ₂ Ta ₂ O ₉ is used as the capacitive insulating film of the capacitive element 6, FIG.
As shown in (1), the stress in the convex direction acts in the conventional example, whereas the stress is 0 in the present embodiment. Thereby, as shown in FIG. 3, when SrBi ₂ Ta ₂ O ₉ is used as the capacitive insulating film of the capacitive element 6, the leakage current is 3
It is reduced by an order of magnitude and the dielectric strength is improved by a factor of five. That is, it is possible to realize a life in a high electric field at a level sufficient for practical use.

In this embodiment, the first heat treatment and the second heat treatment are performed at a temperature of 450 ° C. for 60 minutes.
0 ° C to 450 ° C is desirable. That is, at a temperature lower than 300 ° C., there is no effect of reducing the stress by the heat treatment.
Further, when heat treatment is performed at a temperature higher than 450 ° C., titanium diffuses in silicon at a contact portion with a source, a drain, or a gate of the transistor, so that electrical characteristics of the transistor deteriorate. However, when performing the heat treatment at a temperature of 300 ° C.,
It takes about 100 hours to obtain the same effect as the heat treatment at 0 ° C. for 60 minutes.

In the first heat treatment step of the above embodiment, a rapid temperature rise annealing method (hereinafter referred to as an RTA method) can be used.

The RTA method is a heat treatment method in which the temperature of the substrate surface is rapidly increased to a high temperature by lamp heating to the substrate surface, and after a very short holding time, the temperature is rapidly decreased. Therefore, the temperature rise inside the substrate can be suppressed.
Even if the heat treatment is performed at a temperature of 0 ° C. or more, it becomes possible to heat-treat the wiring layer and the capacitor without diffusion of titanium in the contact portion. Specifically, by performing a heat treatment under the conditions of RTA at a temperature rising rate of 100 ° C./min and a temperature of 550 ° C. for 60 seconds, the above-mentioned temperature of 450 ° C.
It was confirmed that the same effect as the heat treatment under the condition of 0 minutes was obtained. The temperature range of RTA is 450 ° C. or higher, 55
0 ° C. or less is desirable. That is, at a temperature lower than 450 ° C., the RTA method for a short time has no effect of reducing stress,
If the temperature is higher than 550 ° C., the temperature inside the substrate increases greatly, and the characteristics of the transistor deteriorate.

In the above embodiment, nitrogen is used as the atmosphere for the first and second heat treatment steps. However, the same effect can be obtained even in an inert gas such as argon, a mixed gas of nitrogen and argon, or a vacuum. It is possible to get.

In the above embodiment, a multilayer film of titanium and titanium nitride is used as the first wiring layer. However, the same effect can be obtained with titanium nitride, a multilayer film of titanium and titanium tungsten, or titanium tungsten. Can be

Further, in the above embodiment, the heat treatment is performed at a temperature of 450 ° C. for 60 minutes as the second heat treatment step, but the same effect can be obtained by using the rapid heat-up annealing method as the second heat treatment. . However, also in this case, 450 ° C. or more,
A temperature range of 550 ° C. or less is desirable.

[0027]

According to the method of the present invention, after the first wiring layer is formed on the entire surface, an inert gas such as nitrogen or argon, or a mixed gas containing them, or a heat treatment in a vacuum is performed. By forming the second wiring layer, a semiconductor device having excellent reliability which can prevent an increase in leakage current and a decrease in withstand voltage of a capacitor using a high dielectric film or a ferroelectric film as a capacitor insulating film can be prevented. Can be provided.

[Brief description of the drawings]

FIGS. 1A to 1E are first-stage process diagrams in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a characteristic diagram comparing stress acting on a capacitive element according to an embodiment of the present invention and a conventional example.

FIG. 3 is a characteristic diagram comparing a leakage current and a dielectric strength voltage of a capacitive element according to an embodiment of the present invention and a conventional example.

FIGS. 4A to 4D are process diagrams in a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 isolation oxide film 3 diffusion region 4 gate electrode 5 interlayer insulating film 6 capacitive element 6a lower electrode 6b capacitive insulating film 6c upper electrode 7 protective insulating film for capacitive element 8 contact hole 9 first wiring layer 10 second Wiring layer

Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 27/10 451 29/788 29/792 (56) References JP-A-7-50391 (JP, A) JP-A 5-304251 (JP) , A) (58) Fields investigated (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 21/8247 H01L 27/04 H01L 27/10 H01L 29/788 H01L 29 / 792

Claims (9)

(57) [Claims] A step of forming a first wiring layer on a semiconductor substrate on which a capacitive element using at least a dielectric film or a ferroelectric film having a high dielectric constant as a capacitive insulating film is formed; Performing a heat treatment, forming a second wiring layer on the first wiring layer, selectively etching the first wiring layer and the second wiring layer, Performing a second heat treatment on the semiconductor substrate. 2. The method according to claim 1, wherein the atmosphere of the first heat treatment step is an inert gas such as nitrogen or argon, or a mixed gas thereof, or a vacuum. 3. The temperature of the first heat treatment step is 300 ° C.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature is 450 ° C. or lower. 4. The method according to claim 1, wherein the first heat treatment step is performed at 450 ° C. or higher.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed by a rapid temperature rise annealing method at a temperature of 550 ° C. or less. 5. The method according to claim 1, wherein the first wiring layer is titanium nitride, titanium tungsten, or a multilayer film of titanium and titanium nitride.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a multilayer film of titanium and titanium tungsten. 6. The method according to claim 1, wherein said second wiring layer is a metal layer containing aluminum. 7. The atmosphere of the second heat treatment step is an inert gas such as nitrogen or argon, a mixed gas thereof, or a vacuum.
7. The method for manufacturing a semiconductor device according to 2, 3, 4, 5, or 6. 8. The temperature of the second heat treatment step is 300 ° C.
8. The method according to claim 1, wherein the temperature is 450 ° C. or lower. 9. The method according to claim 1, wherein the second heat treatment step is performed at 450 ° C. or higher.
The heat treatment is performed by a rapid temperature rising annealing method at a temperature of 550 ° C. or less,
8. The method for manufacturing a semiconductor device according to 6 or 7.