JP2901785B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a flash EEPROM (Electrically Erasable) which can electrically write or erase data.
rasable and Programmable R
(Ead Only Memory: EEPROM).

[0002]

2. Description of the Related Art Conventionally, a flash EEPROM (nonvolatile semiconductor memory device) has been known as a semiconductor memory device capable of electrically writing and erasing data. FIG. 14 is a block diagram showing the overall configuration of a conventional flash EEPROM.

Referring to FIG. 14, a conventional flash EE
The PROM has a memory cell array 30 in which a plurality of memory cells (not shown) for storing data are arranged in a matrix, an X decoder 21 and a Y decoder 22 for decoding external address signals, and a Y cell. Gate 23
, A control circuit 24, and an input / output circuit 25.
X decoder 21, Y decoder 22, Y gate 23, control circuit 24, input / output circuit 25, and memory cell array 30
Are formed on the same substrate on the semiconductor chip 26. Conventional flash EEPROM further includes a power supply input terminal Vcc28, and a high voltage power input terminal V _PP 29.

FIG. 15 is a sectional structural view showing a memory cell (semiconductor storage element) constituting the memory cell array shown in FIG.

Referring to FIG. 15, a conventional memory cell comprises:
P-type silicon semiconductor substrate 31 having an impurity concentration of 1 × 10 ¹⁵ / cm ³ and a specific resistance of 10 Ω · cm, arsenic (As) under the conditions of an acceleration voltage of 30 to 40 KV and a dose of 1 × 10 ¹⁵ / cm ² It was formed by ion implantation impurity concentration 1 × 10 ²⁰ / cm ³ of n ⁺ -type drain region 3
2, acceleration voltage 100 to 150 KV, dose 5 × 10
N having an impurity concentration of 1 × 10 ²⁰ / cm ³ formed by ion implantation of arsenic (As) under a condition of ¹⁵ / cm ^2
+ Source region 33, n ⁺ type drain region 32 and n ⁺
Channel region 34 formed between mold source region 33
A 100 ° thick gate oxide film 35 formed on the channel region 34, a floating gate 36 made of a polycrystalline silicon layer formed on the gate oxide film 35,
Interlayer insulating film 3 formed on floating gate 36
7 and a control gate 38 made of a polycrystalline silicon layer formed on the interlayer insulating film 37.

Next, with reference to FIGS. 14 and 15, data writing and erasing operations of a conventional flash EEPROM will be described.

For writing data to the memory cell, first, 12.5 V is applied to the high voltage power supply input terminal V _PP 29. The control gate 38 is connected to the high-voltage power supply input terminal V _PP 29.
Is supplied with 12.5V. At the same time, 8 V is supplied to the n ⁺ -type drain region 32 via a load resistor. On the other hand, the n ⁺ type source region 33 is grounded, and the ground potential (GN
D). Under such a condition, the n ⁺ type source region 3
Electrons move from 3 toward the n ⁺ -type drain region 32. A current of about 0.5 to 1 mA flows through the channel region 34. At this time, the flowing electrons are accelerated by a high electric field near the n ⁺ -type drain region 32. Thereby, electrons obtain high energy exceeding an energy barrier of 3.2 eV from the surface of the P-type silicon semiconductor substrate 31 to the gate oxide film 35. The electrons that have obtained this high energy are called hot electrons. Part of the hot electrons jumps over the barrier of the gate oxide film 35 and the control gate 38
At a high potential (12.5 V). The floating gate 36 is in an electrically negative state. This write state is made to correspond to data “0”.

On the other hand, erasing data from a memory cell
As with writing, firstly, to the high voltage power input terminal V _PP 29 12.
5 V is applied. This high voltage power supply input terminal V _PP 29 to n
12.5 V is supplied to ⁺ type source region 33. The control gate 38 is grounded and attains a ground potential (GND). The n ⁺ type drain region 32 is set in a floating state. Under such a state, the gate oxide film 35 between the floating gate 36 and the n ⁺ type source region 33 is formed.
, A high electric field is generated. Thereby, the energy barrier of the gate oxide film 35 is reduced. Electrons are emitted by being pulled from the floating gate 36 to the high potential (12.5 V) of the n ⁺ type source region 33. Floating gate 36 and n
^A current called a tunnel current flows between the ^positive type source region 33 and the ^positive type source region 33. That is, electrons are extracted from the floating gate 36 by a predetermined amount, and this state corresponds to data “1”.

[0009]

As described above, in the conventional flash EEPROM, when data is erased, n ⁺
A high voltage V _PP (12.5 V) is applied to the mold source region 33. Therefore, the junction breakdown voltage of the n ⁺ -type source region 33 needs to be maintained higher than V _PP (12.5 V) with a margin.

However, when the elements are miniaturized with the integration of the semiconductor device, the well concentration is increased, the boron concentration of the channel cut is increased, and the n ⁺ region is increased due to the lower temperature of the heat treatment. Phenomenon such as steep impurity distribution occurs. As a result, it tends to be difficult to keep the junction breakdown voltage sufficiently high. The reduction in junction breakdown voltage due to such integration causes the following problems.

That is, the leakage current at the time of data erasure increases due to a decrease in the junction breakdown voltage. Further, there is a problem that avalanche breakdown generates hot holes, and the injection of the hot holes into the gate oxide film 35 significantly deteriorates the reliability of the gate oxide film 35.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor memory device capable of erasing data with a low source voltage (voltage applied to an impurity region). And

[0013]

According to a first aspect of the present invention, there is provided a semiconductor memory device, comprising: a first conductivity type semiconductor substrate; and a second conductivity type formed on a main surface of the first conductivity type semiconductor substrate at a predetermined interval. A pair of impurity regions of conductivity type, a charge storage electrode formed between the pair of impurity regions via a first insulating film, and a control formed on the charge storage electrode via a second insulating film. In a semiconductor memory device including a flash EEPROM having an electrode, a threshold voltage when a voltage is applied to the control electrode in a state where the charge storage electrode is electrically neutral is 0 volt or more and a voltage applied to the charge storage electrode is The threshold voltage is set to be equal to or less than 1/2 of the threshold voltage after the charge is accumulated.

[0014]

In the semiconductor memory device according to the present invention, when the voltage is applied to the control electrode while the charge storage electrode is electrically neutral, the threshold voltage is 0 volt or more, By setting the threshold voltage within 1/2 or less of the threshold voltage after accumulation, the voltage to be applied to the impurity region at the time of erasing data is reduced.

[0015]

Embodiments of the present invention will be described below.

First, the background of the present invention will be described. Consider an operation of erasing data written in a memory cell in a flash EEPROM.

The data erasing operation is performed by the Fowler-Nordheim tunnel effect phenomenon. The Fowler-Nordheim current is represented by the following equation (1).

[0018]

(Equation 1) Referring to this equation (1), it can be seen that the tunnel current density J depends very much on the electric field E applied to the oxide film.

Next, in a flash EEPROM,
A write (program) state and an erase state of data in the memory will be considered.

Normally, the threshold voltage V _th of a memory cell is
About 8V in program state (write state), 1 in erase state
It is set to about 2V. This is for the following reasons.

That is, when reading data after writing data, V _cc (up to 5 V) is applied to the control gate, and data is discriminated based on whether it is larger or smaller than V _cc . For this reason, the threshold voltage _Vth of the memory cell after data writing needs to be 5 V or more. If the threshold voltage _Vth of the memory cell becomes negative while data is erased, the memory cell transistor cannot be turned off. Therefore, the threshold voltage V _th of the memory cell in the erased state needs to be 0 volt or more.

With the above constraint including a margin,
The threshold voltage after writing is set to 8V, and the threshold voltage after erasing is set to 1-2V. Therefore, the threshold voltage V _th of the memory cell fluctuates (swings) by 6 to 7 V between the write state (program state) and the erase state. The voltage actually applied to the floating gate due to such a change in V _th is determined by the capacitance division ratio of the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the semiconductor substrate. This capacity division ratio is about 0.5 to 0.6. Therefore, the variation (6 to 7 V) of the threshold voltage _Vth of the memory cell corresponds to a variation of 3 to 4 V when viewed from the floating gate. That is, the voltage of the floating gate changes by 3 to 4 V between the data write state (program state) and the erase state.

Next, a phenomenon occurring when data is actually erased will be considered. Normally, data is always written before an erase operation of a memory cell is performed. Therefore, the memory cell to be erased is always in the written state, that is, in the state of high _Vth , regardless of the data content. The potential of the floating gate at this time is V _FP
And

From this state, the high voltage V is applied to the source region._STo
When applied, (V) _S-V_FP) / T_OXof
Charge is applied. Thereby, the above-mentioned Fowler-Nord
Deheim current flows. As a result, the floating game
The electrons in the data are withdrawn and the data is erased. Erase
In a later state, the floating gate
The voltage rises by 3 to 4 V as compared with the written state, and V_FEbecome.
Therefore, after the data erase operation is completed, the tunnel oxide film
Is applied to (V_S-V_FE) / T_OX= (V_S-V_FP-4) / t_OX To decrease.

That is, the electric field applied to the oxide film is the largest at the beginning of the erasing operation, and is decreased by 4 / t _OX at the completion of the erasing operation as compared with the initial stage of the erasing operation. From this Fowler-Nordheim equation, it can be seen that a large amount of current flows at the beginning of the erasing operation, and the current is greatly reduced when the erasing operation is completed.

FIG. 1 is a diagram showing the relationship between the erase voltage application time and the threshold voltage _Vth of a memory cell. Referring to FIG. 1, immediately after application of the applied voltage V _S of the source region, rapidly decreases V _th, it can be seen that thereafter decreasing moderately. In order to make this a predetermined V _th (1-2 V) within a preset erase time (for example, 10 msec), it is necessary to set V _S or V _S / t _OX to a certain value or more. That is, as V _S or V _S / t _OX is larger, the force for extracting electrons is larger and the erase time is shorter.

Here, the floating gate is electrically
The threshold voltage of the memory cell in the neutral state is V_th(N)
And Also, the threshold voltage after programming (after writing)
To V _th(P), and the threshold voltage after erasing is V_th(E)
And Flow after writing using these threshold voltages
Potential V of the gate_FPAnd floating gate after erase
Potential V_FEWhere
(2) and (3) are obtained.

V _FP = {V _th (N) −V _th (P)} × R (2) V _FE = {V _th (N) −V _th (E)} × R (3) R is the capacitance coupling ratio.

Next, the minimum electric field necessary to obtain a predetermined erase characteristic (erase speed) is considered.
Assuming that the minimum electric field is E _min , the minimum source voltage V _Smin required at that time is derived as follows.

E _min = (V _Smin −V _FP ) / t _OX (4) E _min = [V _Smin − {V _th (N) −V _th (P)} × R] / t _OX (5) V _Smin = t _OX · E _min + {V _th (N) −V _th (P)} × R (6) Since t _OX , E _min , V _th (P) and R are constants, By reducing V _th (N), V _Smin can be reduced. The minimum value of V _th (N) is the same as threshold voltage V _th after erasing described above, which must _satisfy V _th > 0.
_th (N) also needs to _satisfy V _th (N)> 0. Further, the threshold voltage V _th (N) in the neutral state is preferably as close to 0 volt, but is １ ／ or less of the threshold voltage V _th (P) after data writing (after programming). Then, the effect of reducing the voltage applied to the source region at the time of erasing can be obtained.

FIGS. 2 to 13 show a manufacturing process (first to twelfth steps) of a memory cell of a stacked gate type flash EEPROM according to an embodiment of the present invention.
It is sectional drawing which showed. Next, an actual manufacturing process for controlling the above-described threshold voltage will be described with reference to FIGS. 2 to 13. First, as shown in FIG. 2, a P-type silicon semiconductor substrate having a specific resistance of about 10 Ωcm. 1, boron (B) is implanted under the conditions of 100 KeV and 4 × 10 ¹² / cm ² . Then, a heat treatment is performed at 1150 ° C. for 6 hours to form a well (not shown).

Next, as shown in FIG. 3, boron (B) is applied to the region separating the active region at 80 KeV and 2.5 × 10 ^13.
/ Cm ² . Then, a field oxide film 2 having a thickness of about 6000 ° is formed in this region by using a selective oxidation method. The cross section taken along the line AA in the right drawing shown in FIG. 3 is the drawing shown on the left.

Next, as shown in FIG. 4, ions are implanted into the active region to control the threshold voltage _Vth of the memory cell. An oxide film 3 of about 100 ° is formed on the entire surface. First polycrystalline silicon layer 4 is formed on oxide film 3 by 1000
Deposit about Å. Using photolithography and anisotropic etching, the first polycrystalline silicon layer 4 is linearly patterned at a constant pitch in the column direction (vertical direction). That is, by performing anisotropic etching using the resist mask 7a, patterning is performed at a pitch as shown on the right side of FIG. After this, the resist mask 7
a is removed.

Next, as shown in FIG. 5, an ON film 5 is formed on the first polycrystalline silicon layer 4. Second on ON film 5
Is formed with a thickness of about 2500 °. Resist mask 7b on second polycrystalline silicon layer 6
To form

Next, as shown in FIG. 6, the resist mask 7b is patterned linearly at a constant pitch in the row direction (horizontal direction) using a photolithography technique. Then, the second polycrystalline silicon layer 6, the ON film 5 thereunder and the first polycrystalline silicon layer 4 are anisotropically etched using the resist mask 7b. Thus, the first polysilicon layer 4 forms the floating gate 4, and the second polysilicon layer 6 forms the control gate 6.

Next, as shown in FIG. 7, a region to be a drain region of the memory cell is covered with a resist mask 7c. Using the resist mask 7c as a mask, phosphorus (P) is ion-implanted into a region to be a source region by an oblique rotation implantation method. Further, the source region 8 is formed by ion-implanting arsenic (As).

Next, as shown in FIG. 8, the source region 8 of the memory cell is covered with a resist mask 9. Boron (B) is ion-implanted into a region to be a drain region by an oblique rotation implantation method. Further, the drain region 10 is formed by ion-implanting arsenic (As). Depending on the amount of impurities (the amount of doping) injected into the drain region 10,
The threshold voltage of the memory cell can be easily controlled.

Next, as shown in FIG. 9, an oxide film (not shown) is formed with a thickness of about 1500 °. Sidewalls 11 are formed on the side walls of the floating gate 4 and the control gate 6 by using anisotropic etching.

Next, as shown in FIG. 10, an oxide film 12 is formed on the entire surface to a thickness of about 1500 °. Further, a nitride film 13 is formed with a thickness of about 500 °.

Next, as shown in FIG. 11, boron (B)
An oxide film containing silicon and phosphorus (P) is formed to a thickness of about several thousand Å, and heat treatment and etching are performed to form an interlayer film 14. A resist mask 15 is formed in a predetermined region on the interlayer film 14 using a photolithography technique. The interlayer film 14 is isotropically etched using the resist mask 15 to form the interlayer film 14 having the tapered shape 17 in the opening 16. Thereafter, as shown in FIG. 12, an opening is formed on the drain region 10 by further performing anisotropic etching using the resist mask 15 as a mask.

Finally, as shown in FIG. 13, on the drain region 10 thus opened, a titanium 18 is formed with a thickness of about 500 ° so as to be electrically connected. Then, aluminum 19 is formed with a thickness of about 5000 °. By using a photolithography technique and a chemical process, a bit line (18, 19) that is in contact with the drain region 10 is formed by patterning a laminated film of titanium 18 and aluminum 19.

In the above embodiment, in the manufacturing process described with reference to FIG. 4, ion implantation was performed before forming the polycrystalline silicon layer 4. However, the present invention is not limited to this. The threshold value of the memory cell can be controlled also by performing boron (B) implantation at a higher energy.

[0043]

According to the first aspect of the present invention, the threshold voltage when a voltage is applied to the control electrode in a state where the charge storage electrode is electrically neutral is 0 volt or more, and is applied to the charge storage electrode. Since the voltage to be applied to the impurity region at the time of data erasure is reduced by setting the threshold voltage within a range equal to or less than 1/2 of the threshold voltage after the accumulation of the charges, the source voltage (application to the impurity region) is reduced. Voltage) can be provided. The electrically neutral state of the charge storage electrode can be obtained by erasing the chip with UV (ultraviolet).

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between an erase voltage application time and a threshold voltage _Vth of a memory cell.

FIG. 2 is a cross-sectional view showing a first step of a manufacturing process of the memory cell of the stacked gate type flash EEPROM of one embodiment according to the present invention.

FIG. 3 is a cross-sectional view showing a second step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM of one embodiment according to the present invention.

FIG. 4 is a sectional view showing a third step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention;

FIG. 5 is a sectional view showing a fourth step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to the embodiment of the present invention;

FIG. 6 is a sectional view showing a fifth step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention;

FIG. 7 is a sectional view showing a sixth step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention;

FIG. 8 is a sectional view showing a seventh step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention;

FIG. 9 is a sectional view showing an eighth step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention;

FIG. 10 is a sectional view showing a ninth step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention;

FIG. 11 is a sectional view showing a tenth step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention;

FIG. 12 is a cross-sectional view showing an eleventh step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention.

FIG. 13 is a sectional view showing a twelfth step of the manufacturing process of the memory cell of the stacked gate type flash EEPROM according to one embodiment of the present invention;

FIG. 14 shows a conventional nonvolatile semiconductor memory device (EEPRO);
It is a block diagram showing the whole composition of M).

15 is a sectional structural view showing a memory cell (semiconductor storage element) constituting the memory cell array shown in FIG. 14;

[Explanation of symbols]

 1: P-type silicon semiconductor substrate 2: Field oxide film 3: Oxide film 4: First polycrystalline silicon layer (floating gate) 5: ON film 6: Second polycrystalline silicon layer (control gate) 8: Source region 10: Drain region 18: Titanium 19: Aluminum In each drawing, the same reference numerals indicate the same or corresponding parts.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] A first conductivity type semiconductor substrate; a pair of second conductivity type impurity regions formed at a predetermined interval on a main surface of the first conductivity type semiconductor substrate; A semiconductor memory including a flash EEPROM having a charge storage electrode formed between a pair of impurity regions via a first insulating film, and a control electrode formed on the charge storage electrode via a second insulating film. In the apparatus, a threshold voltage when a voltage is applied to the control electrode in a state where the charge storage electrode is electrically neutral is 0 volt or more, and a threshold after the charge is stored in the charge storage electrode. A semiconductor memory device characterized in that the voltage is set within a range of 1/2 or less of a value voltage.