JP3152749B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a nonvolatile semiconductor memory device having a two-layer gate structure including a floating gate and a control gate, a method of manufacturing the same, and an erasing method.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory device having as a memory cell a MOS transistor having a two-layer gate structure including a floating gate and a control gate, for example, a flash type EEPROM (Electrically Erasable and PRAM).
In the program (programmable ROM), data is programmed (written) by selectively injecting charges, for example, electrons, into the floating gate of the memory cell, and by selectively extracting charges, for example, electrons from the floating gate of the memory cell. Data is erased.

In writing data in such a memory cell comprising a MOS transistor having a two-layer gate structure, a high voltage is applied to a control gate and a drain region, and a channel region between a source region and a drain region is formed near a drain region. This generates an electron-hole pair, and injects the electrons into the floating gate. Data reading is performed by applying a reading voltage to the control gate and the drain region. At the time of reading this data, in the case of a memory cell in which electrons have been injected into the floating gate in advance, the threshold voltage has risen, and even if a reading voltage is applied to the control gate, the memory cell does not turn on. On the other hand, in the case of a memory cell in which electrons are not injected into the floating gate, the threshold voltage is in the original low state,
When a read voltage is applied to the control gate, the memory cell turns on. Therefore, at the time of data reading, the stored data is determined by whether or not a current flows through the memory cell.
Further, in erasing data, a high voltage is applied to the source region, so that FN (Fo) is applied from the floating gate to the source region.
This is performed by generating a wler-Nordheim tunnel current (hereinafter, referred to as FN current) and discharging electrons stored in the floating gate to the source.

FIG. 13 shows a conventional flash type EEPROM.
It is sectional drawing of M memory cell. In the surface region of the P-type silicon semiconductor substrate 1, an N ⁺ impurity diffusion region is formed,
These are referred to as a source region 7 and a drain region 8. These source - so as to surround the outside of the scan / drain regions 7, 8 N ^-
The low concentration impurity diffusion regions 71 and 81 are formed, and the withstand voltage of the MOS transistor formed on the semiconductor substrate 1 is increased. On the region between the source / drain regions 7 and 8 of the semiconductor substrate 1, a silicon oxide film having a thickness of 1
A first gate insulating film 2 of about 00 angstroms is formed by thermal oxidation or the like, and a floating gate 3 is formed thereon by a first layer of polysilicon. This floating gate 3
On top of this, a second gate insulating film 4 made of, for example, a laminate of a silicon oxide film / silicon nitride film / silicon oxide film is formed, and a control gate 5 is formed thereon. The control gate 5 is made of a second layer of polysilicon, but a high melting point metal or a silicide film thereof is deposited on the polysilicon film to lower the resistance of the gate. Saw
Since the source / drain regions 7 and 8 partially extend below the gate, both ends of the gate are respectively disposed on both regions.

As described above, the data erasure of the memory cell is performed by applying a high voltage to the source region. At the time of this erasing, electric field concentration occurs at the lower end of the floating gate on the source side (indicated by A in the figure), and when the FN current flows there, the amount of current at that time is reduced by the lower end of the gate of each cell transistor. (Part A) It largely depends on the shape. Normally, the cell transistor has considerable irregularities, and particularly has a sharp corner, so that the erasing characteristics of the cell transistor greatly vary. To avoid electric field concentration at the lower end of the gate as shown in FIG. 14, a bird's peak (portion indicated by B in FIG. 14) is inserted at the lower end of the gate, and an EEPROM memory cell having a rounded corner is also known. ing. FIG. 15 shows an impurity concentration profile of the surface of the source N ⁺ diffusion region of the memory cell. With the origin on the extension of the end of the floating gate 3 on the source 7 side, + x is set in the channel direction between the source / drain regions. Generally, the source region 7 is formed by introducing impurities into the semiconductor substrate 1 by ion implantation or the like using the gate 5 as a mask, and thermally diffusing the impurities.

Therefore, there is only an impurity diffused from the side below the gate which is masked at the time of impurity introduction. Therefore, as shown in FIG.
The impurity concentration tends to decrease monotonically. In other words, the source / drain regions 7 and 8 have their ends extending below the floating gate 3, and thus are separated from the portion immediately below the floating gate 3 and from the floating gate 3. Divided into parts. The portion immediately below the floating gate corresponds to a region in the channel direction + x from the origin of the impurity concentration distribution diagram in FIG. 15, and the portion away from the floating gate corresponds to a region in the -x direction from the origin. . This figure shows the distribution of the surface impurity concentration in the source region. The portion immediately below the floating gate is as described above, and the surface impurity concentration in the portion away from the floating gate is almost the same. The portion has the same density as the origin at the portion immediately below the floating gate. In general, when electrons are extracted from the floating gate to the source region at the time of erasing, the electrons are extracted to the high concentration region of the source region. Therefore, in the conventional memory cell shown in FIGS. 13 and 14, the source region of the source region is located at the origin of FIG. 15, that is, immediately below the lower end of the floating gate on the source side, even among the portions immediately below the floating gate. Since there is a high concentration region, in the memory cell of FIG. 13, a passage for electrons is formed at a portion A in FIG.

[0007]

When an erasing operation is performed in the memory cell of FIG. 14, the FN current flows through a region where no bird's beak is present as indicated by an arrow. As a result, it is possible to avoid the problem as in the first case where the electric field is concentrated at the gate end having a variation in shape.
However, as the miniaturization of the semiconductor device progresses, the gate length becomes shorter, and as a result, it becomes difficult to secure a bird's beak width and sufficiently round the end portion. Also,
This rounding is usually performed by an oxidation process such as post-oxidation. However, with the miniaturization, if the heat process requires a shorter time and a lower temperature, the gate end can be sufficiently formed. It is difficult to round. The present invention has been made in view of the above circumstances, and provides a two-layer gate nonvolatile semiconductor memory device that suppresses erase variation and improves erase characteristics without sufficiently rounding the lower end of the floating gate on the source side. It is intended to be.

[0008]

A feature of the present invention is a double-layer gate type nonvolatile semiconductor memory device in which an end of a source / drain region extends below a floating gate. The portion of the first gate insulating film that is in contact with the lower end of the floating gate on the source side is not directly in contact with the source region, or is not in contact with this source region.
In contact with the low-concentration impurity region of the semiconductor region. That is, in the method for manufacturing a semiconductor memory device according to the present invention, a step of forming a source region having an exposed surface on a semiconductor substrate and a step of forming a drain region having an exposed surface on the semiconductor substrate Forming a first gate insulating film on a portion of the source / drain region of the semiconductor substrate and a channel region between the source / drain regions; and forming a first gate insulating film on the first gate insulating film. A step of forming a floating gate, a step of forming a second gate insulating film on the floating gate, a step of forming a control gate on the second gate insulating film, Forming a groove by etching a predetermined area where the area is exposed, arranging the groove at least below the lower end on the source side of the floating gate; And a step of coating the film.

[0009]

[0010]

[0011]

[0012]

[0013]

[0014]

In a two-layer gate type nonvolatile semiconductor memory device for electrically erasing, a portion of the first gate insulating film which is in contact with the lower end of the floating gate on the source side is directly connected to the source. The floating gate of the source region is located closer to the channel than directly below the lower end on the source side of the floating gate because it is not in contact with the region or is in contact with the low concentration impurity region of the source region. A surface impurity concentration peak region immediately below is formed. As a result, an oxide film passing current (for example, FN current) at the time of the erase operation is caused to flow in the surface impurity concentration peak region closer to the channel than the gate end, so that the erase characteristic does not depend on the sharp shape of the gate end. Can be suppressed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. First, a first reference example will be described with reference to FIGS. FIG. 1 is a sectional view of a two-layer gate type nonvolatile memory such as a 16 Mbit flash EEPROM, FIGS. 2 to 3 are sectional views of the manufacturing process, and FIG. FIG. 9 is a surface impurity concentration distribution diagram of a source region below a floating gate. P-type silicon semiconductor substrate 1
An N ⁺ impurity diffusion region (hereinafter, referred to as N ⁺ region) is formed in the surface region of FIG. N ^- low-concentration impurity diffusion regions (hereinafter referred to as N-type
⁽ Referred to as “regions”) 71 and 81 are formed, and the withstand voltage of the MOS transistor formed on the semiconductor substrate 1 is increased. A first gate insulating film 2 made of a silicon oxide film and having a thickness of about 100 A is formed on the region between the source / drain regions 7 and 8 of the semiconductor substrate 1 by thermal oxidation or the like. The floating gate 3 is formed of the first layer of polysilicon. The gate length of the floating gate is 0.6 to
0.8 μm.

On the floating gate 3, a second gate insulating film 4 composed of a laminate of, for example, a silicon oxide film / silicon nitride film / silicon oxide film is formed, and a control gate is formed thereon. 5 is formed. The control gate 5 is made of a second layer of polysilicon. Here, a silicide film is deposited on the polysilicon film to reduce the resistance of the gate. Since the source / drain regions 7, 8 partially extend below the gate, both ends of the gate are arranged on both regions, respectively. An N-type low-concentration impurity diffusion region (N ^- region) 10 having a lower impurity concentration than the source region is provided in a part of the surface region of the source region 7, and the source of the floating gate 3 is provided on this region. -The lower end of the tooth side is arranged. Therefore, the portion of the source region 7 exposed on the surface of the substrate below the floating gate 3 is not disposed immediately below the lower end on the source side, and is not disposed between the source / drain regions. Channel region. The control gate 5 and the floating gate 3 are covered with an insulating film 6 such as a silicon oxide film. A gate electrode G, a source electrode S, and a drain electrode D are formed in the control gate 5, the source region 7, and the drain region 8, respectively. Although not shown, the gate electrode G
And the drain electrode are connected to a word line and a bit line of the memory, respectively.

In the cell having such a configuration, the impurity concentration profile of the source region, particularly, the portion immediately below the floating gate 3 is represented as shown in FIG. The origin is defined as the origin (0) on the extension of the lower end portion of the floating gate 3 on the source side, and + x is taken on the channel side (therefore, the direction away from the floating gate 3 on the opposite side to the channel is -x). As is clear from the figure, just below the lower end on the source side (near x = 0)
The impurity concentration peak region on the surface of the source region is formed closer to the channel. This impurity concentration peak
It is appropriate that the peak value is approximately 1 × 10 ^{20 to} 3 × 10 ²¹ cm ⁻³ , but it is needless to say that the present invention is not limited to this range. This region has a higher impurity concentration than other regions, and is therefore referred to as an N ⁺ region. The portion of the source region 3 in the -x direction away from the floating gate is the N ^- region 10, which maintains the low surface impurity concentration at the position x = 0 almost uniformly. The impurity concentration of this N ⁻ region 10 is
What is necessary is just higher than about 1 × 10 ¹⁸ cm ^{−3 and} lower than the peak value of the impurity concentration. N ⁻ on the opposite side of the region 10 from N ⁻
The impurity concentration of the region 71 may be lower than the peak value of the impurity concentration, and becomes substantially equal to the impurity concentration of the substrate (for example, on the order of 10 ¹⁶ cm ⁻³ ) near the boundary with the substrate.

The source electrode S is, for example, 11 V to 13 V
When an erasing operation is performed by applying a positive bias of a certain degree and a gate electrode G of zero or a negative bias, the potential difference between the floating gate 3 and the source electrode S causes the first gate insulating film 2
When the electric field is increased, electrons are extracted to the source side by the FN current. At this time, the depletion layer extends immediately below the lower end on the source side, which is the N ⁻ region 10, to have a high resistance.
The FN current flows not in the gate end but in the portion of the N ⁺ source region 7 where the surface impurity concentration is high as shown by the arrow. Therefore, the erasing characteristics of this memory do not depend on the shape of the end of the floating gate, so that variations can be suppressed. It is not preferable that the N ^- region 10 extends too far in the channel direction below the gate from immediately below the gate end A, since the channel length Lc becomes short. When a source region 7 is formed by ion-implanting impurities into a semiconductor substrate and performing thermal diffusion,
Since thermal diffusion is also performed in the lateral direction, even if ions are implanted using the gate as a mask, the diffusion region extends to a portion below the gate. This lateral diffusion corresponds to 60% of the diffusion in the depth direction with respect to the semiconductor substrate.

Accordingly, when the impurity for the diffusion region is ion-implanted vertically to the semiconductor substrate using the gate end as a mask, the floating gate of the source region 7 including the N ^- region 71 is formed.
Length x _s of the portion below the bets 3, like source - corresponding to 0.6 times the depth x _j of the semiconductor substrate 1 of the surface of the source region to the bottom. However, for example, when ion implantation obliquely, x _s is much larger. The N ^- source comprises a region 71 - depth x _j of the source region 7, but in the order of 0.2 to 0.3 [mu] m, source - source region of the gate - part under preparative length x _s as appropriate It is also possible to go beyond the range of the value of x _j in order to adjust the length to In addition, it is necessary that the N ^- region 10 also goes under the floating gate 3 so as not to be affected by the shape of the gate end A. If the length t is set to about 6 to 20% of the gate length Lg of the floating gate 3, the influence of the gate end is as follows.
It is not so much affected and the channel length is not made too small.

Next, a method of manufacturing this nonvolatile memory will be described. A silicon thermal oxide film serving as a first gate insulating film 2, a first polysilicon film serving as a floating gate 3, and a second gate at predetermined positions on the P-type silicon semiconductor substrate 1. After sequentially depositing a silicon oxide film / silicon nitride film / silicon oxide film laminate serving as a gate insulating film 4 and a polycide film comprising a second polysilicon film serving as a control gate 5 and a tungsten silicide film, To form a stacked gate having a two-layer gate structure (FIG. 2). Then, As, for example, 60 KeV, 1
Ion implantation is performed at a dose of about × 10 ¹⁶ cm ⁻² . Next, a silicon oxide (SiO ₂ ) film 6 is deposited by low pressure CVD to about 200 A, and P
KeV ions are implanted at about 2 × 10 ¹³ cm ⁻² , and the resultant is thermally diffused to form source / drain regions. The N ⁺ source region 7 and the N ⁺ drain region 8 are formed by As ion implantation with a small diffusion coefficient, and the N ⁻ low-concentration impurity diffusion regions 71 and 81 are formed by P ion implantation with a large diffusion coefficient. It is formed.

Subsequently, a photoresist 9 having a pattern in which only the vicinity of the lower end of the floating gate 3 in the source region 7 is opened (FIG. 3). Using this resist pattern as a mask, for example, BF ₂ is ion-implanted at about 20 keV and about 2 × 10 ¹⁵ cm ⁻² , and is thermally diffused to form a source region 7 immediately below the lower end of the floating gate ₃ on the source side. N ^- region 1 in the surface region of
0 is formed. This region includes just below the lower end of the floating gate 3 on the source side, and extends toward the channel from here.
Thereafter, an interlayer insulating film is deposited on the semiconductor substrate 1 according to a normal method of manufacturing a semiconductor device, and further, a contact hole is opened, and a post-process of wiring formation is performed to complete a nonvolatile memory. In this reference example, the implanted As and P are thermally diffused, and then BF ₂ is ion-implanted. However, if a desired profile as shown in FIG. The insertion position, the presence / absence of introduction of the thermal diffusion step, and the ion implantation order of the impurity species are not limited. For example, As and P have a tilt angle of 30 ° and BF ₂ has a tilt angle of 0 °.
If the ion implantation is performed at a degree, the diffusion heat process can be appropriately suppressed. Further, in the above reference example, the ion implantation method is used, but other existing impurity introduction methods such as solid phase diffusion can be used without limitation.

Next, a second reference example will be described with reference to FIG. The figure is a sectional view of a two-layer gate type nonvolatile memory. In this example, the same conductivity type low-concentration impurity diffusion regions (71 and 81 in FIG. 1) are not provided outside the high-concentration source / drain region. As in the previous embodiment, N ⁺ is added to the surface region of the P-type silicon semiconductor substrate 1.
An impurity diffusion region is formed, which is referred to as a source region 7 and a drain region 8. This source / drain region 7,
On the region between 8 and 10, a silicon oxide film having a thickness of 10
A first gate insulating film 2 of about 0A is formed by thermal oxidation or the like, and a floating gate 3 is formed thereon by a first layer of polysilicon. On this floating gate 3, for example,
A second gate insulating film 4 composed of a laminate of a silicon oxide film / silicon nitride film / silicon oxide film is formed, and a control gate 5 is formed thereon. The control gate 5 is 2
In this case, the gate resistance is lowered by depositing a silicide film on the polysilicon film. Since the source / drain regions 7, 8 partially extend below the gate, both ends of the gate are arranged on both regions, respectively. A part of the surface region of the source region 7 has an N ⁻ impurity concentration lower than that of the source region.
An area 10 is provided on which the lower end of the floating gate 3 on the source side is arranged.

Therefore, the floating gate 3 of the source region 7
The portion exposed to the substrate surface below is not located immediately below the lower end on the source side, but depends on the direction of the channel between the source / drain regions. The control gate 5 and the floating gate 3 are covered with an insulating film 6 such as a CVD silicon oxide film. When an erasing operation is performed using the nonvolatile memory of this reference example, when the electric field applied to the first gate insulating film 2 is increased by the potential difference between the floating gate 3 and the source electrode, the FN current is increased. The electrons flow and are drawn to the source 7 side. At this time, the depletion layer extends just below the lower end of the floating gate where the N ⁻ region 10 exists on the source side, and the resistance becomes high,
The FN current flows not in the gate end but in the source region 7 where the surface impurity concentration is high, as indicated by the arrow.
Therefore, the erase characteristics of this memory do not depend on the shape of the floating gate end.

In the first embodiment, in order to form the source region 7, ions of As and P are first implanted, and
A low-concentration impurity diffusion region 71 is formed outside the semiconductor region 7 to form a so-called LDD structure. However, this is provided to meet requirements such as securing a sufficient junction breakdown voltage, and is not always necessary. is not. For example, as in the second embodiment, an N ⁺ single layer made of only As may be used. At this time, the surface impurity profile becomes steep at the boundary with the channel, but basically shows a shape similar to FIG.
Further, in the above description, the impurity diffusion region is defined as N ⁺ ,
Although it is described as N ⁻ , this is not a limitation, and it is essential that the impurity concentration has a tendency profile as shown in FIG. 4 to realize the present invention. a do not request, N ⁺ and N ^- does not necessarily have to stick to the notation. This is the same in the following embodiments.

Next, a third reference example will be described with reference to FIG. The figure is a sectional view of a two-layer gate type nonvolatile memory. This example is characterized in that an N ⁻ region is also formed on the surface of the drain region. In the surface region of the P-type silicon semiconductor substrate 1, a source region 7 which is an N ⁺ impurity diffusion region is provided.
And a drain region 8, a first gate insulating film 2 made of a silicon oxide film and having a thickness of about 100A is formed on the region between the source / drain regions 7 and 8,
A floating gate 3 is formed thereon by a first layer of polysilicon. On this floating gate 3, a silicon oxide film /
A second silicon nitride / silicon oxide film stack
The gate insulating film 4 is formed, and the control gate 5 is formed thereon. The control gate 5 is made of a second polysilicon layer, on which a silicide film is deposited.
Since the source / drain regions 7, 8 partially extend below the gate, both ends of the gate are arranged on both regions, respectively. Control gate 5 and floating gate 3
Is covered with an insulating film 6 such as a CVD silicon oxide film. As in the first embodiment, outside the high-concentration source / drain region, low-concentration impurity diffusion regions 71 and 81 of the same conductivity type as this region are provided. An N ^- region 10 having a lower impurity concentration than that of the source region is provided in a part of the surface region of the source region 7 so that the lower end of the floating gate 3 on the source side is arranged above this region. I do.

Therefore, the floating gate 3 of the source region 7
The portion exposed to the substrate surface below is not located immediately below the lower end on the source side, but depends on the direction of the channel between the source / drain regions. Further, an impurity concentration lower than the drain region in a part of the surface region of the drain region 8 N ^- region 10 is provided, the floating gate over this area - so that the drain-side lower end of the bets 3 is arranged. Therefore, the portion of the drain region 8 which is below the floating gate 3 and is exposed on the substrate surface is not disposed immediately below the lower end on the drain side, but is formed in the channel between the source / drain regions. It depends on the direction. As described above, since the N ⁻ region 10 is formed in both the source / drain regions 7 and 8, the surface of the drain region below the floating gate 3 is also formed as shown in FIG. 4 (N ^{− to} N ⁺ To N ⁻ ). In this case, the N ^- regions 10 formed in the source / drain regions 7 and 8 are formed simultaneously using one resist pattern. According to this reference example, the erasing operation can be performed well even in the drain region.

By the way, in each of the above-mentioned reference examples, the L formed under reduced pressure is used instead of the post oxide film formed by thermal oxidation.
This is an example in which a P-CVD silicon oxide film 6 is deposited. For example, a CVD oxide film is used in order to meet the demand for lowering the temperature of the heat process and reducing the number of heat processes accompanying the miniaturization of semiconductor devices. In this case, the lower end portion of the floating gate (portion A in FIG. 13) is hardly oxidized, so that it does not have a rounded shape like B shown in FIG.

Next, a fourth embodiment will be described with reference to FIGS. These drawings show cross-sectional views of the manufacturing process of the nonvolatile memory. In the reference examples so far,
By setting the surface impurity concentration of the source / drain region immediately below the floating gate end low, a depletion layer is formed immediately below the floating gate end at the time of erasing, and electrons are formed at a portion where the concentration is higher than the channel. Has been pulled out. In this example, as a means to perform the operation of extracting electrons from the part beyond the channel,
A method of forming a depletion layer immediately below the end of the floating gate is not used. As in the first reference example, the P-type silicon semiconductor substrate 1
A source region 7 and a drain region 8 are formed in the surface region of FIG. 1. A first gate insulating film 2 is formed on the region between the source / drain regions, and a poly gate insulating film 2 is formed thereon. A floating gate 3 of silicon is formed. This floating gate 3
A second gate insulating film 4 is formed thereon.
A control gate 5 of polysilicon is formed. The control gate 5 has a silicide film deposited on polysilicon. The source / drain regions 7, 8 are partially gated.
Since both ends extend below the gate, both ends of the gate are respectively disposed on both regions. The control gate 5 and the floating gate 3 are covered with an insulating film 6 such as an LD-CVD silicon oxide film. As in the first embodiment, outside the high-concentration source / drain region, low-concentration impurity diffusion regions 71 and 81 of the same conductivity type as this region are provided.

Next, using a resist pattern 9 exposing a part of the source region 7 and a gate end portion thereon as a mask, for example, ion implantation of O ₂ at 20 keV and about 2 × 10 ¹⁸ cm ^{−2 is performed.} (FIG. 7). Thereafter, the semiconductor substrate 1 is heat-treated to convert the silicon in this region into a silicon oxide film 11 (FIG. 8). Oxygen ions are diffused to a portion below the gate by heat treatment, so that the silicon oxide film 1 is formed under the lower end on the source side of the floating gate 3 of the silicon semiconductor substrate.
1 is formed. Therefore, at the time of the erase operation, the FN current flows from the channel instead of the lower end of the floating gate 3 on the source side as shown by an arrow.

Next, an embodiment will be described with reference to FIGS. The figure is a cross-sectional view of the manufacturing process of the nonvolatile memory. A first gate insulating film 2 is formed on a P-type silicon semiconductor substrate 1 and a polysilicon floating gate is formed thereon.
3 is formed. On this floating gate 3, the second
A gate insulating film 4 is formed, and a polysilicon control gate 5 is formed thereon. The control gate 5 has a silicide film deposited on polysilicon. Next, the semiconductor substrate 1 including the control gate 5 and the floating gate 3
An insulating film 6 made of, for example, an LP-CVD oxide film or the like is deposited thereon at about 200 A (FIG. 9). Next, a part of the control gate 5 and the insulating film 6 in the region where the source region is to be formed are removed by etching using the resist pattern as a mask 9 by an anisotropic etching method such as RIE. And a region where the source region is to be formed is exposed. Then
A groove 12 is formed in a region where a source region is to be formed on the silicon substrate 1 exposed by the isotropic etching method (FIG. 10). Then, after removing the mask 9, using a new mask (not shown), for example, As is 35 keV, 1 × 10 ¹⁶
Ions are implanted at a dose of about cm ^-2 .

Subsequently, the exposed surfaces of the grooves 12 and the control gate 5 are heated in an oxidizing atmosphere to form a silicon oxide film 13.
Is formed inside the groove 12. From above, for example, P is 3
Ion implantation is performed at a dose of about 0 keV and about 2 × 10 ¹³ cm ⁻² . As the ^{N +} source - source region 7 is formed, the outside of N by P ^- region 71 is formed. The N ⁺ drain region 8 and the N ⁻ region 81 outside the N ⁺ drain region 8 are similarly formed on the drain side by these ion implantations. After this,
An insulating film 14 such as a silicon oxide film is deposited on the semiconductor substrate 1 including the groove 12 by, for example, low-pressure CVD (FIG. 11). In the present embodiment, the silicon oxide film 13 is formed just below the source-side lower end of the floating gate 3 of the silicon semiconductor substrate 1 as described above. Therefore, at the time of the erase operation, the FN current flows not in the lower end on the source side but in the N ⁺ region 7 from the channel. Therefore, also in the present embodiment, the erasing characteristic does not depend on the shape of the gate end, and the variation can be suppressed. Groove 12
The silicon oxide film 13 is formed by a thermal oxidation method in this embodiment, but may be formed by a low pressure CVD. According to this method, it is possible to integrally form the insulating film 14 deposited on the surface of the semiconductor substrate 1, and the process is shortened.
Also, if the number of heating steps increases, the end of the gate becomes rounded and obstructs the tendency to miniaturize the device. Therefore, this method is also advantageous in this sense.

In the above embodiment, the source region 7, the N ^- region 71 and the like are formed by forming the groove 12 and then diffusing impurities by ion implantation and thermal diffusion. In this case, groove 1
2 is already formed and the surface of the substrate is deformed, so that it is difficult to implant ions into a predetermined position.
Diffusion control down the surface is quite difficult. However, when forming the source region 7 and the like after forming the groove 12 in advance,
If the solid-phase diffusion method is used, it is possible to relatively accurately control the length of the source region and the like sunk under the gate.
It will be advantageous. When the groove 12 is formed after the source region 7 or the N ^- region 71 is formed, the length of diffusion under the gate must be accurately determined in advance using an ion implantation method, a solid phase diffusion method, or the like. Since it can be determined, the channel length is not shortened unnecessarily, which is useful for miniaturization of the semiconductor memory device. Although the present embodiment shows a case of extracting from the source, it is needless to say that a similar structure may be applied to the drain when extracting from the drain. In FIG. 8, oxygen is ion-implanted into the semiconductor substrate and a silicon oxide film is formed in that portion. However, hydrogen can be used instead of oxygen. In this case, a damage region for trapping charges is formed in the ion-implanted portion, but the above-described oxide film passing current does not flow in this region.

In the above embodiment, a P-type semiconductor substrate is used, and an N-type source / drain region is formed in this substrate. However, this is only an example, and a semiconductor substrate having another structure can be used in the present invention. For example, an N-type semiconductor substrate is used, and a P-type
An N-type or P-type semiconductor substrate formed with a P / S drain region and a P-well or N-well formed in the substrate can be used. However, an N-type source / drain region is provided in the P well, and a P-type source / drain region is provided in the N well.

[0034]

As described above, according to the present invention, there is provided a two-layer gate type non-volatile memory which suppresses erasing variation and has stable erasing characteristics without depending on the shape of the lower end of the floating gate on the source side. can do.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor memory device according to a first reference example.

FIG. 2 is a sectional view of a manufacturing process of the semiconductor memory device of the first reference example;

FIG. 3 is a sectional view of a manufacturing step of the semiconductor memory device of the first reference example;

FIG. 4 is a characteristic diagram showing a surface impurity concentration distribution of a source region of the semiconductor memory device of the present invention.

FIG. 5 is a sectional view of a semiconductor memory device according to a second reference example;

FIG. 6 is a sectional view of a semiconductor memory device according to a third reference example;

FIG. 7 is a sectional view of a manufacturing step of a semiconductor memory device according to a fourth reference example;

FIG. 8 is a sectional view of a manufacturing step of a semiconductor memory device according to a fourth reference example;

FIG. 9 is a sectional view of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention;

FIG. 10 is a sectional view of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention;

FIG. 11 is a sectional view of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention;

FIG. 12 is an enlarged sectional view of a diffusion region of the semiconductor memory device of the present invention.

FIG. 13 is a cross-sectional view of a conventional semiconductor memory device.

FIG. 14 is a cross-sectional view of a conventional semiconductor memory device.

FIG. 15 is a characteristic diagram showing a surface impurity concentration distribution in a source region of a conventional semiconductor memory device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 first gate insulating film 3 floating gate 4 second gate insulating film 5 control gate 6, 14 insulating film such as silicon oxide film 7 N ⁺ source region 8 N ⁺ drain region 9 photoresist 10, 71, 81 Low-concentration impurity diffusion region (N ⁻ region) 11, 13 Silicon oxide film 12 Groove

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] 1. A semiconductor substrate having a surface exposed on a semiconductor substrate.
Forming a drain region having an exposed surface on the semiconductor substrate; and forming a part of the source / drain region of the semiconductor substrate on a channel region between the source / drain regions. Forming a first gate insulating film; forming a floating gate on the first gate insulating film; and forming a second gate insulating film on the floating gate. Forming a control gate on the second gate insulating film; etching a predetermined region of the source region exposed to form a groove; A step of disposing at least a lower portion of the bottom of the groove on the source side, and a step of coating an inner surface of the groove with an insulating film.