JPH04364076A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable data erasing operation with a low source voltage by setting a threshold voltage, obtained when a voltage is applied to a control electrode under the condition that a charge accumulating electrode is electrically neutral, to a value higher than the predetermined value and is lower than the predetermined threshold voltage after accumulation of charges. CONSTITUTION:A threshold voltage obtained when a voltage is applied to a control electrode under the condition that a charge accumulation electrode is electrically neutral is set to a range higher than 0 volt and is lower than 1/2 the threshold voltage after accumulation of charges to the charge accumulation electrode. Thereby, a voltage to be applied to impurity region is lowered while data is erased. For the control of threshold voltage, a source region 8 of a memory cell is covered with a resist mask 9 and boron is implanted to the area which becomes a drain region. Moreover, arsenic is implanted to form a drain region 10. A threshold voltage of a memory cell can be controlled easily depending on the amount of impurity to be implanted to the drain region 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to nonvolatile semiconductor memory devices in which data can be electrically written or erased.
Erasable and programmable
e Read Only Memory: EEPRO
Regarding M).

0002

2. Description of the Related Art Conventionally, among semiconductor memory devices, an EEPR is used as one in which data can be electrically written and erased.
OM (nonvolatile semiconductor memory device) is known. Figure 1
4 is a conventional non-volatile semiconductor memory device (EEPROM)
FIG. 2 is a block diagram showing the overall configuration.

Referring to FIG. 14, a conventional EEPROM includes a memory cell array 30 in which a plurality of memory cells (not shown) for storing data are arranged in a matrix, and a memory cell array 30 for decoding address signals from the outside. It includes an X decoder 21 and a Y decoder 22, a Y gate 23, a control circuit 24, and an input/output circuit 25. X decoder 21, Y decoder 22, Y gate 23, control circuit 24,
The input/output circuit 25 and the memory cell array 30 are formed on the same substrate on the semiconductor chip 26. Conventional E
The EPROM further includes a power input terminal Vcc28 and a high voltage power input terminal VPP29.

FIG. 15 is a cross-sectional structural diagram showing memory cells (semiconductor storage elements) constituting the memory cell array shown in FIG. 14.

Referring to FIG. 15, the conventional memory cell is
Impurity concentration 1×1015/cm3, specific resistance 10Ω・c
P-type silicon semiconductor substrate 31 having characteristics of
The n+ type drain region 32 with an impurity concentration of 1 x 1020/cm3 was formed by ion implanting arsenic (As) under the conditions of 1 x 1020/cm3 of arsenic (As) ion implantation under the conditions of an acceleration voltage of 100 to 150 KV and a dose of 5 x 1015/cm2. (As)
An impurity concentration of 1× formed by ion implantation of
1020/cm3 of n+ source region 33 and n+
A channel region 34 formed between the type drain region 32 and the n+ type source region 33, a gate oxide film 35 with a thickness of 100 Å formed on the channel region 34, and a polygonal layer formed on the gate oxide film 35. A floating gate 36 made of a crystalline silicon layer and a floating gate 3
6 and a control gate 38 made of a polycrystalline silicon layer formed on the interlayer insulating film 37.

Next, data writing and erasing operations of a conventional EEPROM will be explained with reference to FIGS. 14 and 15.

To write data to a memory cell, first, 12.5V is applied to the high voltage power supply input terminal VPP29. 12.5V is supplied to the control gate 38 from this high voltage power supply input terminal VPP29. At the same time, n+
8V is supplied to the mold drain region 32 via a load resistor. On the other hand, the n+ type source region 33 is grounded and has a ground potential (GND). Under such conditions, electrons move from the n+ type source region 33 toward the n+ type drain region 32. The channel region 34 has a voltage of 0.5 to 1 mA.
A certain amount of current flows. At this time, the flowing electrons are n+
It is accelerated by the high electric field near the type drain region 32. As a result, the electrons obtain high energy that exceeds the energy barrier of 3.2 eV from the surface of the P-type silicon semiconductor substrate 31 to the gate oxide film 35. Electrons with this high energy are called hot electrons. A part of the hot electrons jumps over the barrier of the gate oxide film 35, is attracted to the high potential (12.5 V) of the control gate 38, and is injected into the floating gate 36. The floating gate 36 becomes electrically negative. This write state corresponds to data "0".

On the other hand, erasing data from memory cells is
As with writing, first set 12 to the high voltage power supply input terminal VPP29.
．． Apply 5V. 12.5V is supplied to the n+ type source region 33 from this high voltage power supply input terminal VPP29. The control gate 38 is grounded and has a ground potential (GN
D). The n+ type drain region 32 is placed in a floating state. Under such conditions, a high electric field is generated in the gate oxide film 35 between the floating gate 36 and the n+ type source region 33. This lowers the energy barrier of gate oxide film 35. The high potential (12.
5V) and electrons are emitted. A current called a tunnel current flows between the floating gate 36 and the n+ type source region 33. In other words, a predetermined amount of electrons are extracted from the floating gate 36, and this state corresponds to data "1".

[0009]

As described above, in the conventional EEPROM, a high voltage VPP (12.5 V) is applied to the n+ type source region 33 when erasing data. Therefore, the junction breakdown voltage of the n+ type source region 33 is V
It needs to be held higher than PP (12.5V) with a margin.

However, as semiconductor devices become more integrated and the elements become smaller, the well concentration becomes higher, the boron concentration in the channel cut becomes higher, and the temperature of the n+ region decreases due to the lower temperature of heat treatment. Phenomena such as impurity distribution becoming steep occur. As a result, it tends to be difficult to maintain a sufficiently high junction breakdown voltage. The reduction in junction breakdown voltage due to such integration causes the following problems.

[0011] That is, due to a decrease in junction breakdown voltage, leakage current during data erasing increases. Further, hot holes are generated due to avalanche breakdown, and the injection of these hot holes into the gate oxide film 35 significantly deteriorates the reliability of the gate oxide film 35.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a semiconductor memory device capable of erasing data with a low source voltage (voltage applied to an impurity region). shall be.

[0013]

[Means for Solving the Problems] A semiconductor memory device according to claim 1 includes a semiconductor substrate of a first conductivity type, and a second semiconductor memory device formed at a predetermined interval on the main surface of the semiconductor substrate of the first conductivity type. A pair of conductivity type impurity regions, a charge storage electrode formed between the pair of impurity regions with a first insulating film interposed therebetween, and a control electrode formed on the charge storage electrode with a second insulating film interposed therebetween. In a semiconductor memory device that has a charge storage electrode and electrically writes or erases data by storing charge in the charge storage electrode or extracting charge from the charge storage electrode, the charge storage electrode is electrically neutral. The threshold voltage when a voltage is applied to the control electrode in this state is set within a range of 0 volts or more and 1/2 or less of the threshold voltage after charge is accumulated in the charge storage electrode.

[0014]

[Operation] In the semiconductor memory device according to the present invention, when a voltage is applied to the control electrode with the charge storage electrode in an electrically neutral state, the threshold voltage is set to 0 volts or more, and the charge on the charge storage electrode is By setting the threshold voltage within a range of 1/2 or less of the threshold voltage after accumulation, the voltage to be applied to the impurity region when erasing data is reduced.

[0015]

[Examples] Examples of the present invention will be described below.

First, the background of the present invention will be explained. E
Let us consider the operation of erasing data written to memory cells in an EPROM.

The data erasing operation is performed by the Fawler-Nordheim tunnel effect phenomenon. The Fowler-Nordheim current is expressed by the following equation (1).

J=KE2exp[-4√2m*(eφB)
3/2 /3ehE] ... (1) J: tunnel current density K: Boltzmann constant E: electric field m
*: Effective mass e: Elementary electric field of electron h: Planck's constant φB: Barrier height Referring to equation (1), it can be seen that the tunneling current density J is extremely dependent on the electric field E applied to the oxide film.

Next, in the EEPROM, the state of writing (programming) data into the memory and the state of erasing data will be considered.

Normally, the threshold voltage Vth of a memory cell is set to about 8 V in a programmed state (written state) and about 1 to 2 V in an erased state. This is due to the following reasons.

That is, when reading data after data has been written, Vcc (~5V) is applied to the control gate, and data is determined based on whether it is greater or less than Vcc. Therefore, the threshold voltage Vth of the memory cell after writing data needs to be 5V or more. Also,
If the threshold voltage Vth of the memory cell becomes negative in a state where data has been erased, the memory cell transistor cannot be turned off. Therefore, the threshold voltage Vth of the memory cell in the erased state needs to be 0 volts or more.

[0022] Including the margin in the above constraints,
The threshold voltage after writing is set to 8V, and the threshold voltage after erasing is set to a value of 1 to 2V. Therefore, the threshold voltage Vth of the memory cell fluctuates (swings) by 6 to 7 V between the written state (programmed state) and the erased state. Due to such fluctuations in Vth, the voltage actually applied to the floating gate is determined by the capacitance division ratio between the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the semiconductor substrate. This capacity division ratio is approximately 0.5-0.6. Therefore, the variation (6 to 7 V) in the threshold voltage Vth of the memory cell is
From the perspective of the floating gate, this corresponds to a variation of 3-4V. That is, the voltage of the floating gate is between 3 and 4 in the data write state (program state) and erase state.
V changes.

Next, let us consider the phenomenon that occurs when actually erasing data. Normally, before performing an erase operation on a memory cell, data is always written in the memory cell. Therefore, a memory cell to be erased is always in a written state, that is, a state where Vth is high, regardless of the data content. The potential of the floating gate at this time is V
Let it be FP.

From this state, a high voltage VS is applied to the source region.
When applying (VS −VFP)/ to the tunnel oxide film,
A charge of tOX is applied. This causes the Fowler-Nordheim current described above to flow. As a result, electrons from the floating gate are extracted and data is erased. In the post-erasure state, as mentioned above, the potential of the floating gate increases by 3 to 4 V compared to the written state, and VF
Becomes E. Therefore, after the data erase operation is completed, the electric field applied to the tunnel oxide film is (VS - VFE)/tOX = (VS - VFP-4)
/tOX.

That is, the electric field applied to the oxide film is greatest at the beginning of the erase operation, and when the erase operation is completed, it has decreased by 4/tOX compared to the initial period of the erase operation. If we look at this phenomenon from the Fowler-Nordheim equation mentioned above, it can be seen that a large amount of current flows at the beginning of the erase operation, and the current decreases significantly when the erase operation is completed.

FIG. 1 is a diagram showing the relationship between the erase voltage application time and the threshold voltage Vth of a memory cell. Referring to FIG. 1, it can be seen that Vth rapidly decreases immediately after applying the voltage VS to the source region, and then gradually decreases. This is set to a preset erasing time (
For example, a predetermined Vth (1 to 2 V) within 10 msec).
In order to achieve this, it is necessary to set VS or VS /tOX to a certain value or more. That is, VS or V
The larger S /tOX is, the greater the force for extracting electrons becomes, and the erasing time becomes shorter.

Here, the threshold voltage of the memory cell when the floating gate is electrically neutral is Vth(N
). In addition, the threshold voltage after programming (after writing) is Vth (P), and the threshold voltage after erasing is Vth (P).
(E). When the floating gate potential VFP after writing and the floating gate potential VFE after erasing are expressed using these threshold voltages, the following equations (2) and (3) are obtained, respectively.

VFP={Vth(N)−Vth(P)}×R
…(2
) VFE={Vth(N)-Vth(E)}×R
…(
3) Here, R is the capacitive coupling ratio.

Next, consider the minimum electric field required to obtain a predetermined erase characteristic (erase speed). Assuming that this minimum electric field is Emin, the minimum source voltage VSmin required at that time is derived as follows.

Emin=(VSmin−VFP)/tOX

...(4) Emin = [VSmin-{Vt
h(N)-Vth(P)}×R]/tOX...(
5) VSmin=tOX・Emin +{Vth(
N)-Vth(P)}×R...(6) Here, since tOX, Emin, Vth(P) and R are constants, by reducing Vth(N),
VSmin can be lowered. The minimum value of Vth(N) is the threshold voltage Vth after erasing described above is Vth
In the same way that the threshold voltage Vth(N) in this neutral state must also be Vth(N)>0. In addition, the threshold voltage Vth (N) in the neutral state
The closer to 0 volts, the better, but after writing the data (
If the threshold voltage Vth(P) (after programming) is 1/2 or less, the effect of reducing the voltage applied to the source region during erasing can be obtained.

FIGS. 2 to 13 show a manufacturing process (first step to twelfth step) of a memory cell of a stacked gate flash EEPROM according to an embodiment of the present invention.
FIG. Next, the actual manufacturing process for controlling the threshold voltage described above will be explained with reference to FIGS. 2 to 13. First, as shown in FIG. 2, a P-type silicon semiconductor substrate with a specific resistance of about 10 Ωcm 1, boron (B) is implanted under the conditions of 100 KeV and 4×10 12 /cm 2 . Then, heat treatment is performed at 1150° C. for 6 hours to form a well (not shown).

Next, as shown in FIG. 3, boron (B) was applied to the region separating the active regions at 80 KeV and 2.5×101
Inject under conditions of 3/cm2. Then, a field oxide film 2 having a thickness of about 6000 Å is formed in this region using a selective oxidation method. The cross section taken along line A-A in the right-hand drawing shown in FIG. 3 is the drawing shown on the left-hand side.

Next, as shown in FIG. 4, ions are implanted into the active region in order to control the threshold voltage Vth of the memory cell. An oxide film 3 of about 100 Å is formed over the entire surface. A first polycrystalline silicon layer 4 is formed on the oxide film 3 at a thickness of 100 nm.
A thickness of about 0 Å is deposited. Using photolithography and anisotropic etching, the first polycrystalline silicon layer 4 is linearly patterned at a constant pitch in the column direction (vertical direction). That is, by performing anisotropic etching using the resist mask 7a, patterning is performed at a pitch as shown on the right side of FIG. After this, resist mask 7
Remove a.

Next, as shown in FIG. 5, an ON film 5 is formed on the first polycrystalline silicon layer 4. A second layer is formed on the ON film 5.
A polycrystalline silicon layer 6 with a thickness of about 2500 Å is formed. Resist mask 7b on second polycrystalline silicon layer 6
form.

Next, as shown in FIG. 6, the resist mask 7b is linearly patterned at a constant pitch in the row direction (lateral direction) using photolithography. Then, the second polycrystalline silicon layer 6, the underlying ON film 5, and the first polycrystalline silicon layer 4 are anisotropically etched using the resist mask 7b. Thus, the first polycrystalline silicon layer 4 forms the floating gate 4 and the second polycrystalline silicon layer 6 forms the control gate 6.

Next, as shown in FIG. 7, a region that will become the drain region of the memory cell is covered with a resist mask 7c. Using the resist mask 7c as a mask, phosphorus (P) ions are implanted into a region that will become a source region using an oblique rotational implantation method. Furthermore, by ion-implanting arsenic (As),
A source region 8 is formed.

Next, as shown in FIG. 8, the source region 8 of the memory cell is covered with a resist mask 9. Boron (B) ions are implanted into a region that will become a drain region using an oblique rotational implantation method. Furthermore, a drain region 10 is formed by ion-implanting arsenic (As). Depending on the amount of impurity (doping amount) implanted into this drain region 10,
The threshold voltage of a memory cell can be easily controlled.

Next, as shown in FIG. 9, an oxide film (not shown) is formed to a thickness of about 1500 Å. Sidewalls 11 are formed on the sidewall portions of floating gate 4 and control gate 6 using anisotropic etching.

Next, as shown in FIG. 10, an oxide film 12 is formed over the entire surface to a thickness of about 1500 Å. Further, a nitride film 13 is formed to a thickness of about 500 Å.

Next, as shown in FIG. 11, boron (B)
The interlayer film 14 is formed by forming an oxide film containing phosphorus (P) and phosphorus (P) to a thickness of approximately several thousand angstroms, and performing heat treatment and etching. A resist mask 15 is formed in a predetermined region on the interlayer film 14 using photolithography. By isotropically etching the interlayer film 14 using the resist mask 15, the interlayer film 14 having a tapered shape 17 in the opening 16 is formed. Thereafter, as shown in FIG. 12, an anisotropic etching is further performed using the resist mask 15 as a mask to form an opening above the drain region 10.

Finally, as shown in FIG. 13, titanium 18 is formed to a thickness of about 500 Å on the opened drain region 10 for electrical connection. Then, aluminum 19 is formed to a thickness of about 5000 Å. Bit lines (18, 19) in contact with the drain region 10 are formed by patterning the laminated film of titanium 18 and aluminum 19 using photolithography and chemical processing.

In the above embodiment, ion implantation was performed before forming the polycrystalline silicon layer 4 in the manufacturing process explained in FIG. 4, but the present invention is not limited to this. The threshold value of the memory cell can also be controlled by performing boron (B) implantation at higher energy.

[0043]

According to the invention as claimed in claim 1, when a voltage is applied to the control electrode when the charge storage electrode is electrically neutral, the threshold voltage to the charge storage electrode is set to 0 volts or more. By setting the threshold voltage within the range of 1/2 or less of the threshold voltage after charge accumulation, the voltage to be applied to the impurity region when erasing data is reduced. It has now become possible to provide a semiconductor memory device that can perform voltage erasing operation using voltage.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the relationship between erase voltage application time and threshold voltage Vth of a memory cell.

FIG. 2 is a cross-sectional view showing a first step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a second step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a third step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a fourth step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a fifth step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the sixth step of the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a seventh step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the eighth step of the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the ninth step of the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a tenth step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view showing an eleventh step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a twelfth step in the manufacturing process of a stacked gate flash EEPROM memory cell according to an embodiment of the present invention.

FIG. 14: Conventional non-volatile semiconductor memory device (EEPRO)
It is a block diagram showing the whole structure of M).

15 is a cross-sectional structural diagram showing a memory cell (semiconductor storage element) constituting the memory cell array shown in FIG. 14. FIG.

[Explanation of symbols]

1: P-type silicon semiconductor substrate 2: Field oxide film 3: Oxide film 4: First polycrystalline silicon layer (floating gate)
5: ON film 6: Second polycrystalline silicon layer (control gate) 8
: Source region 10 : Drain region 18 : Titanium 19 : Aluminum Note that in each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type;
A pair of impurity regions of a second conductivity type formed at a predetermined distance on the main surface of a semiconductor substrate of a conductivity type, and a charge formed between the pair of impurity regions with a first insulating film interposed therebetween. comprising a storage electrode and a control electrode formed on the charge storage electrode via a second insulating film, and storing charge in the charge storage electrode or extracting charge from the charge storage electrode. In a semiconductor memory device in which data is electrically written or erased by a semiconductor memory device, the threshold voltage when a voltage is applied to the control electrode while the charge storage electrode is electrically neutral is 0 volt or more. , a semiconductor memory device characterized in that the threshold voltage is set within a range of 1/2 or less of the threshold voltage after charge is accumulated in the charge storage electrode.