JP2886193B2 - Semiconductor wafer exposure method - Google Patents

Semiconductor wafer exposure method

Info

Publication number
JP2886193B2
JP2886193B2 JP22039089A JP22039089A JP2886193B2 JP 2886193 B2 JP2886193 B2 JP 2886193B2 JP 22039089 A JP22039089 A JP 22039089A JP 22039089 A JP22039089 A JP 22039089A JP 2886193 B2 JP2886193 B2 JP 2886193B2
Authority
JP
Japan
Prior art keywords
semiconductor wafer
wafer
semiconductor
exposed
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP22039089A
Other languages
Japanese (ja)
Other versions
JPH0384921A (en
Inventor
智昭 坪香
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22039089A priority Critical patent/JP2886193B2/en
Publication of JPH0384921A publication Critical patent/JPH0384921A/en
Application granted granted Critical
Publication of JP2886193B2 publication Critical patent/JP2886193B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造工程において用いられる
半導体ウェハの露光方法に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for exposing a semiconductor wafer used in a semiconductor device manufacturing process.

〔従来の技術〕[Conventional technology]

半導体装置の製造工程においては、一般に薄い円板状
の半導体ウェハ上に多数個の半導体チップを作り付け、
ホトリソグラフィー、エッチング、イオン打込み等の各
種工程が一括して行われる。
In the process of manufacturing semiconductor devices, generally, a large number of semiconductor chips are formed on a thin disk-shaped semiconductor wafer,
Various processes such as photolithography, etching, and ion implantation are collectively performed.

なお、露光装置は例えは、「電子材料別冊、超LSI製
造・試験装置、ガイドブック」97〜104頁、「光露光装
置」、1984年工業調査会発行、で知られている。
The exposure apparatus is known, for example, in "Electronic Materials Separate Volume, Ultra LSI Manufacturing / Testing Equipment, Guidebook", pp. 97-104, "Light Exposure Equipment", published by the Industrial Research Institute in 1984.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

円形の半導体ウェハ上に多数個の矩形の半導体チップ
を形成するので、ウェハの周縁部に階段状の不要な領域
(以下、不要領域と称す)が存在する。従って、ホトリ
ソグラフィー技術を用いてパターンを形成するとき、ホ
トレジストはウェハ全面に塗布されるのでこの不要領域
にもホトレジストが塗布され、しかもこの不要領域は露
光されないので、ホトレジストがポジ型の場合ホトレジ
ストがそのまま残存し、後のドライエッチング工程やイ
オン打込み工程等においてウェハ周縁部を保持する際、
ホトレジストが剥がれて異物となり、この異物に起因し
て半導体素子の性能が低下したり、歩留りが低下する問
題があった。
Since a large number of rectangular semiconductor chips are formed on a circular semiconductor wafer, a step-like unnecessary region (hereinafter, referred to as an unnecessary region) exists at a peripheral portion of the wafer. Therefore, when a pattern is formed by using the photolithography technique, the photoresist is applied to the entire surface of the wafer, so that the unnecessary area is also coated with the photoresist, and the unnecessary area is not exposed. It remains as it is, and when holding the peripheral portion of the wafer in a later dry etching step, ion implantation step, or the like,
The photoresist is peeled off to form foreign matter, which causes a problem that the performance of the semiconductor element is reduced or the yield is reduced.

本発明の目的は、このような異物の発生を防止できる
半導体ウェハの露光方法を提供することにある。
An object of the present invention is to provide a method for exposing a semiconductor wafer, which can prevent the generation of such foreign matter.

〔課題を解決するための手段〕[Means for solving the problem]

上記の課題を解決するために、本発明の半導体ウェハ
の露光方法は、露光用光源の光で、ホトレジストが塗布
された半導体ウェハを露光する方法において、上記半導
体ウェハの露光される面を回転させる工程と、上記露光
用光源の光を照射するレンズを上記半導体ウェハの露光
される面と平行に2次元的に移動させる工程と、上記露
光用光源と上記レンズとの間に設けたシャッタで上記半
導体ウェハの半導体素子が形成される領域を除く不要領
域を、上記半導体素子が形成される領域と上記不要領域
との境界に沿う形状に選択的に露光する工程を有するこ
とを特徴とする。
In order to solve the above-mentioned problems, a method of exposing a semiconductor wafer according to the present invention is a method of exposing a semiconductor wafer coated with photoresist with light from an exposure light source, wherein the exposed surface of the semiconductor wafer is rotated. A step of two-dimensionally moving a lens for irradiating the light of the exposure light source in parallel with a surface to be exposed of the semiconductor wafer, and a step of using a shutter provided between the exposure light source and the lens. And a step of selectively exposing an unnecessary region excluding a region where the semiconductor element is formed on the semiconductor wafer to a shape along a boundary between the region where the semiconductor element is formed and the unnecessary region.

〔作用〕[Action]

本発明では、ホトレジストが塗布された半導体ウェハ
の半導体素子が形成される領域を除く不要領域を、上記
半導体素子が形成される領域と上記不要領域との境界に
沿う形状に選択的に露光することにより、不要領域のホ
トレジストを除去でき、ウェハ周縁部を保持しても異物
が発生しない。
In the present invention, an unnecessary region excluding a region where a semiconductor element is formed on a semiconductor wafer coated with a photoresist is selectively exposed to a shape along a boundary between the region where the semiconductor element is formed and the unnecessary region. Accordingly, the photoresist in the unnecessary area can be removed, and no foreign matter is generated even if the peripheral portion of the wafer is held.

〔実施例〕〔Example〕

第1図は、本発明の参考例の半導体製造装置を示す概
略図、第3図は、半導体ウェハの概略平面図である。
FIG. 1 is a schematic view showing a semiconductor manufacturing apparatus according to a reference example of the present invention, and FIG. 3 is a schematic plan view of a semiconductor wafer.

第1図で、1は回転ステージ、2は半導体ウェハ、3
はHgランプ等の光源、4はレンズ、5はマスク、6はモ
ータである。第3図で、7は半導体ウェハ2の向きを知
るためのオリエンテーションフラット部(以下、オリフ
ラ部と記す)、8は半導体チップ(素子部)、9は階段
状の不要領域(実際はチップ8の数がもっと多いので、
不要領域9はもっと段数が多い)、10は半導体ウェハ2
を識別するためのマークである。
In FIG. 1, 1 is a rotary stage, 2 is a semiconductor wafer, 3
Denotes a light source such as an Hg lamp, 4 denotes a lens, 5 denotes a mask, and 6 denotes a motor. In FIG. 3, reference numeral 7 denotes an orientation flat portion (hereinafter referred to as an orientation flat portion) for knowing the direction of the semiconductor wafer 2, 8 denotes a semiconductor chip (element portion), and 9 denotes a step-like unnecessary area (actually, the number of chips 8). Because there are more
Unnecessary area 9 has more steps), 10 is semiconductor wafer 2
Is a mark for identifying.

ポジ型ホトレジストが塗布された半導体ウェハ2が回
転ステージ1上に吸着保持されている。ウェハ2の不要
領域9に、光源3からの光がレンズ4を介して導かれ、
マスク5を通して照射される。マスク5はモータ6によ
り回転し、マスク5に形成されたパターン(第3図の不
要領域9を露光するための階段状のパターンおよび識別
用マーク10のパターン)によりウェハ2の周縁部が露光
される。
A semiconductor wafer 2 coated with a positive photoresist is held on a rotary stage 1 by suction. Light from the light source 3 is guided to the unnecessary area 9 of the wafer 2 via the lens 4,
Irradiation is performed through the mask 5. The mask 5 is rotated by a motor 6, and the periphery of the wafer 2 is exposed by a pattern formed on the mask 5 (a stepped pattern for exposing the unnecessary area 9 and a pattern of the identification mark 10 in FIG. 3). You.

第2図は、本発明の半導体ウェハの露光方法に用いる
半導体製造装置の一実施例を示す概略図である。
FIG. 2 is a schematic view showing one embodiment of a semiconductor manufacturing apparatus used for the method of exposing a semiconductor wafer according to the present invention.

第1図と同様の回転ステージ1およびウェハ2に対し
て、矢印方向に駆動するシャッタ13により処理された光
源3からの光がレンズ4、光ファイバ12およびレンズ11
を介してウェハ2の周縁部に照射される。このとき、レ
ンズ11がウェハ2の周縁部の上方で矢印方向に駆動する
ことにより、ウェハ2の周縁部を選択的に露光できる。
The light from the light source 3 processed by the shutter 13 driven in the direction of the arrow is applied to the lens 4, the optical fiber 12 and the lens 11 with respect to the rotary stage 1 and the wafer 2 similar to FIG.
Is irradiated to the peripheral portion of the wafer 2 via the. At this time, the peripheral edge of the wafer 2 can be selectively exposed by driving the lens 11 in the direction of the arrow above the peripheral edge of the wafer 2.

第1図および第2図に示した装置により露光された半
導体ウェハの一例を第3図に示す。素子部すなわち半導
体チップ8の外側の階段状の不要領域9が露光され、オ
リフラ部7には識別用マーク10が露光されている。この
半導体ウェハ2を現像することにより、不要領域9のホ
トレジストが除去され、かつオリフラ部7に識別用マー
ク10が形成される。すなわち、半導体ウェハ2の周縁部
のホトレジストを除去できるので、後の工程、例えばエ
ッチング工程においてエッチング速度のウェハ内の均一
性が向上し、ウェハ周縁部を接触して保持する機構によ
りホトレジストが剥がれて異物が発生するのを抑制でき
る。従って、素子の性能向上および歩留りの向上が図れ
る。また、識別用マーク10を同時に形成できるので、製
品の管理の効率が向上する。
FIG. 3 shows an example of a semiconductor wafer exposed by the apparatus shown in FIGS. The element portion, that is, the step-like unnecessary area 9 outside the semiconductor chip 8 is exposed, and the orientation mark 7 is exposed on the orientation flat portion 7. By developing the semiconductor wafer 2, the photoresist in the unnecessary area 9 is removed, and the identification mark 10 is formed on the orientation flat section 7. That is, since the photoresist at the peripheral portion of the semiconductor wafer 2 can be removed, the uniformity of the etching rate in the wafer in a later step, for example, an etching step is improved, and the photoresist is peeled off by a mechanism that contacts and holds the wafer peripheral portion. The generation of foreign matter can be suppressed. Therefore, the performance of the element and the yield can be improved. Further, since the identification mark 10 can be formed at the same time, the efficiency of product management is improved.

第1図の参考例では、ウェハ2を回転させ、かつ所定
のパターンを形成したマスク5を機械的に駆動してウェ
ハ2の周縁部を選択的に露光した。また、第2図の実施
例では、ウェハ2を回転させ、かつシャッタ13により処
理された光を照射するレンズ11を駆動してウェハ2の周
縁部を選択的に露光した。しかし、第2図の構成は例示
であり、本発明はこれらに限定されない。例えば、第3
図に示すように、ウェハの周縁部を必ずしも階段状に露
光しなくてもよく、少なくとも後の工程で保持する部分
を露光すればよい。
In the reference example shown in FIG. 1, the wafer 2 is rotated, and the mask 5 on which a predetermined pattern is formed is mechanically driven to selectively expose the periphery of the wafer 2. In the embodiment shown in FIG. 2, the wafer 2 is rotated, and the lens 11 for irradiating the light processed by the shutter 13 is driven to selectively expose the periphery of the wafer 2. However, the configuration in FIG. 2 is an exemplification, and the present invention is not limited to these. For example, the third
As shown in the figure, the peripheral portion of the wafer does not necessarily need to be exposed in a stepwise manner, and at least a portion to be held in a later step may be exposed.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明の半導体ウェハの露光方
法では、半導体ウェハの周縁部のホトレジストを除去で
きるので、後の工程によりホトレジストが剥がれて異物
が発生するのを抑制できる。従って、素子の性能向上お
よび歩留りの向上が図れる。また、ウェハ識別用マーク
を形成できるので、製品の管理の効率が向上できる。
As described above, in the method for exposing a semiconductor wafer according to the present invention, the photoresist at the peripheral portion of the semiconductor wafer can be removed, so that it is possible to prevent the photoresist from peeling off in a later step to generate foreign matter. Therefore, the performance of the element and the yield can be improved. Further, since the wafer identification mark can be formed, the efficiency of product management can be improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図は、本発明の参考例の半導体製造装置を示す概略
図、第2図は、本発明の半導体ウェハの露光方法に用い
る半導体製造装置の一実施例を示す概略図、第3図は、
本発明の方法により露光された半導体ウェハの概略平面
図である。 1……回転ステージ 2……半導体ウェハ 3……光源 4……レンズ 5……マスク 6……モータ 7……オリフラ部 8……半導体チップ(素子部) 9……階段状の不要領域 10……半導体ウェハの識別用マーク 11……レンズ 12……光ファイバ 13……シャッタ
FIG. 1 is a schematic view showing a semiconductor manufacturing apparatus according to a reference example of the present invention, FIG. 2 is a schematic view showing one embodiment of a semiconductor manufacturing apparatus used for a semiconductor wafer exposure method of the present invention, and FIG. ,
1 is a schematic plan view of a semiconductor wafer exposed by the method of the present invention. DESCRIPTION OF SYMBOLS 1 ... Rotary stage 2 ... Semiconductor wafer 3 ... Light source 4 ... Lens 5 ... Mask 6 ... Motor 7 ... Orientation flat part 8 ... Semiconductor chip (element part) 9 ... Unnecessary step-like area 10 ... … Semiconductor wafer identification mark 11 …… Lens 12 …… Optical fiber 13 …… Shutter

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】露光用光源の光で、ホトレジストが塗布さ
れた半導体ウェハを露光する方法において、上記半導体
ウェハの露光される面を回転させる工程と、上記露光用
光源の光を照射するレンズを上記半導体ウェハの露光さ
れる面と平行に2次元的に移動させる工程と、上記露光
用光源と上記レンズとの間に設けたシャッタで上記半導
体ウェハの半導体素子が形成される領域を除く不要領域
を、上記半導体素子が形成される領域と上記不要領域と
の境界に沿う形状に選択的に露光する工程を有すること
を特徴とする半導体ウェハの露光方法。
1. A method of exposing a semiconductor wafer coated with a photoresist with light from an exposure light source, the method comprising: rotating a surface of the semiconductor wafer to be exposed; A step of two-dimensionally moving the semiconductor wafer in parallel with a surface to be exposed, and an unnecessary area excluding an area where semiconductor elements of the semiconductor wafer are formed by a shutter provided between the exposure light source and the lens. Selectively exposing the semiconductor wafer to a shape along a boundary between a region where the semiconductor element is formed and the unnecessary region.
JP22039089A 1989-08-29 1989-08-29 Semiconductor wafer exposure method Expired - Lifetime JP2886193B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22039089A JP2886193B2 (en) 1989-08-29 1989-08-29 Semiconductor wafer exposure method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22039089A JP2886193B2 (en) 1989-08-29 1989-08-29 Semiconductor wafer exposure method

Publications (2)

Publication Number Publication Date
JPH0384921A JPH0384921A (en) 1991-04-10
JP2886193B2 true JP2886193B2 (en) 1999-04-26

Family

ID=16750369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22039089A Expired - Lifetime JP2886193B2 (en) 1989-08-29 1989-08-29 Semiconductor wafer exposure method

Country Status (1)

Country Link
JP (1) JP2886193B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3439932B2 (en) * 1996-10-28 2003-08-25 大日本スクリーン製造株式会社 Peripheral exposure equipment
JP3383169B2 (en) * 1996-10-28 2003-03-04 大日本スクリーン製造株式会社 Peripheral exposure equipment
US5960305A (en) * 1996-12-23 1999-09-28 Lsi Logic Corporation Method to improve uniformity/planarity on the edge die and also remove the tungsten stringers from wafer chemi-mechanical polishing
JP3313628B2 (en) 1997-10-20 2002-08-12 富士通株式会社 Method for manufacturing semiconductor device
EP2039257A1 (en) 2007-09-19 2009-03-25 Circle Tekko Co., Ltd. Agricultural product peeling apparatus

Also Published As

Publication number Publication date
JPH0384921A (en) 1991-04-10

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