JP2880825B2 - Semiconductor element mounting method - Google Patents
Semiconductor element mounting methodInfo
- Publication number
- JP2880825B2 JP2880825B2 JP3158274A JP15827491A JP2880825B2 JP 2880825 B2 JP2880825 B2 JP 2880825B2 JP 3158274 A JP3158274 A JP 3158274A JP 15827491 A JP15827491 A JP 15827491A JP 2880825 B2 JP2880825 B2 JP 2880825B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- melting point
- point metal
- low melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子の接続・実装
方法に係り、特にフリップチップ型の半導体素子を回路
基板面にフェイスダウンにより接続・実装する実装方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of connecting and mounting a semiconductor device, and more particularly to a method of connecting and mounting a flip-chip type semiconductor device face down on a circuit board surface.
【０００２】[0002]
【従来の技術】半導体素子の高密度実装ないし簡易な実
装手段として、いわゆるフリップチップ型半導体素子
を、所定の回路（配線）基板面にフェイスダウンボンデ
ィングすることが知られている。2. Description of the Related Art As a means for high-density mounting or simple mounting of semiconductor elements, it is known that a so-called flip-chip type semiconductor element is face-down bonded to a predetermined circuit (wiring) substrate surface.
【０００３】図６はこのようなフェイスダウンによる接
続・実装の実施態様を模式的示す断面図であり、先ずフ
リップチップ型半導体素子１の能動面に設けられている
入出力電極端子２面上、もしくは回路基板３面に設けら
れている対応する接続パッド４面上に、たとえばPb-Sn
合金（半田）のような低融点金属により接続用バンプ５
を形成し、この接続用バンプ５が半導体素子１の電極端
子２もしくは回路基板３の接続パッド４に当接するよう
に、半導体素子１と回路基板３とを位置合せして対向配
置する（フェイスダウンに配置する）。次いで、前記接
続用バンプ５を構成する低融点金属をリフローさせるこ
とにより、半導体素子１の電極端子２と回路基板３面の
接続パッド４とを接合し電気的に接続することによって
行われている。なお、図６において、６は半導体素子１
の能動面の保護安定化のために、電極端子２以外の部分
を覆うように形成されたパッシベーション膜、７は回路
基板３主面の接続パッド４以外の部分に被覆形成された
ソルダーレジスト層、８はバリアメタル層をそれぞれ示
す。FIG. 6 is a cross-sectional view schematically showing an embodiment of such a face-down connection / mounting. First, an input / output electrode terminal 2 provided on an active surface of a flip-chip type semiconductor device 1 is provided. Alternatively, for example, Pb-Sn is formed on the surface of the corresponding connection pad 4 provided on the surface of the circuit board 3.
Connection bump 5 made of low melting point metal such as alloy (solder)
The semiconductor element 1 and the circuit board 3 are aligned and opposed to each other such that the connection bumps 5 are in contact with the electrode terminals 2 of the semiconductor element 1 or the connection pads 4 of the circuit board 3 (face down). To place it). Next, the low melting point metal forming the connection bumps 5 is reflowed so that the electrode terminals 2 of the semiconductor element 1 and the connection pads 4 on the surface of the circuit board 3 are joined and electrically connected. . In FIG. 6, reference numeral 6 denotes the semiconductor element 1
A passivation film formed so as to cover portions other than the electrode terminals 2 for protection and stabilization of the active surface, a solder resist layer 7 formed so as to cover portions other than the connection pads 4 on the main surface of the circuit board 3, Reference numeral 8 denotes a barrier metal layer.
【０００４】また、図７は他のフェイスダウンによる接
続・実装の実施態様を模式的示す断面図であり、半導体
素子１の電極端子２面上に形成された金などの突起電極
９を、回路基板３の接続パッド４面に位置合わせして当
接するとともに、、半導体素子１と回路基板３との隙間
に光硬化性樹脂10などを充填して硬化させ、この樹脂の
硬化、収縮作用を利用して、突起電極９と回路基板面側
の接続パッド４とを圧着接続する方法も行われている。
この場合は、半導体素子１と回路基板３との熱膨脹率の
差により生じる応力が、光硬化性樹脂10層に吸収され緩
和されるので、接合部に大きな応力が生じないという利
点がある。FIG. 7 is a cross-sectional view schematically showing another embodiment of connection / mounting by face-down, in which a protruding electrode 9 such as gold formed on the surface of the electrode terminal 2 of the semiconductor element 1 is connected to a circuit. In addition to aligning and contacting the surface of the connection pad 4 of the substrate 3, the space between the semiconductor element 1 and the circuit board 3 is filled with a photocurable resin 10 and cured, and the curing and shrinking action of the resin is used. Then, a method of crimping connection between the protruding electrode 9 and the connection pad 4 on the circuit board surface side is also performed.
In this case, the stress caused by the difference in the coefficient of thermal expansion between the semiconductor element 1 and the circuit board 3 is absorbed by the photocurable resin layer 10 and relaxed, so that there is an advantage that no large stress is generated at the joint.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記し
た半導体素子の接続・実装方法のうち、図６に示した低
融点金属の接続用バンプ５を用いる場合は、低融点金属
をリフローさせて半導体素子１の電極端子２と回路基板
３の接続パッド４とを接合する際、もしくは半導体素子
実働期間中に、接続用バンプ５の表面（側周面）が酸化
され、この酸化によって接続部の信頼性が低下するとい
う問題があった。また、前記接続用バンプ５は、比較的
多量の低融点金属で構成され、かつ半導体素子１と回路
基板３との中間部で外側に膨らんだ鼓形の形状となるた
め、特に隣接する電極端子２間の距離が短い狭ピッチの
半導体素子１を実装する場合には、マウンタによる位置
合わせの際の位置ズレやリフロー条件の不定が原因とな
り、電極端子２間で低融点金属によるブリッジが発生し
易いという問題がある。However, in the connection / mounting method of the semiconductor element described above, when the connection bump 5 of the low melting point metal shown in FIG. 6 is used, the low melting point metal is reflowed and the semiconductor element is reflowed. The surface (side peripheral surface) of the connection bump 5 is oxidized when the electrode terminal 2 is bonded to the connection pad 4 of the circuit board 3 or during the active period of the semiconductor element. However, there was a problem that was reduced. Further, since the connection bumps 5 are made of a relatively large amount of low melting point metal and have a drum-shaped shape which swells outward at an intermediate portion between the semiconductor element 1 and the circuit board 3, particularly the adjacent electrode terminals are provided. When mounting the semiconductor element 1 having a short pitch with a short distance between the electrodes 2, a bridge due to a low melting point metal occurs between the electrode terminals 2 due to a positional shift at the time of alignment by the mounter and an uncertain reflow condition. There is a problem that it is easy.
【０００６】さらに、図６に示す実施態様の場合は、半
導体素子１の実装高さである回路基板３との隙間が、接
続用バンプ５を構成する低融点金属の量とその種類組成
に依存する表面張力の大きさ、および電極端子２の面積
などで決定されるため、このような制御が重要な因子と
なり、如何に行うかがプロセス上および設計上の大きな
制約となっている。しかも、機械的接合強度の見地か
ら、前記半導体素子１の実装高さ、すなわち半導体素子
１と回路基板３との距離をあまり大きく設定することも
できない。Further, in the case of the embodiment shown in FIG. 6, the gap between the semiconductor element 1 and the circuit board 3, which is the mounting height, depends on the amount of the low-melting point metal constituting the connection bump 5 and its type composition. Such control is an important factor because it is determined by the magnitude of the surface tension to be applied, the area of the electrode terminal 2, and the like, and how to perform such control is a great limitation in process and design. In addition, from the viewpoint of mechanical bonding strength, the mounting height of the semiconductor element 1, that is, the distance between the semiconductor element 1 and the circuit board 3 cannot be set too large.
【０００７】一方、図７に示す光硬化性樹脂10などを用
いて圧着する場合は、半導体素子１と回路基板３との接
続が、光硬化性樹脂10層と半導体素子１表面との間の接
着、および光硬化性樹脂10層と回路基板３表面との間の
接着のみによって形成されているため、十分な機械的接
着強度が得られないという問題があった。On the other hand, when pressure bonding is performed using the photocurable resin 10 shown in FIG. 7, the connection between the semiconductor element 1 and the circuit board 3 is established between the photocurable resin 10 layer and the surface of the semiconductor element 1. Since it is formed only by bonding and bonding between the 10 layers of the photocurable resin and the surface of the circuit board 3, there is a problem that a sufficient mechanical bonding strength cannot be obtained.
【０００８】本発明はこれらの問題を解決するためにな
されたもので、半導体素子のフェイスダウンによる接続
・実装において、小型、高機能化に伴う半導体素子の電
極端子間距離の狭小化に対応して、接続強度が高く、か
つ高い信頼性を有する接続部の形成が可能な半導体素子
の実装方法の提供を目的とする。The present invention has been made to solve these problems. In connection / mounting of a semiconductor device by face-down, the distance between the electrode terminals of the semiconductor device has been reduced due to the miniaturization and higher functionality. Accordingly, it is an object of the present invention to provide a method for mounting a semiconductor element capable of forming a connection portion having high connection strength and high reliability.
【０００９】[0009]
【課題を解決するための手段】本発明に係る半導体素子
の実装方法は、回路基板面に設けられている接続パッド
に、半導体素子の入出力電極端子を位置合せしフェイス
ダウンに接続・実装する方法において、前記回路基板面
の接続パッドが突起状に形成され、半導体素子の入出力
電極端子面側が前記接続パッドの突起が嵌合可能な縦断
面凹型に形成されかつ凹部に低融点金属を介在させ、こ
の低融点金属をリフローさせて半導体素子を回路基板面
にフェイスダウンに接続・実装することを特徴とする。According to a method of mounting a semiconductor device according to the present invention, input / output electrode terminals of the semiconductor device are aligned with connection pads provided on a circuit board surface, and the semiconductor device is connected and mounted face down. In the method, a connection pad on the circuit board surface is formed in a protruding shape, an input / output electrode terminal surface side of the semiconductor element is formed in a vertical cross-section concave shape into which the protrusion of the connection pad can be fitted, and a low melting point metal is interposed in the concave portion. The low melting point metal is reflowed to connect and mount the semiconductor element face down on the circuit board surface.
【００１０】本発明において、半導体素子の入出力電極
端子面側を前記接続パッドの突起が嵌合可能に縦断面凹
型化する手段としては、たとえば電極端子面上にめっき
などの方法でリング状の金突起部を形成するか、あるい
は半導体素子の電極端子面を除いてポリイミド樹脂やガ
ラスのような低融点金属に対する濡れ性のない耐熱材料
で、厚さ20μm 程度以上の被覆層を形成することになさ
れる。一方、回路基板面の接続パッドの突起状は、前記
電極端子面の凹部の構成などにも左右されるが、要する
に凹部に嵌合可能であればよく、たとえば円柱状もしく
は縦断面凸型であってもよい。In the present invention, the means for making the input / output electrode terminal side of the semiconductor element into a longitudinal cross-sectional concave shape so that the projection of the connection pad can be fitted is, for example, a method of forming a ring on the electrode terminal surface by plating or the like. To form a gold protrusion or to form a coating layer with a thickness of about 20 μm or more with a heat-resistant material such as polyimide resin or glass that has no wettability to low-melting metals except for the electrode terminal surface of the semiconductor element. Done. On the other hand, the shape of the projection of the connection pad on the circuit board surface depends on the configuration of the recess on the electrode terminal surface, but it is only necessary to be able to fit into the recess. You may.
【００１１】[0011]
【作用】本発明に係る半導体素子の実装方法において
は、半導体素子の入出力電極端子面を凹面化するかある
いは入出力電極端子面を囲繞する突堤が形成されてお
り、この凹部に半田などの低融点金属粒子などが貯留さ
れる形を呈する。しかして、このような半導体素子と回
路基板とは、半導体素子の電極端子面の凹部内に回路基
板面の接続パッド（突起状）が嵌合するように位置合わ
せされ、リフロー炉などを通されて半導体素子の電極端
子面の凹部内に貯留された低融点金属がリフローされ、
溶融した低融点金属で充填され、この低融点金属層を介
して強固な接合がなされる。しかも、電極端子の周りに
突堤が形成されており、低融点金属がこの突堤の外側へ
流れ出すことがないので、ブリッジなどの接続不良が生
じない。さらに、回路基板面に形成される金、銅などか
ら成る接続パッドの突起部の高さの調整で、半導体素子
と回路基板との間隔も任意に設定できる。特に半導体素
子の電極端子面上に金突起部をリング状形成した場合
は、リフローの際にこの金突起部が低融点金属の外周面
（側周面）を覆うので、表面の酸化が効果的に防止さ
れ、信頼性の高い接続部の形成が可能である。In the method of mounting a semiconductor device according to the present invention, the input / output electrode terminal surface of the semiconductor device is made concave or a jetty surrounding the input / output electrode terminal surface is formed. It has a form in which low melting point metal particles and the like are stored. The semiconductor element and the circuit board are positioned so that the connection pads (projections) on the circuit board fit into the recesses on the electrode terminal surfaces of the semiconductor element, and are passed through a reflow furnace or the like. The low melting point metal stored in the concave portion of the electrode terminal surface of the semiconductor element is reflowed,
It is filled with the molten low melting point metal, and strong bonding is performed via this low melting point metal layer. In addition, since a jetty is formed around the electrode terminal and the low melting point metal does not flow out of the jetty, a connection failure such as a bridge does not occur. Further, the distance between the semiconductor element and the circuit board can be arbitrarily set by adjusting the height of the projection of the connection pad made of gold, copper, or the like formed on the circuit board surface. In particular, when a gold protrusion is formed in a ring shape on the electrode terminal surface of a semiconductor element, the gold protrusion covers the outer peripheral surface (side peripheral surface) of the low melting point metal during reflow, so oxidation of the surface is effective. And a highly reliable connection portion can be formed.
【００１２】[0012]
【実施例】以下図１〜図５を参照して本発明の実施例を
説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.
【００１３】図１〜図３は、本発明に係る半導体素子の
実装方法の実施態様例を模式的に示す断面図であり、次
のような手順で行われる。FIGS. 1 to 3 are cross-sectional views schematically showing an embodiment of a method for mounting a semiconductor device according to the present invention.
【００１４】すなわち、図１に断面的に示すように、常
法によりパッシベーション膜６およびバリアメタル層８
がそれぞれ形成された半導体素子１の電極端子２面上
に、めっきなどの方法でリング状の金突起部11を形成し
た後、この金突起部11に囲まれた電極端子２面の凹部内
に、半田などの低融点金属12を、電気めっきするかある
いは図２に模式的に示すように、低融点金属の微小ボー
ル12a を塗布印刷するなどの方法で供給して貯留する。That is, as shown in cross section in FIG. 1, the passivation film 6 and the barrier metal layer 8 are formed by a conventional method.
Is formed on the surface of the electrode terminal 2 of the semiconductor element 1 on which is formed, respectively, by a method such as plating or the like, and then the ring-shaped gold protrusion 11 is formed in the recess of the surface of the electrode terminal 2 surrounded by the gold protrusion 11. A low-melting metal 12 such as solder is supplied and stored by electroplating or by coating and printing micro-balls 12a of low-melting metal as schematically shown in FIG.
【００１５】一方、前記半導体素子１が実装される回路
基板３の対応する接続パッド４上に、前記リング状金突
起部11の内径よりも小さい外径を有するストレートウォ
ール型の金から成る突起状電極13を、選択的めっきなど
の方法で形成する。次いで、このような半導体素子１と
回路基板３とを、フェイスダウン方式のマウンタによ
り、半導体素子１の金突起部11の内側に回路基板３の金
突起状電極13が嵌合するように位置合わせして仮搭載し
た後、リフロー炉を通して低融点金属12もしくは12a を
リフローさせる。リフローにより溶融した低融点金属12
もしくは12a は、図３に断面的に示すように、半導体素
子１の金突起部11と回路基板３の金突起状電極13との隙
間を充填するように濡れ広がる。このとき、低融点金属
12もしくは12a 層の側周面が金突起部11により被覆され
ているので、良好な耐酸化性を呈して、信頼性の高い円
柱状の接続部を形成して所要の実装が達成される。On the other hand, a projection made of straight wall type gold having an outer diameter smaller than the inner diameter of the ring-shaped gold projection 11 is formed on the corresponding connection pad 4 of the circuit board 3 on which the semiconductor element 1 is mounted. The electrode 13 is formed by a method such as selective plating. Next, the semiconductor element 1 and the circuit board 3 are aligned by a face-down type mounter such that the gold-projecting electrodes 13 of the circuit board 3 fit inside the gold-projecting portions 11 of the semiconductor element 1. After that, the low melting point metal 12 or 12a is reflowed through a reflow furnace. Low melting metal 12 melted by reflow
Alternatively, as shown in cross-section in FIG. 3, 12a spreads out so as to fill the gap between the gold projection 11 of the semiconductor element 1 and the gold projection electrode 13 of the circuit board 3. At this time, low melting point metal
Since the side peripheral surface of the layer 12 or 12a is covered with the gold protrusions 11, the desired mounting is achieved by forming a highly reliable columnar connecting portion exhibiting good oxidation resistance.
【００１６】図４および図５は、本発明の他の実施態様
例を模式的に示す断面図である。FIGS. 4 and 5 are cross-sectional views schematically showing another embodiment of the present invention.
【００１７】この実施例では、図４に断面的に示すよう
に、半導体素子１能動面の電極端子２面上に、バリアメ
タル層８を形成した後、この電極端子２以外の能動面上
に、20μm 以上の厚さを有するポリイミド樹脂などの層
14を、たとえばフォトリソグラフィなどにより形成す
る。次いで、前記ポリイミド樹脂層14表面から陥入した
電極端子２面上に、半田などの低融点金属12を、電気め
っきあるいは微小ボール12a を塗布印刷するなどの方法
で供給と貯留（滞留）させる。In this embodiment, as shown in cross section in FIG. 4, a barrier metal layer 8 is formed on the electrode terminal 2 on the active surface of the semiconductor element 1, and then on the active surface other than the electrode terminal 2. , A layer of polyimide resin or the like having a thickness of 20 μm or more
14 is formed by, for example, photolithography. Next, the low melting point metal 12 such as solder is supplied and stored (retained) by a method such as electroplating or application and printing of microballs 12a on the surface of the electrode terminal 2 recessed from the surface of the polyimide resin layer 14.
【００１８】一方、回路基板３の接続パッド４上に、前
記陥入部（低融点金属12などが貯留している領域）より
も小さい外径を有するストレートウォール型の銅から成
る突起状電極13a を、選択的めっきなどの方法で形成す
る。なお、この突起状電極13a の高さは、20μm 以上た
とえば50μm 程度とする。次に、前記半導体素子１と回
路基板３とを、フェイスダウン方式のマウンタにより、
低融点金属12(12a) が貯留（滞留）した電極端子２面に
回路基板３の突起状電極13a の上面が当接するように位
置合わせして仮搭載した後、リフロー炉を通して低融点
金属12(12a) をリフローさせる。こうして、図５に断面
的に示すように、溶融した低融点金属12(12a) の層を介
して、半導体素子１の電極端子２と回路基板３の突起状
電極13aとが強固に接合され、強度の高い接続部を形成
して所要の実装がなされる。On the other hand, on the connection pad 4 of the circuit board 3, a projecting electrode 13a made of straight-wall type copper having an outer diameter smaller than that of the recess (the area where the low melting point metal 12 or the like is stored) is formed. , By selective plating or the like. The height of the protruding electrode 13a is not less than 20 μm, for example, about 50 μm. Next, the semiconductor element 1 and the circuit board 3 are separated by a face-down type mounter.
After the low melting point metal 12 (12a) is temporarily mounted and positioned so that the upper surface of the protruding electrode 13a of the circuit board 3 is in contact with the surface of the electrode terminal 2 where the low melting point metal 12 (12a) is stored (resides), the low melting point metal 12 (12a) is passed through a reflow furnace. 12a) is reflowed. In this way, as shown in cross section in FIG. 5, the electrode terminals 2 of the semiconductor element 1 and the protruding electrodes 13a of the circuit board 3 are firmly joined via the layer of the molten low melting point metal 12 (12a), The required mounting is performed by forming a connection part having high strength.
【００１９】[0019]
【発明の効果】以上説明したように本発明の半導体素子
の実装方法によれば、少量の低融点金属を用いて所要の
接合・実装を完成させることができ、ブリッジなどの接
続不良が生じないうえに、十分な機械的強度を有する接
続部が得られる。また、半導体素子と回路基板との間の
隙間の大きさを、低融点金属の流出防止用突堤として形
成されるリング状金突起部などの高さ、あるいは回路基
板側の突起状電極の高さを変えることにより、容易に調
整することができるので、プロセス上設計上の簡易性が
増し、歩留まりの向上が期待される。さらに、これらの
隙間を任意に設定することにより、熱サイクルが加わっ
た際の半導体素子と回路基板との熱膨脹率の差による応
力を緩和することができる。さらにまた、リング状金突
起部を形成した場合は、接合部の低融点金属層の側周面
が金で被覆された構造となるため、耐酸化性の点で信頼
性が著しく向上した接続部を形成した実装がなされる。As described above, according to the semiconductor device mounting method of the present invention, required bonding and mounting can be completed using a small amount of low melting point metal, and no connection failure such as a bridge occurs. In addition, a connection with sufficient mechanical strength is obtained. In addition, the size of the gap between the semiconductor element and the circuit board is determined by the height of a ring-shaped gold protrusion formed as a jetty for preventing outflow of low melting point metal, or the height of a protrusion-like electrode on the circuit board side. By changing the value, it is possible to easily adjust, so that simplicity in process and design is increased, and improvement in yield is expected. Furthermore, by setting these gaps arbitrarily, stress caused by a difference in thermal expansion coefficient between the semiconductor element and the circuit board when a thermal cycle is applied can be reduced. Furthermore, when a ring-shaped gold protrusion is formed, the side peripheral surface of the low-melting metal layer of the joint has a structure covered with gold, so that the connection part has significantly improved reliability in terms of oxidation resistance. Is formed.
【図１】本発明に係る半導体素子の実装方法の実施態様
例において、入出力電極端子の凹面に低融点金属を貯留
させた半導体素子および接続パッド上に突起状電極を形
成した回路基板の状態をそれぞれ模式的に示す断面図。FIG. 1 is a diagram showing an embodiment of a semiconductor element mounting method according to the present invention, in which a semiconductor element in which a low melting point metal is stored in a concave surface of an input / output electrode terminal and a state of a circuit board in which projecting electrodes are formed on connection pads; Sectional drawing which each shows typically.
【図２】本発明に係る半導体素子の実装方法の実施態様
例において、をた入出力電極端子の凹面に低融点金属の
微小ボールを塗布印刷して貯留させた半導体素子の状態
を模式的に示す断面図。FIG. 2 schematically shows a state of a semiconductor element in which a low-melting-point metal microball is applied and printed on a concave surface of an input / output electrode terminal and stored in an embodiment of a mounting method of a semiconductor element according to the present invention. FIG.
【図３】本発明に係る半導体素子の実装方法の実施態様
例において、回路基板上に半導体素子を実装した状態を
模式的に示す断面図。FIG. 3 is a cross-sectional view schematically showing a state in which a semiconductor element is mounted on a circuit board in an embodiment of a method for mounting a semiconductor element according to the present invention.
【図４】本発明に係る半導体素子の実装方法の別の実施
態様例において、入出力電極端子凹面部に低融点金属を
貯留させた半導体素子および接続パッド上に突起状電極
を形成した回路基板の状態をそれぞれ模式的に示す断面
図。FIG. 4 is a view showing another embodiment of a method of mounting a semiconductor device according to the present invention, wherein a semiconductor element having a low melting point metal stored in a concave portion of an input / output electrode terminal and a circuit board having projecting electrodes formed on connection pads; Sectional drawing which shows each state typically.
【図５】本発明に係る半導体素子の実装方法の別の実施
態様例において、回路基板上に半導体素子を実装した状
態を模式的に示す断面図。FIG. 5 is a cross-sectional view schematically showing a state in which a semiconductor element is mounted on a circuit board in another embodiment of the semiconductor element mounting method according to the present invention.
【図６】従来の低融点金属の接続用バンプを用いた半導
体素子の実装方法の実施態様を模式的に示す断面図。FIG. 6 is a cross-sectional view schematically showing an embodiment of a conventional method of mounting a semiconductor element using a low-melting-point metal connection bump.
【図７】従来の光硬化性樹脂などを用いて圧着接合する
半導体素子の実装方法の実施態様を模式的に示す断面
図。FIG. 7 is a cross-sectional view schematically showing an embodiment of a conventional method of mounting a semiconductor element by pressure bonding using a photocurable resin or the like.
１…半導体素子（フリーツプチップ） ２…入出力電
極端子 ３…回路基板４…接続パッド ５…接続用
バンプ ６…パッシベーション膜 ７…ソルダーレ
ジスト層 ８…バリアメタル層 ９、13、13a …突
起状電極10…光硬化性樹脂 11…リング状金突起部
12、12a …低融点金属 14…ポリイミド樹脂層DESCRIPTION OF SYMBOLS 1 ... Semiconductor element (free-tip chip) 2 ... Input / output electrode terminal 3 ... Circuit board 4 ... Connection pad 5 ... Connection bump 6 ... Passivation film 7 ... Solder resist layer 8 ... Barrier metal layer 9, 13, 13a ... Projection Electrode 10: Photo-curable resin 11: Ring-shaped gold protrusion
12, 12a: Low melting point metal 14: Polyimide resin layer
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−187638（ＪＰ，Ａ) 特開 昭64−91118（ＪＰ，Ａ) 特開 昭64−28931（ＪＰ，Ａ) 特開 平８−330360（ＪＰ，Ａ) 実開 平４−70743（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311 H01L 21/92 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-187638 (JP, A) JP-A-64-11118 (JP, A) JP-A-64-28931 (JP, A) JP-A-8-118 330360 (JP, A) Japanese Utility Model Hei 4-70743 (JP, U) (58) Field surveyed (Int. Cl. 6 , DB name) H01L 21/60 311 H01L 21/92
Claims (2)
に、半導体素子の入出力電極端子を位置合わせしフェイ
スダウンに接続・実装する方法において、 前記回路基板面の接続パッドが突起状に形成され、半導
体素子の入出力電極端子面側が、前記接続パッドの突起
が嵌合可能な縦断面凹型に形成され、かつ凹部に低融点
金属を介在させ、この低融点金属をリフローさせて半導
体素子を回路基板面にフェイスダウンに接続・実装する
ことを特徴とする半導体素子の実装方法。1. A method of aligning an input / output electrode terminal of a semiconductor element with a connection pad provided on a circuit board surface and connecting / mounting the terminal face-down, wherein the connection pad on the circuit board surface is formed in a projection shape. The input / output electrode terminal surface side of the semiconductor element is formed in a concave longitudinal section in which the projection of the connection pad can be fitted, and a low melting point metal is interposed in the concave part, and the low melting point metal is reflowed to form the semiconductor element. A method for mounting a semiconductor element, wherein the semiconductor element is connected and mounted face down on a circuit board surface.
ていることを特徴とする請求項１記載の半導体素子の実
装方法。 2. The method according to claim 1, wherein the side wall protrusion having a concave vertical section is formed of gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3158274A JP2880825B2 (en) | 1991-06-28 | 1991-06-28 | Semiconductor element mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3158274A JP2880825B2 (en) | 1991-06-28 | 1991-06-28 | Semiconductor element mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0513496A JPH0513496A (en) | 1993-01-22 |
| JP2880825B2 true JP2880825B2 (en) | 1999-04-12 |
Family
ID=15668025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3158274A Expired - Fee Related JP2880825B2 (en) | 1991-06-28 | 1991-06-28 | Semiconductor element mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2880825B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7316664B2 (en) | 2002-10-21 | 2008-01-08 | Advanced Medical Optics, Inc. | Modulated pulsed ultrasonic power delivery system and method |
| JP2006093420A (en) * | 2004-09-24 | 2006-04-06 | Oki Electric Ind Co Ltd | Mounting method of semiconductor device |
| US7611040B2 (en) | 2005-05-24 | 2009-11-03 | Panasonic Corporation | Method for forming solder bump and method for mounting semiconductor device using a solder powder resin composition |
| JP4835406B2 (en) * | 2006-11-24 | 2011-12-14 | 富士通株式会社 | Mounting structure and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
| WO2012070381A1 (en) * | 2010-11-22 | 2012-05-31 | 日本電気株式会社 | Mounting structure and mounting method |
| KR101936232B1 (en) | 2012-05-24 | 2019-01-08 | 삼성전자주식회사 | Electrical interconnection structures and methods for fabricating the same |
-
1991
- 1991-06-28 JP JP3158274A patent/JP2880825B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0513496A (en) | 1993-01-22 |
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