JP3646500B2 - Electronic circuit equipment - Google Patents

Electronic circuit equipment Download PDF

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Publication number
JP3646500B2
JP3646500B2 JP02385598A JP2385598A JP3646500B2 JP 3646500 B2 JP3646500 B2 JP 3646500B2 JP 02385598 A JP02385598 A JP 02385598A JP 2385598 A JP2385598 A JP 2385598A JP 3646500 B2 JP3646500 B2 JP 3646500B2
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Japan
Prior art keywords
bare chip
resist film
solder resist
electronic circuit
solder
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JP02385598A
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JPH11214449A (en
Inventor
良嗣 堀
達弥 舟木
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は混成集積回路のように、配線基板上にベアチップと表面実装部品とが混在して実装された複合型の電子回路装置に関するものである。
【０００２】
【従来の技術】
従来、混成集積回路において、プリント配線基板などのエポキシ樹脂等を基材とする配線基板に、ベアチップをはんだバンプ技術を用いて搭載する場合、図１に示す方法がとられていた（特開平５−２１８１３５号公報）。すなわち、１は配線基板、２はベアチップであり、配線基板１上に形成された電極３上にベアチップ２がはんだバンプ４を介して接合され、フリップチップ実装されている。配線基板１の電極３は、はんだの不要な濡れ拡がりを防止するためソルダーレジスト膜５によって被覆されている。このソルダーレジスト膜５はベアチップ２の周囲だけでなくベアチップ２の下面側にも設けられている。
なお、図１では説明を簡単にするため、配線基板１上にベアチップ２のみが実装されているが、実際にはベアチップ２に隣接してチップコンデンサやチップ抵抗などの他の表面実装部品が実装される。
【０００３】
【発明が解決しようとする課題】
上記のような混成集積回路では、はんだの不要な拡がりを防止してはんだバンプ４の形状を整えるとともに、ベアチップ２の沈み込みを防止し、かつはんだバンプ４同士がブリッジするのを防止するため、ベアチップ２の下面側にレジスト膜５ａ設けられている。つまり、はんだバンプ４が電極３と確実に接合されるように、レジスト膜５ａの膜厚以上のバンプ高さが維持されていなければならない。しかし、レジスト膜５ａの膜厚は膜形成方法などによって異なるため、はんだバンプ４の厚みを一々調整しなければならず、煩雑であった。また、はんだバンプ４を必要以上に厚肉に形成すると、隣接するバンプ４同士がブリッジを起こす恐れがある。
【０００４】
そこで、本発明の目的は、ソルダーレジスト膜の膜厚とは関係なく、バンプ接合の接合強度の向上と確実な導通性とを確保できる電子回路装置を提供することにある。
【０００５】
【課題を解決するための手段】
上記目的を達成するため、請求項１に記載の発明は、配線基板の表面に配線電極が形成され、上記配線電極に対しベアチップがフリップチップ実装されるとともに表面実装部品が半田付けされ、上記半田付け部を除く部位がソルダーレジスト膜で覆われた電子回路装置において、上記ベアチップ搭載部に対応するソルダーレジスト膜の部位に空所を設けるとともに、上記ベアチップをベアチップ搭載部に金属バンプの固相拡散によってバンプ接合したものである。
【０００６】
【課題を解決するための手段】
上記目的を達成するため、請求項１に記載の発明は、配線基板の表面に配線電極が形成され、上記配線電極に対しベアチップがフリップチップ実装されるとともに表面実装部品が半田付けされ、上記半田付け部を除く部位がソルダーレジスト膜で覆われた電子回路装置において、上記ベアチップ搭載部に対応するソルダーレジスト膜の部位に空所を設けるとともに、上記ベアチップをベアチップ搭載部に金属バンプの固相拡散によってバンプ接合してなり、上記ベアチップ搭載部の周囲のソルダーレジスト膜の膜厚は、ベアチップの下面と配線基板の表面との隙間より大きいことを特徴とする電子回路装置を提供する。
【０００７】
本発明では、はんだバンプに代えて固相拡散によって接合される金属バンプを用いたので、はんだ流れを起こす恐れがなく、しかも隣接するバンプ同士がブリッジを起こす心配もない。また、レジスト膜の膜厚に関係なく背の低いバンプでも実装でき、かつ実装時に十分な荷重を付加できるので、接合強度の上昇が望める。
【０００８】
従来では、ソルダーレジスト膜の膜厚とはんだバンプの厚みを厳密に管理する必要があったが、本発明ではソルダーレジスト膜の膜厚をベアチップの下面と配線基板の表面との隙間より高くしても全く支障がない。ベアチップの下面と配線基板の表面との隙間には封止樹脂を充填する場合があるが、請求項２のように、ベアチップ搭載部の周囲のソルダーレジスト膜の膜厚を大きくしておくことで、レジスト膜がダムの役割をなし、樹脂の溢れ出しを有効に防止できる。
【０００９】
従来では、ソルダーレジスト膜の膜厚とはんだバンプの厚みを厳密に管理する必要があったが、本発明ではソルダーレジスト膜の膜厚をベアチップの下面と配線基板の表面との隙間より高くしても全く支障がない。ベアチップの下面と配線基板の表面との隙間には封止樹脂を充填する場合があるが、本発明では、ベアチップ搭載部の周囲のソルダーレジスト膜の膜厚を大きくしておくことで、レジスト膜がダムの役割をなし、樹脂の溢れ出しを有効に防止できる。
【００１０】
【発明の実施の形態】
図２〜図５は本発明にかかる電子回路装置の一例である混成集積回路を示す。図において、１０はプリント配線基板であり、その上面には配線電極１１がパターン形成されている。配線基板１０の上面はベアチップ搭載部１２と表面実装部品の半田付け部１３，１４を残してソルダーレジスト膜１５で覆われている。すなわち、ベアチップ搭載部１２および半田付け部１３，１４はソルダーレジスト膜１５の空所で構成されている。ソルダーレジスト膜１５の材質としては、例えば熱硬化型のメラミン樹脂，エポキシ樹脂、紫外線硬化型のエポキシ樹脂，ポリイミド樹脂などを用いることができる。ソルダーレジスト膜１５の膜厚ｔは例えば１０〜１００μｍ程度の厚みに形成されている。
【００１１】
図４に示すように、ベアチップ搭載部１２には電極１１の一部が露出しており、これら電極１１の露出部にＩＣチップなどのベアチップ２０がフリップチップ実装されている。すなわち、ベアチップ２０の下面にはチップ電極２１が設けられ、これらチップ電極２１にはそれぞれ金属バンプ２２が形成されている。金属バンプ２２としては、Ａｕ，Ｃｕなど公知の金属材料が使用されるが、ここでは公知のワイヤーバンピング法で容易にバンプ形成できるＡｕワイヤーを用いている。この実施例では、バンプ２２の接合前の高さは約４０〜５０μｍである。
【００１２】
上記金属バンプ２２が電極１１の露出部に熱圧着、超音波圧着、熱／超音波併用による圧着などの固相拡散により接合されている（図５参照）。接合状態において、バンプ高さは１０〜２０μｍに押し潰されるが、ベアチップ２０の下側にはソルダーレジスト膜１５が形成されていないので、ベアチップ２０とソルダーレジスト膜１５とが干渉しない。そのため、背の低いバンプ２２でも実装でき、かつ接合時に十分な荷重を付加できるので、接合強度の上昇が望める。上記のようにベアチップ２０をフリップチップ実装した後、ベアチップ２０と配線基板１０との隙間にエポキシ樹脂などの封止樹脂（図示せず）を注入し、毛細管現象により浸透させ、固化させる。このとき、ベアチップ搭載部１２の周壁を構成するソルダーレジスト膜１５は、樹脂の拡がりを防止するダムとしての役割を有する。特に、バンプ接合後のベアチップ２０と配線基板１０との隙間ｄよりソルダーレジスト膜１５の膜厚ｔを大きくしておけば、樹脂流れの防止効果が高く、注入樹脂量のバラツキを吸収できる。
【００１３】
また、半田付け部１３，１４にも電極１１が露出しており、これら電極１１の露出部にコンデンサなどの表面実装部品２３，２４が半田２５，２６によって接続されている。この場合には、ソルダーレジスト膜１５が半田流れを防止する役割を有する。
【００１４】
上記実施例では、図４のようにベアチップ２０のチップ電極２１に金属バンプ２２を形成したが、これに限るものではなく、図６のように配線基板１０の配線電極１１上に金属バンプ２２を形成してもよい。この場合も、金属バンプ２２とチップ電極２１とが熱圧着などの固相拡散により接合される。
【００１５】
なお、本発明の金属バンプは、ワイヤーバンピング法で形成されたものに限らず、メッキ法などの他の公知の方法で形成することができる。
【００１６】
【発明の効果】
以上の説明で明らかなように、本発明によれば、ソルダーレジスト膜のベアチップ搭載部に対応する箇所を空所としておき、ベアチップとレジスト膜との干渉を防止したので、レジスト膜の膜厚に関係なく背の低いバンプでも実装でき、かつ実装時に十分な荷重を付加できるので、接合強度を高めることができる。
また、本発明では、はんだバンプに代えて固相拡散によって接合される金属バンプを用いたので、強く圧着しても、はんだ流れを起こす恐れがなく、しかも隣接するバンプ同士がブリッジを起こす心配もない。
さらに、本発明では、ベアチップ搭載部の周囲のソルダーレジスト膜の膜厚をベアチップの下面と配線基板の表面との隙間より大きくしたので、レジスト膜がダムの役割をなし、樹脂の溢れ出しを有効に防止できる。
【図面の簡単な説明】
【図１】従来のベアチップの実装構造を示す断面図である。
【図２】本発明にかかる電子回路装置の一例の平面図である。
【図３】図２の電子回路装置の断面図である。
【図４】ベアチップの実装前の拡大断面図である。
【図５】ベアチップの実装後の拡大断面図である。
【図６】ベアチップの実装前の他の例の拡大断面図である。
【符号の説明】
１０ 配線基板
１１ 電極
１２ ベアチップ搭載部（空所）
１３，１４ 半田付け部
１５ ソルダーレジスト膜
２０ ベアチップ
２２ 金属バンプ
２３，２４ 表面実装部品[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a composite electronic circuit device in which a bare chip and a surface-mounted component are mixedly mounted on a wiring board, such as a hybrid integrated circuit.
[0002]
[Prior art]
Conventionally, in a hybrid integrated circuit, when a bare chip is mounted on a wiring board based on an epoxy resin or the like such as a printed wiring board using a solder bump technique, the method shown in FIG. -218135). That is, 1 is a wiring board, 2 is a bare chip, and the bare chip 2 is bonded to the electrode 3 formed on the wiring board 1 via the solder bumps 4 and is flip-chip mounted. The electrode 3 of the wiring board 1 is covered with a solder resist film 5 in order to prevent unnecessary wetting and spreading of solder. The solder resist film 5 is provided not only around the bare chip 2 but also on the lower surface side of the bare chip 2.
In FIG. 1, only the bare chip 2 is mounted on the wiring substrate 1 for the sake of simplicity of description, but in actuality, other surface mount components such as a chip capacitor and a chip resistor are mounted adjacent to the bare chip 2. Is done.
[0003]
[Problems to be solved by the invention]
In the hybrid integrated circuit as described above, in order to prevent unnecessary spreading of the solder and adjust the shape of the solder bump 4, to prevent the bare chip 2 from sinking and to prevent the solder bumps 4 from bridging, A resist film 5 a is provided on the lower surface side of the bare chip 2. That is, the bump height equal to or greater than the film thickness of the resist film 5a must be maintained so that the solder bump 4 is securely bonded to the electrode 3. However, since the film thickness of the resist film 5a differs depending on the film forming method and the like, the thickness of the solder bump 4 has to be adjusted one by one, which is complicated. Further, if the solder bumps 4 are formed to be thicker than necessary, the adjacent bumps 4 may be bridged.
[0004]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an electronic circuit device that can ensure improvement in bonding strength of bump bonding and reliable conductivity regardless of the film thickness of the solder resist film.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a wiring electrode is formed on a surface of a wiring board, a bare chip is flip-chip mounted on the wiring electrode, and a surface mounting component is soldered. In an electronic circuit device in which a portion other than the attachment portion is covered with a solder resist film, a space is provided in the portion of the solder resist film corresponding to the bare chip mounting portion, and the bare chip is solid-phase diffused into the bare chip mounting portion. Are bump-bonded.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a wiring electrode is formed on a surface of a wiring board, a bare chip is flip-chip mounted on the wiring electrode, and a surface mounting component is soldered. In an electronic circuit device in which a portion excluding the attachment portion is covered with a solder resist film, a space is provided in a portion of the solder resist film corresponding to the bare chip mounting portion, and solid phase diffusion of metal bumps on the bare chip mounting portion is performed. The electronic circuit device is characterized in that the film thickness of the solder resist film around the bare chip mounting portion is larger than the gap between the bottom surface of the bare chip and the surface of the wiring board.
[0007]
In the present invention, metal bumps bonded by solid phase diffusion are used instead of solder bumps, so there is no fear of solder flow and there is no fear of bridging between adjacent bumps. Further, it is possible to mount even a short bump regardless of the thickness of the resist film, and a sufficient load can be applied at the time of mounting, so that an increase in bonding strength can be expected.
[0008]
Conventionally, it was necessary to strictly control the thickness of the solder resist film and the thickness of the solder bump. However, in the present invention, the thickness of the solder resist film is set higher than the gap between the bottom surface of the bare chip and the surface of the wiring board. No problem at all. The gap between the bottom surface of the bare chip and the surface of the wiring board may be filled with sealing resin. However, as described in claim 2, by increasing the film thickness of the solder resist film around the bare chip mounting portion. The resist film acts as a dam and can effectively prevent the resin from overflowing.
[0009]
Conventionally, it was necessary to strictly control the thickness of the solder resist film and the thickness of the solder bump. However, in the present invention, the thickness of the solder resist film is set higher than the gap between the bottom surface of the bare chip and the surface of the wiring board. No problem at all. The gap between the bottom surface of the bare chip and the surface of the wiring board may be filled with sealing resin, but in the present invention, the resist film is formed by increasing the film thickness of the solder resist film around the bare chip mounting portion. Can play the role of a dam and effectively prevent the overflow of the resin.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
2 to 5 show a hybrid integrated circuit which is an example of an electronic circuit device according to the present invention. In the figure, reference numeral 10 denotes a printed wiring board, and wiring electrodes 11 are patterned on the upper surface thereof. The upper surface of the wiring substrate 10 is covered with a solder resist film 15 except for the bare chip mounting portion 12 and the soldering portions 13 and 14 of the surface mount components. That is, the bare chip mounting portion 12 and the soldering portions 13 and 14 are formed by voids in the solder resist film 15. As a material of the solder resist film 15, for example, a thermosetting melamine resin, an epoxy resin, an ultraviolet curable epoxy resin, a polyimide resin, or the like can be used. The solder resist film 15 has a thickness t of, for example, about 10 to 100 μm.
[0011]
As shown in FIG. 4, a part of the electrode 11 is exposed on the bare chip mounting portion 12, and a bare chip 20 such as an IC chip is flip-chip mounted on the exposed portion of the electrode 11. That is, chip electrodes 21 are provided on the lower surface of the bare chip 20, and metal bumps 22 are formed on these chip electrodes 21. As the metal bumps 22, known metal materials such as Au and Cu are used, but here, Au wires that can be easily bump-formed by a known wire bumping method are used. In this embodiment, the height of the bump 22 before bonding is about 40 to 50 μm.
[0012]
The metal bump 22 is joined to the exposed portion of the electrode 11 by solid phase diffusion such as thermocompression bonding, ultrasonic pressure bonding, or heat / ultrasonic pressure bonding (see FIG. 5). In the bonded state, the bump height is crushed to 10 to 20 μm, but since the solder resist film 15 is not formed on the lower side of the bare chip 20, the bare chip 20 and the solder resist film 15 do not interfere with each other. For this reason, even the bumps 22 having a short height can be mounted and a sufficient load can be applied at the time of bonding, so that an increase in bonding strength can be expected. After the bare chip 20 is flip-chip mounted as described above, a sealing resin (not shown) such as an epoxy resin is injected into the gap between the bare chip 20 and the wiring substrate 10, and is infiltrated and solidified by a capillary phenomenon. At this time, the solder resist film 15 constituting the peripheral wall of the bare chip mounting portion 12 serves as a dam that prevents the resin from spreading. In particular, if the film thickness t of the solder resist film 15 is made larger than the gap d between the bare chip 20 and the wiring substrate 10 after bump bonding, the effect of preventing the resin flow is high, and variations in the amount of injected resin can be absorbed.
[0013]
The electrodes 11 are also exposed at the soldering portions 13 and 14, and surface mount components 23 and 24 such as capacitors are connected to the exposed portions of the electrodes 11 by solders 25 and 26. In this case, the solder resist film 15 has a role of preventing the solder flow.
[0014]
In the above embodiment, the metal bumps 22 are formed on the chip electrodes 21 of the bare chip 20 as shown in FIG. 4. However, the present invention is not limited to this, and the metal bumps 22 are formed on the wiring electrodes 11 of the wiring board 10 as shown in FIG. It may be formed. Also in this case, the metal bumps 22 and the chip electrodes 21 are joined by solid phase diffusion such as thermocompression bonding.
[0015]
The metal bumps of the present invention are not limited to those formed by the wire bumping method, and can be formed by other known methods such as a plating method.
[0016]
【The invention's effect】
As is apparent from the above description, according to the present invention, the portion corresponding to the bare chip mounting portion of the solder resist film is left as a void, and interference between the bare chip and the resist film is prevented, so that the resist film thickness is increased. Irrespective of the short bumps can be mounted, and a sufficient load can be applied during mounting, so that the bonding strength can be increased.
Further, in the present invention, metal bumps bonded by solid phase diffusion are used instead of solder bumps, so that there is no risk of solder flow even when strongly pressed, and there is also a concern that adjacent bumps may bridge. Absent.
Furthermore, in the present invention, since the film thickness of the solder resist film around the bare chip mounting portion is made larger than the gap between the bottom surface of the bare chip and the surface of the wiring board, the resist film serves as a dam and effectively prevents the resin from overflowing. Can be prevented.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a conventional bare chip mounting structure.
FIG. 2 is a plan view of an example of an electronic circuit device according to the present invention.
3 is a cross-sectional view of the electronic circuit device of FIG.
FIG. 4 is an enlarged cross-sectional view before mounting a bare chip.
FIG. 5 is an enlarged cross-sectional view after mounting a bare chip.
FIG. 6 is an enlarged cross-sectional view of another example before mounting a bare chip.
[Explanation of symbols]
10 Wiring board 11 Electrode 12 Bare chip mounting part (vacant space)
13, 14 Soldering portion 15 Solder resist film 20 Bare chip 22 Metal bumps 23, 24 Surface mount component

Claims (2)

配線基板の表面に配線電極が形成され、上記配線電極に対しベアチップがフリップチップ実装されるとともに表面実装部品が半田付けされ、上記半田付け部を除く部位がソルダーレジスト膜で覆われた電子回路装置において、
上記ベアチップ搭載部に対応するソルダーレジスト膜の部位に空所を設けるとともに、上記ベアチップを上記ベアチップ搭載部に金属バンプの固相拡散によってバンプ接合してなり、
上記ベアチップ搭載部の周囲のソルダーレジスト膜の膜厚は、ベアチップの下面と配線基板の表面との隙間より大きいことを特徴とする電子回路装置。An electronic circuit device in which a wiring electrode is formed on a surface of a wiring board, a bare chip is flip-chip mounted on the wiring electrode, a surface mounting component is soldered, and a portion other than the soldering portion is covered with a solder resist film In
Provided with a voids in a portion of the solder resist film corresponding to the bare chip mounting portion, the bare chip becomes by bump bonding by solid-phase diffusion of the metal bumps on the bare chip mounting portion,
2. An electronic circuit device according to claim 1, wherein a film thickness of the solder resist film around the bare chip mounting portion is larger than a gap between the bottom surface of the bare chip and the surface of the wiring board . 上記金属バンプはＡｕを主成分とする金属で形成されていることを特徴とする請求項１に記載の電子回路装置。2. The electronic circuit device according to claim 1 , wherein the metal bump is made of a metal having Au as a main component.
JP02385598A 1998-01-20 1998-01-20 Electronic circuit equipment Expired - Lifetime JP3646500B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02385598A JP3646500B2 (en) 1998-01-20 1998-01-20 Electronic circuit equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02385598A JP3646500B2 (en) 1998-01-20 1998-01-20 Electronic circuit equipment

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JPH11214449A JPH11214449A (en) 1999-08-06
JP3646500B2 true JP3646500B2 (en) 2005-05-11

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Publication number Priority date Publication date Assignee Title
JP4366342B2 (en) * 2005-07-08 2009-11-18 ホシデン株式会社 Mounting board and microphone mounted thereon
KR101022942B1 (en) * 2008-11-12 2011-03-16 삼성전기주식회사 A printed circuit board having a flow preventing dam and a manufacturing method of the same
WO2011125546A1 (en) 2010-03-31 2011-10-13 京セラ株式会社 Interposer and electronic device using same
DE112021005514T5 (en) * 2020-10-19 2023-08-17 Tdk Corporation mounting plate and circuit board

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