JP2893634B2 - Connection structure of electronic components - Google Patents

Connection structure of electronic components

Info

Publication number
JP2893634B2
JP2893634B2 JP9076716A JP7671697A JP2893634B2 JP 2893634 B2 JP2893634 B2 JP 2893634B2 JP 9076716 A JP9076716 A JP 9076716A JP 7671697 A JP7671697 A JP 7671697A JP 2893634 B2 JP2893634 B2 JP 2893634B2
Authority
JP
Japan
Prior art keywords
solder
chip
bump
bumps
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9076716A
Other languages
Japanese (ja)
Other versions
JPH1012659A (en
Inventor
充彦 山本
治 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KASHIO KEISANKI KK
Original Assignee
KASHIO KEISANKI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KASHIO KEISANKI KK filed Critical KASHIO KEISANKI KK
Priority to JP9076716A priority Critical patent/JP2893634B2/en
Publication of JPH1012659A publication Critical patent/JPH1012659A/en
Application granted granted Critical
Publication of JP2893634B2 publication Critical patent/JP2893634B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】この発明は電子部品の接続構造に
関し、例えば、ＩＣチップと配線基板の接続構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure for electronic components, for example, to a connection structure between an IC chip and a wiring board.

【０００２】[0002]

【従来の技術】フリップチップボンディング等とよばれ
るＩＣチップの実装技術では、例えば図９に示すよう
に、ＩＣチップ１を配線基板１１上に搭載している。す
なわち、ＩＣチップ１は、チップ本体２の下面にアルミ
ニウム等からなる電極３がパターン形成され、電極３の
下面の所定の一部を除く全下面に保護膜４が設けられ、
電極３の露出面上に、チタンとタングステンとからなる
合金の下面にクロムを積層してなるもの等からなるアン
ダーバンプメタル５が設けられ、アンダーバンプメタル
５の下面に銅等からなる金属層６が設けられ、金属層６
の周囲に当初球状の半田バンプ７が設けられた構造とな
っている。配線基板１１は、樹脂等からなる基板本体１
２の上面に銅等からなる接続パッド１３がパターン形成
され、接続パッド１３の上面の所定の一部を除く全上面
に保護膜１４が設けられ、接続パッド１３の露出面上
に、金、銀、スズ等の半田との密着性の良い金属からな
る金属層１５が設けられた構造となっている。そして、
ＩＣチップ１の半田バンプ７を配線基板１１の金属層１
５に熱圧着すると、半田バンプ７が一旦溶融状態となっ
た後冷却されて固化することにより、半田バンプ７が金
属層１５に固着されて接続され、これによりＩＣチップ
１が配線基板１１上に搭載される。2. Description of the Related Art In an IC chip mounting technique called flip chip bonding, an IC chip 1 is mounted on a wiring board 11 as shown in FIG. That is, in the IC chip 1, the electrode 3 made of aluminum or the like is pattern-formed on the lower surface of the chip main body 2, and the protective film 4 is provided on the entire lower surface of the lower surface of the electrode 3 except for a predetermined part.
On the exposed surface of the electrode 3, an under bump metal 5 made of, for example, a material obtained by laminating chromium on the lower surface of an alloy made of titanium and tungsten is provided, and a metal layer 6 made of copper or the like is formed on the lower surface of the under bump metal 5. Is provided, and the metal layer 6 is provided.
Is initially provided with a spherical solder bump 7. The wiring board 11 is a board body 1 made of resin or the like.
A connection pad 13 made of copper or the like is pattern-formed on the upper surface of the connection pad 2, a protective film 14 is provided on the entire upper surface of the upper surface of the connection pad 13 except for a predetermined part, and gold or silver is provided on the exposed surface of the connection pad 13. , And a metal layer 15 made of a metal having good adhesion to solder such as tin. And
The solder bumps 7 of the IC chip 1 are connected to the metal layer 1 of the wiring board 11.
5, the solder bumps 7 are once melted, then cooled and solidified, so that the solder bumps 7 are fixedly connected to the metal layer 15 and connected, whereby the IC chip 1 is placed on the wiring board 11. Will be installed.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、従来の
このようなＩＣチップの接続構造では、熱圧着時におけ
る加圧により当初球状の半田バンプ７が横方向につぶれ
てＩＣチップ１の電極３から大きく食み出し、このため
ＩＣチップ１の電極３のピッチが小さすぎると相隣接す
る半田バンプ７間で短絡が発生してしまうので、ＩＣチ
ップ１の電極３のピッチとして１５０〜２００μｍ程度
が限界であり、それ以下のピッチのものには対応できな
いという問題があった。なお、当初球状の半田バンプ７
の直径を小さくすることが考えられるが、このようにす
ると、ＩＣチップ１と配線基板１１との接続強度が小さ
くなるばかりでなく、ＩＣチップ１と配線基板１１の各
熱膨張係数の相違から、ＩＣチップ１と配線基板１１と
の面方向の位置がずれると、断線が生じてしまうことが
ある。このようなことを回避するには、当初球状の半田
バンプ７の直径を大きくすればよいが、あまり大きくす
ると、上述したように半田バンプ７が横方向につぶれて
ＩＣチップ１の電極３から大きく食み出すばかりでな
く、ＩＣチップ１に球状の半田バンプ７を形成する時の
半田メッキ工程やウエットバック工程において相隣接す
る半田バンプ７間で短絡が発生してしまうことがある。
この発明の目的は、例えばＩＣチップの電極のピッチが
より一層微細であっても、相隣接するバンプ間で短絡が
発生しないようにすることのできる電子部品の接続構造
を提供することにある。However, in such a conventional connection structure for an IC chip, the initially spherical solder bumps 7 are crushed in the horizontal direction by the pressurization at the time of thermocompression bonding, and the solder bumps 7 are largely separated from the electrodes 3 of the IC chip 1. If the pitch of the electrodes 3 of the IC chip 1 is too small, a short circuit occurs between the adjacent solder bumps 7. Therefore, the pitch of the electrodes 3 of the IC chip 1 is limited to about 150 to 200 μm. There is a problem that pitches smaller than this cannot be handled. It should be noted that the initially solder bumps 7
It is conceivable that the diameter of the IC chip 1 and the wiring board 11 are decreased, and the difference in thermal expansion coefficient between the IC chip 1 and the wiring board 11 is not only reduced. If the positions of the IC chip 1 and the wiring board 11 in the plane direction are shifted, disconnection may occur. In order to avoid such a situation, the diameter of the spherical solder bump 7 may be initially increased. However, if the diameter is too large, the solder bump 7 is crushed in the lateral direction as described above, and the solder bump 7 is largely separated from the electrode 3 of the IC chip 1. In addition to the protrusion, a short circuit may occur between adjacent solder bumps 7 in a solder plating process or a wet back process when the spherical solder bumps 7 are formed on the IC chip 1.
SUMMARY OF THE INVENTION An object of the present invention is to provide a connection structure for electronic components that can prevent a short circuit from occurring between adjacent bumps even when the pitch of electrodes of an IC chip is finer.

【０００４】[0004]

【課題を解決するための手段】この発明は、第１電子部
品に設けられた第１バンプと第２電子部品に設けられた
先端部が円錐状の第２バンプとが、該先端部をつぶし融
点が前記両バンプよりも低い導電層を介して接続された
ものである。According to the present invention, a first bump provided on a first electronic component and a second bump provided on a second electronic component are provided.
A second bump having a conical tip is crushed at the tip and connected via a conductive layer having a lower melting point than the two bumps.

【０００５】[0005]

【作用】この発明によれば、第１電子部品に設けられた
第１バンプと第２電子部品に設けられた先端部が円錐状
の第２バンプとが、該先端部をつぶし融点が前記両バン
プよりも低い導電層を介して接続しているので、導電層
は溶融し第１および第２バンプは溶融しない加熱温度で
熱圧着した場合、溶融した導電層による横方向への広が
り量を少なく抑えて、両バンプを接続することができ、
したがって例えばＩＣチップの電極のピッチがより一層
微細であっても、相隣接するバンプ間で短絡が発生しな
いようにすることができる。According to the present invention, the first bump provided on the first electronic component and the tip provided on the second electronic component have a conical shape.
And the second bump are connected via a conductive layer having a lower melting point than the two bumps by crushing the tip, so that the conductive layer is melted and the first and second bumps are not melted at a heating temperature. In this case, both bumps can be connected with a small amount of spread in the lateral direction due to the molten conductive layer,
Therefore, for example, even if the pitch of the electrodes of the IC chip is finer, it is possible to prevent a short circuit from occurring between adjacent bumps.

【０００６】[0006]

【実施例】図１はこの発明の一実施例におけるＩＣチッ
プと配線基板の接続前の状態を示したものである。ま
ず、ＩＣチップ２１は、図２〜図７に示す工程を順次経
て製造されている。すなわち、まず図２に示すように、
チップ本体２２の上面にアルミニウム等からなる電極２
３をパターン形成し、電極２３の上面の所定の一部を除
く全上面に保護膜２４を形成する。次に、図３に示すよ
うに、全上面に、チタンとタングステンとからなる合金
の上面にクロムを積層してなるものからなるアンダーバ
ンプメタル２５を形成する。この場合、チタンとタング
ステンとからなる合金の厚さを２０００〜５０００Å程
度とし、クロムの厚さを１０００〜２０００Å程度とす
る。次に、図４に示すように、周知のフォトプロセスに
より、電極２３の上面にほぼ対応する部分を除く全上面
にポジ型もしくはネガ型のフォトレジストからなるメッ
キレジスト２６を１０〜２０μｍ程度の厚さに形成す
る。この状態では、電極２３の上面にほぼ対応する部分
には開口部２７が形成されている。次に、図５に示すよ
うに、周知の銅メッキ方法により、開口部２７における
アンダーバンプメタル２５の上面に銅からなる金属バン
プ２８をメッキレジスト２６の厚さと同程度の厚さに形
成する。次に、図６に示すように、金属バンプ２８の上
面およびその周囲のメッキレジスト２６の上面に、例え
ばスズと鉛との比が６：４の構成であって融点が１８３
℃程度の低融点の半田層２９を５〜１０μｍ程度の厚さ
に形成する。この後、周知の方法によりメッキレジスト
２６を剥離し、次いでこの剥離により露出された不要な
部分のアンダーバンプメタル２５を金属バンプ２８をエ
ッチングマスクとしてエッチングして除去すると、図７
に示すように、金属バンプ２８の下面のみにアンダーバ
ンプメタル２５が残存する状態となる。そして、このよ
うにして製造されたＩＣチップ２１を裏返しにすると、
図１に示すような状態となる。FIG. 1 shows a state before connection between an IC chip and a wiring board according to an embodiment of the present invention. First, the IC chip 21 is manufactured through the steps shown in FIGS. That is, first, as shown in FIG.
Electrode 2 made of aluminum or the like on the upper surface of chip body 22
3, and a protective film 24 is formed on the entire upper surface of the upper surface of the electrode 23 except for a predetermined part. Next, as shown in FIG. 3, an under bump metal 25 is formed on the entire upper surface by laminating chromium on the upper surface of an alloy of titanium and tungsten. In this case, the thickness of the alloy composed of titanium and tungsten is set to about 2000 to 5000 °, and the thickness of chromium is set to about 1000 to 2000 °. Next, as shown in FIG. 4, a plating resist 26 made of a positive or negative photoresist is formed on the entire upper surface except for a portion substantially corresponding to the upper surface of the electrode 23 by a known photo process to a thickness of about 10 to 20 μm. Formed. In this state, an opening 27 is formed at a portion substantially corresponding to the upper surface of the electrode 23. Next, as shown in FIG. 5, a metal bump 28 made of copper is formed on the upper surface of the under bump metal 25 in the opening 27 to a thickness approximately equal to the thickness of the plating resist 26 by a known copper plating method. Next, as shown in FIG. 6, on the upper surface of the metal bump 28 and the upper surface of the plating resist 26 therearound, for example, the ratio of tin to lead is 6: 4 and the melting point is 183.
A solder layer 29 having a low melting point of about 10 ° C. is formed to a thickness of about 5 to 10 μm. Thereafter, the plating resist 26 is peeled off by a known method, and then unnecessary portions of the under bump metal 25 exposed by the peeling are removed by etching using the metal bumps 28 as an etching mask.
As shown in FIG. 7, the under bump metal 25 remains only on the lower surface of the metal bump 28. Then, when the IC chip 21 thus manufactured is turned over,
The state is as shown in FIG.

【０００７】一方、配線基板３１は、樹脂等からなる基
板本体３２の上面に銅等からなる接続パッド３３がパタ
ーン形成され、接続パッド３３の上面の所定の一部を除
く全上面に保護膜３４が設けられ、接続パッド３３の露
出面上に、金、銀、スズ等の半田との密着性の良い金属
からなる金属層３５が設けられ、ここまでは図９に示す
従来のものと同一の構造であるが、さらに金属層３５の
上面に樽状半田部３６ａと円錐状半田部３６ｂとからな
る半田バンプ３６が設けられた構造となっている。この
場合、例えば鉛を９５％以上含む構成であって融点が３
００℃以上の高融点の半田からなる直径が４５μｍ程度
の半田ワイヤを用意し、ボールボンディング法等と呼ば
れる技術を利用することにより、すなわちキャピラリを
用いて半田ワイヤの先端部にボールを形成した後このボ
ールの部分を金属層３５の上面に熱圧着し、次いでキャ
ピラリを持ち上げると、図１に示すように、金属層３５
の上面に水平方向の最大直径が１４０μｍ程度で高さが
７０〜８０μｍ程度の樽状半田部３６ａが形成されると
共に、この樽状半田部３６ａの上面に高さが９０〜１１
０μｍ程度の円錐状半田部３６ｂが形成される。On the other hand, in the wiring board 31, a connection pad 33 made of copper or the like is pattern-formed on an upper surface of a substrate body 32 made of a resin or the like, and a protective film 34 is formed on the entire upper surface except for a predetermined part of the upper surface of the connection pad 33. Is provided on the exposed surface of the connection pad 33, and a metal layer 35 made of a metal having good adhesion to solder such as gold, silver, tin or the like is provided. Up to this point, the same as the conventional one shown in FIG. The structure is such that a solder bump 36 composed of a barrel solder portion 36a and a conical solder portion 36b is further provided on the upper surface of the metal layer 35. In this case, for example, it is configured to contain 95% or more of lead and has a melting point of 3%.
After preparing a solder wire having a diameter of about 45 μm made of a solder having a high melting point of 00 ° C. or higher and using a technique called a ball bonding method, that is, after forming a ball at the tip of the solder wire using a capillary, When this ball portion is thermocompression-bonded to the upper surface of the metal layer 35 and then the capillary is lifted, as shown in FIG.
A barrel-shaped solder portion 36a having a horizontal maximum diameter of about 140 μm and a height of about 70 to 80 μm is formed on the upper surface of the barrel, and a height of 90 to 11 is formed on the upper surface of the barrel-shaped solder portion 36a.
A conical solder portion 36b of about 0 μm is formed.

【０００８】さて、ＩＣチップ２１を配線基板３１上に
搭載する場合には、まず図１に示すように、ＩＣチップ
２１の半田層２９の中心部と配線基板３１の半田バンプ
３６の円錐状半田部３６ｂの頂点とが対向するように位
置合わせを行う。次に、１９０〜２００℃程度の加熱温
度をＩＣチップ２１に加えて熱圧着すると、半田層２９
は溶融するが、半田バンプ３６は溶融せず、このため半
田バンプ３６の樽状半田部３６ａは横方向につぶれない
が、半田バンプ３６は鉛の組成割合が多くて比較的柔ら
かいので、その円錐状半田部３６ｂがＩＣチップ２１の
半田層２９を介して金属バンプ２８によって適宜に押し
つぶされることになる。この結果、図８に示すように、
半田バンプ３６の円錐状半田部３６ｂの上面が半田層２
９の下面に沿うようにつぶれ、このつぶれた円錐状半田
部３６ｂの上面に、一旦溶融した後冷却されて固化した
半田層２９の下面が固着される。この場合、一旦溶融し
た後冷却されて固化した半田層２９は、溶融した際の表
面張力により、金属バンプ２８の下面とつぶれた円錐状
半田部３６ｂの下面との間のみに介在される。かくし
て、ＩＣチップ２１が配線基板３１上に搭載される。When the IC chip 21 is mounted on the wiring board 31, first, as shown in FIG. 1, the center of the solder layer 29 of the IC chip 21 and the conical solder of the solder bump 36 of the wiring board 31 are used. Positioning is performed so that the apex of the portion 36b is opposed. Next, a heating temperature of about 190 to 200 ° C. is applied to the IC chip 21 and thermocompression bonding is performed.
Is melted, but the solder bump 36 is not melted, so that the barrel-shaped solder portion 36a of the solder bump 36 is not crushed in the lateral direction. The solder portion 36b is appropriately crushed by the metal bump 28 via the solder layer 29 of the IC chip 21. As a result, as shown in FIG.
The upper surface of the conical solder portion 36b of the solder bump 36 is the solder layer 2
The lower surface of the solder layer 29 that has been melted, cooled, and solidified is fixed to the upper surface of the crushed conical solder portion 36b. In this case, the solder layer 29 that has been melted and then cooled and solidified is interposed only between the lower surface of the metal bump 28 and the lower surface of the crushed conical solder portion 36b due to the surface tension at the time of melting. Thus, the IC chip 21 is mounted on the wiring board 31.

【０００９】このように、配線基板３１の高融点の半田
バンプ３６を溶融させないので、その樽状半田部３６ａ
を横方向につぶすことなく、半田バンプ３６の円錐状半
田部３６ｂのみをＩＣチップ２１の溶融した低融点の半
田層２９を介して金属バンプ２８によって適宜に押しつ
ぶしているだけであるので、半田バンプ３６が全体とし
て横方向に広がらないようにすることができる。換言す
れば、溶融するのは低融点の半田層２９だけであるの
で、この溶融した半田層２９による横方向への広がり量
を少なく抑えることができる。この結果、ＩＣチップ２
１の電極２３のピッチが１００〜１５０μｍ程度とより
一層微細であっても、相隣接する半田バンプ３６間で短
絡が発生しないようにすることができる。As described above, since the high melting point solder bump 36 of the wiring board 31 is not melted, the barrel-shaped solder portion 36a
Only the conical solder portion 36b of the solder bump 36 is appropriately crushed by the metal bump 28 via the melted low melting point solder layer 29 of the IC chip 21 without crushing the solder bump 36 in the lateral direction. 36 can be prevented from spreading as a whole in the lateral direction. In other words, since only the low melting point solder layer 29 is melted, the amount of the molten solder layer 29 spreading in the horizontal direction can be reduced. As a result, IC chip 2
Even if the pitch of the one electrode 23 is as fine as about 100 to 150 μm, it is possible to prevent a short circuit from occurring between the adjacent solder bumps 36.

【００１０】[0010]

【発明の効果】以上説明したように、この発明によれ
ば、第１電子部品に設けられた第１バンプと第２電子部
品に設けられた先端部が円錐状の第２バンプとが、先端
部をつぶし融点が前記両バンプよりも低い導電層を介し
て接続しているので、バンプ全体は横方向に広げること
なく、且つ、導電層は溶融し第１および第２バンプは溶
融しない加熱温度で熱圧着した場合、溶融した導電層に
よる横方向への広がり量を少なく抑えて、両バンプを接
続することができ、したがって例えばＩＣチップの電極
のピッチがより一層微細であっても、相隣接するバンプ
間で短絡が発生しないようにすることができる。As described above, according to the present invention, the first bump provided on the first electronic component and the second bump provided on the second electronic component and having a conical tip are formed by the tip.
Since the parts are crushed and connected via a conductive layer whose melting point is lower than both of the bumps, the entire bumps must be spread in the horizontal direction.
In addition, when the conductive layer is melted and the first and second bumps are thermocompressed at a heating temperature at which the first and second bumps are not melted, both bumps can be connected while suppressing the amount of spread in the lateral direction due to the melted conductive layer. Therefore, for example, even if the pitch of the electrodes of the IC chip is finer, it is possible to prevent a short circuit from occurring between adjacent bumps.

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明の一実施例におけるＩＣチップと配線
基板の接続前の状態の断面図。FIG. 1 is a cross-sectional view of a state before connection between an IC chip and a wiring board according to an embodiment of the present invention.

【図２】ＩＣチップの製造に際し、チツプ本体の上面に
電極および保護膜を形成した状態の断面図。FIG. 2 is a cross-sectional view showing a state in which an electrode and a protective film are formed on an upper surface of a chip body in manufacturing an IC chip.

【図３】ＩＣチップの製造に際し、全上面にアンダーバ
ンプメタルを形成した状態の断面図。FIG. 3 is a cross-sectional view showing a state where an under bump metal is formed on the entire upper surface in manufacturing an IC chip.

【図４】ＩＣチップの製造に際し、メツキレジストを形
成した状態の断面図。FIG. 4 is a cross-sectional view showing a state in which a plating resist is formed in manufacturing an IC chip.

【図５】ＩＣチップの製造に際し、金属バンプを形成し
た状態の断面図。FIG. 5 is a cross-sectional view showing a state in which metal bumps are formed in manufacturing an IC chip.

【図６】ＩＣチップの製造に際し、低融点の半田層を形
成した状態の断面図。FIG. 6 is a cross-sectional view showing a state where a low-melting-point solder layer is formed during the manufacture of an IC chip.

【図７】ＩＣチップの製造に際し、メッキレジストおよ
び不要な部分のアンダーバンプメタルを除去した状態の
断面図。FIG. 7 is a cross-sectional view showing a state where a plating resist and unnecessary portions of under bump metal are removed in manufacturing an IC chip.

【図８】ＩＣチップと配線基板の接続後の状態の断面
図。FIG. 8 is a sectional view of a state after the connection between the IC chip and the wiring board;

【図９】従来例におけるＩＣチップと配線基板の接続後
の状態の断面図。FIG. 9 is a cross-sectional view of a state after connection of an IC chip and a wiring board in a conventional example.

【符号の説明】[Explanation of symbols]

２１ ＩＣチップ ２２ 電極 ２８ 金属バンプ ２９ 半田層 ３１ 配線基板 ３３ 接続パッド ３６ 半田バンプ DESCRIPTION OF SYMBOLS 21 IC chip 22 Electrode 28 Metal bump 29 Solder layer 31 Wiring board 33 Connection pad 36 Solder bump

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 第１電子部品に設けられた第１バンプと
第２電子部品に設けられた先端部が円錐状の第２バンプ
とが、該先端部をつぶし融点が前記両バンプよりも低い
導電層を介して接続されたことを特徴とする電子部品の
接続構造。A first bump provided on a first electronic component and a second bump having a conical tip provided on a second electronic component crush the tip and have a lower melting point than the two bumps. A connection structure for electronic components, wherein the connection structure is connected via a conductive layer. 【請求項２】 請求項１記載の発明において、前記第１
バンプは銅からなり、前記第２バンプは半田からなり、
前記導電層は融点が前記第２バンプの半田よりも低い半
田からなることを特徴とする基板の接続構造。2. The method according to claim 1, wherein the first
The bump is made of copper, the second bump is made of solder,
The connection structure of a substrate, wherein the conductive layer is made of solder having a melting point lower than that of the solder of the second bump. 【請求項３】 請求項１または２記載の発明において、
前記第１電子部品はＩＣチップからなり、前記第２電子
部品は配線基板からなることを特徴とする電子部品の接
続構造。3. The method according to claim 1, wherein
The first electronic component is formed of an IC chip, and the second electronic component is formed of a wiring board.
JP9076716A 1997-03-13 1997-03-13 Connection structure of electronic components Expired - Fee Related JP2893634B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9076716A JP2893634B2 (en) 1997-03-13 1997-03-13 Connection structure of electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9076716A JP2893634B2 (en) 1997-03-13 1997-03-13 Connection structure of electronic components

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3581392A Division JP2789910B2 (en) 1992-01-28 1992-01-28 IC chip connection structure and method

Publications (2)

Publication Number Publication Date
JPH1012659A JPH1012659A (en) 1998-01-16
JP2893634B2 true JP2893634B2 (en) 1999-05-24

Family

ID=13613291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9076716A Expired - Fee Related JP2893634B2 (en) 1997-03-13 1997-03-13 Connection structure of electronic components

Country Status (1)

Country Link
JP (1) JP2893634B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858941B2 (en) * 2000-12-07 2005-02-22 International Business Machines Corporation Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array
US7235886B1 (en) 2001-12-21 2007-06-26 Intel Corporation Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby
US20030116860A1 (en) 2001-12-21 2003-06-26 Biju Chandran Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses
JP3905100B2 (en) 2004-08-13 2007-04-18 株式会社東芝 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH1012659A (en) 1998-01-16

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