JP2873134B2 - Nonlinear delay feedback type digital oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonlinear delay feedback type digital oscillation circuit.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing a basic configuration of a conventional nonlinear delay feedback type oscillation circuit. As shown in FIG. 11, a nonlinear element 101 having a nonlinear input / output characteristic f
, An amplifier 102 having an amplification degree μ, and a signal x having an impulse response characteristic h (t).
A linear portion composed of an impulse response circuit 103 outputting (t) and a delay circuit 104 having a delay time Tr is electrically connected in cascade in a loop LP shape.
The output signal x (t) in the nonlinear delay feedback oscillation circuit configured as described above can be expressed by the following equation (1).

[0003]

X (t) = μh (t) * f (x (t−Tr)) = ∫− _∞ ⁺ ∞μ · h (t−τ) · f (x (τ−Tr)) dτ where , * Represent convolution integral.

FIG. 12 is a block diagram of a conventional nonlinear delay feedback type photoelectric hybrid oscillation circuit using an optical fiber cable as a delay feedback path. As shown in FIG. 12, an optical signal output from the light source 201 is intensity-modulated by an electro-optic modulator 207 based on an electric signal output from an analog filter 206, and then transmitted through a delay line 208 formed of an optical fiber cable. Input to the photodetector 204 via the The photodetector 204 detects an input optical signal and converts it into an electric signal, and then passes through an electro-optic modulator 205 via a DC amplifier 205 having a predetermined amplification factor and an analog filter 206 having a predetermined time response characteristic. 207. Here, the impulse response h (t) of the feedback loop
Is determined by the time response characteristic of the filter 6, and the loop gain μ is determined by the gain of the DC amplifier 205 and the light intensity of the optical signal from the light source 201.

Further, an adaptive control method of a signal generator for changing an oscillation mode and an oscillation signal in accordance with an external condition in a nonlinear delay feedback type oscillation circuit is disclosed by Peter Davis, one of the inventors of the present invention, in Japanese Patent Laid-Open Publication No. HEI 9-279,086. 4-142
No. 519. This method evaluates the output signal according to any external evaluation method in a signal generator in which a chaotic transition that goes through all of the oscillation modes that were originally stable occurs by increasing the excitation parameter. At this time, the excitation parameter is adjusted up and down according to the magnitude of the error amount so that a mode with a small error is selected. Regarding the function when this control method is applied,
The inventors of the present application have confirmed that a signal generator of an analog circuit is manufactured to change an oscillation waveform (for example, Aida Tato and Peter Davis "Possibility of application from branch to chaos" : Experimental demonstration of a method for switching between multistable modes in nonlinear resonators (Applicability of bifurcation to Chaos: Experi)
mental Demonstration of Methods for SwitchingAmong
Multistable Modes in a Nonlinear Resonator ", Optical Society of America (OSA), Proceedings on Nonlinear Resonator
Dynamics in Optical Systems, V
ol. 7, 1991).

[0006]

In the conventional nonlinear delay feedback type photoelectric hybrid oscillation circuit, the nonlinear characteristic is determined by the modulation characteristic of the electro-optic modulator 1 and the light intensity of the optical signal from the light source 201. , It is not possible to realize an arbitrary nonlinear characteristic by changing the nonlinear characteristic,
Further, the nonlinear characteristic cannot be dynamically changed. Further, since the impulse response characteristics are realized by using the analog filter 206, the impulse response characteristics cannot be dynamically changed. Further, the DC amplifier 20
5 cannot be dynamically changed with high precision.

Further, when chaos oscillation is caused in a signal generator of an analog circuit manufactured by using the above control method, the same oscillation trajectory can be reproduced by perturbation such as internal noise in the circuit. There was a problem that it was not possible.

A first object of the present invention is to solve the above problems, to stably oscillate with higher accuracy as compared with the conventional example, to reproduce the same oscillation trajectory, and It is an object of the present invention to provide a nonlinear delay feedback type oscillation circuit which can automatically change an oscillation waveform in accordance with an externally set parameter.

A second object of the present invention is to provide a nonlinear delay feedback oscillation circuit which can change various parameters of the nonlinear delay feedback oscillation circuit and can oscillate in various oscillation modes. .

[0010]

[0011]

According to a first aspect of the present invention, there is provided a non-linear delay feedback type digital oscillating circuit which stores data having a predetermined non-linear characteristic at each address and stores the data based on an input address. First storage means for outputting data, digital multiplication means for multiplying input data by multiplier data of a predetermined amplification degree and outputting product data, and a predetermined filtering coefficient for the input data A digital filtering unit that performs impulse response processing based on data and outputs filtered data after filtering, and has a write port and a read port, and stores the input data through the write port. Second storage means for outputting the stored data through the read port, and outputting the data stored in the second storage means via the read port Control for controlling the second storage means so as to write and read data by delaying a predetermined timing by a predetermined delay time from a timing of inputting and storing the data via the write port of the second storage means. Means, the first storage means, the digital multiplying means, the digital filtering means, and the second
Is electrically connected in cascade so as to form a feedback path of an oscillation loop, and the nonlinear delay feedback digital oscillation circuit further includes an oscillation signal oscillated in the nonlinear delay feedback digital oscillation circuit. Parameter detection means for detecting a predetermined parameter of the oscillation signal based on the data, and multiplication data of the amplification degree for each difference between a parameter detected by the input external setting parameter and the parameter detected by the parameter detection means. A third memory for storing characteristic data and outputting multiplied data of the amplification degree to the digital multiplying means based on a parameter difference between an externally set parameter inputted and a parameter detected by the parameter detecting means; Means.

Further, the nonlinear delay feedback type digital oscillating circuit according to the second aspect of the present invention is the nonlinear delay feedback type digital oscillating circuit according to the first aspect, further comprising: the data of the nonlinear characteristic, the multiplication data of the amplification degree, and A data changing means for changing at least one of the filtering coefficient data and the delay time is provided.

[0013]

[0014]

For example, the first storage means, the digital multiplication means, the digital filtering means, and the second storage means are electrically connected in such an order that a feedback path of an oscillation loop is formed. Assume that they are connected in cascade. Here, the first storage means outputs the stored data to the digital multiplication means based on the address output and input from the read port of the second storage means, and the digital multiplication means The data input from the first storage means is multiplied by multiplier data of a predetermined amplification degree, and the product data is output to the digital filtering means. Next, the digital filtering means performs an impulse response process on the data input from the digital multiplication means based on predetermined filtering coefficient data, and filters the data after the filtering into the second data.
Output to the write port of the storage means. Further, the second storage means stores the data input from the digital filtering means via the write port via the write port, and then stores the stored data via the read port. 1 to the storage means.
Here, the control means determines the timing at which the data stored in the second storage means is output via the read port from the timing at which the data is input and stored via the write port of the second storage means. The second storage means is controlled so as to write and read data with a delay of a delay time. Further, the parameter detecting means detects a predetermined parameter of the oscillation signal based on data of the oscillation signal oscillated in the non-linear delayed feedback digital oscillation circuit, and the third storage means
The data of the characteristic of the multiplication data of the amplification degree for each difference of the parameter between the input external setting parameter and the parameter detected by the parameter detecting means is stored, and the input external setting parameter and the parameter detecting means The multiplication data of the amplification degree is output to the digital multiplication means based on a difference between the detected parameter and the detected parameter.

Therefore, the first storage means, the digital multiplication means, the digital filtering means, and the second storage means are electrically connected in cascade so as to form a feedback path of an oscillation loop. Thereby, a nonlinear delay feedback type digital oscillation circuit is formed, and the feedback path of the oscillation loop is based on the nonlinear characteristic data, the amplification multiplication data, the filtering coefficient data, and the delay time. , A nonlinear delay type oscillation occurs, and for example, data of an oscillation signal can be obtained from the digital filtering means. Since the circuit of the present invention is composed of a digital circuit, it can oscillate with higher accuracy and stability than the conventional example, and can reproduce the same oscillation trajectory. In addition, the oscillation waveform can be automatically changed according to parameters set externally.

Also, in the nonlinear delay feedback type digital oscillation circuit according to the second aspect, the data changing means may include a data of the nonlinear characteristic, a product of the amplification factor, the filtering coefficient data, and the delay time. At least one of them
Change two data. Therefore, various parameters of the nonlinear delay feedback type oscillation circuit can be changed, and oscillation can be performed in various oscillation modes.

[0017]

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a nonlinear delay feedback type digital oscillation circuit according to an embodiment of the present invention. When the above equation 1 representing the operation of the nonlinear delay feedback system is converted into a discrete equation, the following equation 2 representing the oscillation signal x (n) represented by the time variable n is obtained.

[0020]

X (n) = μh (n) * f (x (n−nr)) = Σμ · h (nk) · f (x (k−nr)) where Σ is k = − Is the sequence sum from ∞ to + 、, n
r is the number of delay stages corresponding to the delay time Tr, and h (n)
Is a discrete impulse response corresponding to h (t). Here, t = Tc · n (Tc is the cycle of the clock signal).

The nonlinear delay feedback type digital oscillation circuit according to the present embodiment is configured based on the above equation (2), and stores (a) data Dm of the nonlinear characteristic which operates as the nonlinear element 101 as shown in FIG. (B) a digital multiplier which operates as an amplifier 102 and multiplies input data Dm by input amplification data Dμ and outputs product data 12, and (c) a digital filter 13 operating as an impulse response circuit 103;
(D) The dual-port RAM 14, which operates as the delay circuit 104, is electrically connected in cascade to provide a loop LP of a delay feedback path for nonlinear oscillation, and each of the circuit elements 11, 12, 13, 14 Is controlled by a microprocessor unit (hereinafter, referred to as MPU) 10 which is an arithmetic control circuit, as will be described later in detail.

An oscillation waveform evaluation circuit 40 counts the number of pulses equal to or higher than a predetermined threshold voltage Vth of the oscillation signal generated by the oscillation circuit and evaluates the oscillation waveform.
Lookup table that outputs data Dμ2 of a predetermined amplification degree based on the absolute value of the difference between the pulse count value data Dcc output from the evaluation circuit 40 and the data Ds set by the MPU 10. ROM
(Hereinafter, referred to as a table ROM) 53 is provided.

In the oscillation circuit of this embodiment, a clock signal generating circuit (not shown) is provided for operating each circuit element, and a clock signal of a predetermined frequency is supplied from the circuit to each circuit element. .

The operation of the delay feedback type digital oscillation circuit of the present embodiment is represented by a delay differential equation, and starts oscillating when the delay feedback gain exceeds a predetermined threshold value. Here, assuming that the delay time of feedback is Tr, the oscillation circuit
A fundamental wave having a period T ₁ = 2Tr and an oscillation signal of an nth harmonic having a period T _n = T ₁ / n (n is a positive odd number) can be oscillated. Further, if the branch order is a positive integer m, the waveform of the oscillation signal is split into 2 ^(m-1) peaks and valleys with increasing delay feedback gain. A so-called “double-period branching” occurs, in which the modulation cycle of the modulation cycle is shifted to an oscillation state of 2 ^(m−1) T ₁ one after another. A label (n, m) indicated by the harmonic order n and the branch order m is given to each oscillation state of the “double period branch”, and the oscillation of the m-th branch of the n-th harmonic will be described below. n, m) oscillation. In (n, m) oscillation, the difference in the arrangement of peaks or valleys with different levels
If the phase can be specified, there are 2 ^{n (m-1)} oscillation states.

SRAM 1 for storing non-linear characteristic data
1 are controlled by the MPU 10 and the address terminals An of the SRAM 11
And a data selector 32 for selecting data to be input / output to / from the data terminal Dn of the SRAM 11.

When non-linear characteristic data is stored in the SRAM 11, the MPU 10 controls the data selectors 31 and 32.
To the terminal A side, and the MPU 10 outputs the H level write signal to the write / read control terminal W /
R to put the SRAM 11 in the write state. At this time, the non-linear characteristic data Dm is transmitted from the MPU 10 to the data terminal D via the terminal A of the terminal 32 of the data selector 32.
n, and address data Da for storing the data Dm is input from the MPU 10 to the address terminal An via the terminal A of the data selector 31,
As a result, the data of the non-linear characteristic is stored in each address.

FIG. 3 is a graph showing an example of nonlinear characteristic data stored in the SRAM 11 of FIG. In FIG. 3, the data Dm of the nonlinear characteristic is 0000 in 16 bits.
It is displayed in a range from h to FFFFh (where h represents a hexadecimal number), and the amplification degree μ corresponds to a range from 0.0 to 0.999985.

On the other hand, in the oscillation operation state, the MPU 10
Switches the data selectors 31 and 32 to the terminal B side, and the MPU 10 outputs an L level write signal to the SRAM 1
1 to the write / read control terminal W / R of the SRAM 11
Is set to the read state. At this time, the dual port RA
The data Dr read from the second data terminal D2n of M14 is transferred to the SRAM via the terminal B of the data selector 31.
11 is input to the address terminal An, and the address Dr
Is read from the SRAM 11 and input to the first input terminal of the digital multiplier 12 via the terminal B of the data selector 32.

Digital multiplier 12 operating as an amplifier
Selector 33 and latch circuit 3 as peripheral circuits of
4 are provided. The MPU 10 temporarily stores the data Dμ1 having the fixed amplification degree in the latch circuit 34,
Data selector 33 whose selection is controlled by 10
Through the terminal A of the digital multiplier 12 as the data Dμ of the amplification degree. Data Dμ2 read from a table ROM 53, which will be described in detail later, is supplied to the digital multiplier 12 via a terminal B of the data selector 33.
Is output to the second input terminal. Therefore, when setting a constant amplification degree, the MPU 10 switches the data selector 33 to the terminal A, while dynamically changing the amplification degree data μ over time using the oscillation waveform evaluation circuit 40, The data selector 33 is switched to the terminal B. The digital multiplier 12 multiplies the data Dm input to the first input terminal by the data Dμ input to the second input terminal, and outputs the multiplication result data to the data input terminal DI of the digital filter 13.

The digital filter 13 operating as an impulse response circuit performs a predetermined impulse response filtering process on the data input to the data input terminal DI, and outputs the processed data Dd from the data output terminal DO to the dual port RAM 14. Of the first data terminal D1
n, a digital oscillation output terminal 61, and a digital / analog converter (hereinafter, referred to as a D / A converter) 16. Here, the coefficient value data Dc in the filtering processing is input from the MPU 10 to the coefficient data input terminals CDI1-4 of the digital filter 13, and is temporarily stored. Next, the D / A converter 16 D / A converts the input oscillation signal data Dd and converts the data Dd into an analog voltage signal Va.
And outputs it to the analog oscillation output terminal 62 and the threshold value processor 41 in the oscillation waveform evaluation circuit 40.

FIG. 2 is a block diagram showing an example of the digital filter 13 shown in FIG. As shown in FIG. 2, the data Dc of the coefficient value output from the MPU 10 is, for example, data C
a, Cb0, Cb1, Cc, and these data are respectively supplied from the MPU 10 to the coefficient data input terminal CDI1.
-4, which are input to the latch circuits 71 to 74 and temporarily stored therein, and thereafter, the digital multipliers 66, 63, 67,
61 is set as multiplier data.

The data input through the data input terminal DI is multiplied by the multiplier data Cc by the digital multiplier 61, and the multiplication result data is stored in the first adder of the digital adder 62.
Input terminal. On the other hand, the multiplication result data output from the digital multiplier 66 is input to the second input terminal of the adder 62. The digital adder 62 adds the data input to the first input terminal and the data input to the second input terminal, and outputs the addition result data to the digital multiplier 63 and a one-clock delay circuit (hereinafter, referred to as a “multiplier”). (Referred to as a delay circuit). The delay circuit 65 delays the input data by the time of one clock of the clock signal, and outputs the data to the digital multipliers 66 and 67. The digital multiplier 63 adds multiplier data Cb0 to the input data.
, And then multiplies the resulting data by a digital adder 64.
To the first input terminal. The digital multiplier 6
6 multiplies the input data by the multiplier data Ca, and outputs the resulting data to the second input terminal of the digital adder 62. Further, the digital multiplier 67 multiplies the input data by the multiplier data Cb1, and then outputs the multiplied data to the second input terminal of the digital adder 64. Further, the digital adder 64 adds the data input to the first input terminal and the data input to the second input terminal, and outputs the added data as output data via the data output terminal DO. Output.

The operation of the filtering process of the digital filter 13 configured as described above is performed by converting input data into x
(N), and the output data is y (n).

Y (n) = h (n) * x (n) = {h (nk) × (k) Here, Σ in the second expression of Expression 3 is from k = −∞ to + ∞. Is the sequence sum of.

FIG. 4 is a graph showing an example of the impulse response characteristic of the digital filter 13 shown in FIG. 2, which is the characteristic of the impulse response signal h (n) with respect to the time variable n. This impulse response signal h (n) is expressed by the following equation (4).

Equation 4] h (n) = Cb0 · Ca n · u (n) + Cb1 · Ca n-1 · u (n-1) where, u (n) is the unit step function, the number of the next 5
Is represented by

U (n) = 1; When n ≧ 0 = 0; When n <0

In this embodiment, the delay time in the delay circuit 65 is fixed in advance, but the present invention is not limited to this, and the delay time in the delay circuit 65 may be set by the MPU 10.

The operation of the dual port RAM 14 configured as a delay circuit is controlled by a memory control circuit 20 including an up counter 21, an AND gate 22, and an up counter 23. Up counter 21
Counts a clock signal output from the clock signal generation circuit, and uses the data Ar of the counted value as address data of a write address in parallel with the dual port RA.
The signal is output to the first address terminal of M14 and is input in parallel to the first input terminal of the match detection circuit 22. The maximum value of the count value of the up counter 21 is set to the maximum value of the address of the dual port RAM 14,
After the up counter 21 counts the maximum address, the count value becomes zero. Data Dnr having the number of delay stages nr is input from the MPU 10 to the second input terminal of the AND gate 22 in parallel.

As shown in FIG. 13, the coincidence detecting circuit 22
16 exclusive NOR gates (hereinafter referred to as EXNO
It is called R gate. ) 22b-1 to 22b-16 and 1
And 22 gates. Data A input from the up counter 21 via the first input terminal
r is input to the first input terminal of the EXNOR gate 22b-1, and the second bit of the data Ar is set to E.
The data is input to the first input terminal of the XNOR gate 22b-2, and similarly, the third to sixteenth data of the data Ar is input.
Bits are EXNOR gates 22b-3 to 22b, respectively.
It is input to each first input terminal of b-16. On the other hand, MP
Data D input from U10 via the second input terminal
The first bit of nr is the second bit of EXNOR gate 22b-1.
, And the second bit of the data Dnr is input to the second input terminal of the EXNOR gate 22b-2. Similarly, the third to sixteenth bits of the data Dnr are respectively input to the EXNOR gate 22b. -3 to 22b-16 are input to the second input terminals. EXN
A signal output from each output terminal of the OR gates 22b-1 to 22b-16 is input to each input terminal of the AND gate 22a, and a match detection signal output from the output terminal of the AND gate 22a is a clear input of the up counter 23. Output to terminal CL.

The coincidence detection circuit 22 raises the H level coincidence detection signal when the address data Ar input to the first input terminal matches the data Dnr of the number of delay stages nr input to the second input terminal. It outputs to the clear input terminal CL of the counter 23. The up counter 23 counts the clock signal in the same manner as the up counter 21. However, the count value is cleared to 0 by the coincidence detection signal, so that the up counter 23 lags behind the count value of the up counter 21 by the data Dnr. The data of the counted value is output to the second address terminal A2n of the dual port RAM 14 as the address data of the read address. Here, the first data terminal D1n is always set to the data write state, while the second data terminal D2n
Is always set to the data read state.

The dual port R configured as described above
In the circuit of the AM 14 and the memory control circuit 20, the address data of the write address counted by the up counter 21 is counted with a delay of the data Dnr of the number nr of delay stages, and the count value is used as the address data of the read address. Therefore, the memory control circuit 20 writes the data Dd from the digital filter 13 to the dual port RAM 14 and then reads the data Dd and sets it as data Dr.
The timing of writing to the address terminal An of the SRAM 11 via the terminal B of the SRAM 11 can be shifted by the predetermined number of delay stages nr, whereby the data Dd written to the dual-port RAM 14 can be shifted by the delay time Tr = nr.times.Tc (where Tc is the cycle of the clock signal) to delay the dual port RA.
Since data can be read from M14 and written to SRAM 11, a delay circuit can be configured.

FIG. 9 is a graph for explaining the operation of the oscillation waveform evaluation circuit 40 of FIG. 1, and shows two stable oscillation modes of the (3, 2) oscillation modes output from the D / A converter 16. Of the third harmonic oscillation signal which is one of
Is a graph showing a voltage signal Va of the example of FIG. 1, a voltage signal S1 outputted from the threshold value processor 41, and a voltage signal S2 outputted from the pulse width expander 42, and FIG. 10 shows the oscillation waveform of FIG. 6 is a graph for explaining the operation of the evaluation circuit 40, which is another one of two stable oscillation modes of the (3, 2) oscillation modes output from the D / A converter 16, and is a triple. Voltage signal Va of second example of harmonic oscillation signal
And the voltage signal S1 output from the threshold processor 41
5 is a graph showing a voltage signal S2 output from a pulse width expander 42.

The oscillation waveform evaluation circuit 40 comprises a threshold value processor 41, a pulse width expander 42, and a counter 43. As shown in FIG. 9 and FIG. 10, the threshold value processor 41 extracts only a voltage signal equal to or higher than the threshold voltage Vth and converts the extracted voltage signal into S1 and a pulse width expander 42.
Output to Next, the pulse width expander 42 determines that the pulse width of each pulse of the input voltage signal S1 is, for example, 1.2 Tr.
And the voltage signal S2 after the pulse width expansion.
Is output to the counter 43. Here, Tr is the delay time as described above, and is (clock signal period Tc) ×
(Number of delay stages nr). Clear pulse generator 44
Generates a positive-polarity clear pulse having a pulse width Tc / 2 with a cycle of Tcl = 20 Tr and outputs it to the clear terminal CL of the counter 43. Here, the counter 43 resets its count value to 0 by the fall of the clear pulse of the period Tcl, counts the input voltage signal S2, and outputs the count value data as the number of high peak levels, discrete Oscillation parameter data Dc representing waveform characteristics such as degrees
It outputs to the subtraction input terminal of the digital adder 51 via the latch circuit 45 as c. Here, the latch circuit 45 latches the count value of the counter 43 immediately before being cleared by the rise of the clear pulse generated from the clear pulse generator 44.

Here, the pulse width expander 42 is shown in FIG. 9 and FIG.
It is provided to extract the parameters of the oscillation waveform that distinguishes the oscillation signals of the two (3, 2) oscillation modes indicated by 0. For example, if the pulse width expander 42 is not provided, the oscillation parameter data Dcc is the same as is apparent from FIGS.

The data Ds of the reference amplification factor, which is an externally set parameter when changing the amplification factor μ, which is an oscillation parameter, for example, when obtaining a chaos oscillation signal, is temporarily stored in the latch circuit 35 from the MPU 10, The signal is input to the addition input terminal of the adder 51. Digital adder 51
Is obtained by subtracting the oscillation parameter data Dcc inputted to the subtraction input terminal from the data Ds inputted to the addition input terminal, and giving the data of the subtraction result via an absolute value calculator 52 which computes and outputs the absolute value thereof. The data is output to the address terminal of the table ROM 53 as data Dab. The data Dμ2 of the amplification degree μ read from the table ROM 53 is supplied to the digital multiplier 1 via the terminal B of the data selector 33.
2 is input to the second input terminal.

FIG. 8 is a graph showing an example of the amplification degree data Dμ2 stored in the table ROM 53 of FIG. As is apparent from FIG. 8, when the address Dab is 0, the data Dμ2 of the amplification μ stored in the table ROM 53 is smaller than the threshold amplification μth between the stable oscillation and the chaos oscillation and stably oscillates. Initial value amplification μ
When the address Dab increases, the data Dμ2 is set to increase monotonically and reach the maximum amplification value μs via the threshold amplification degree μth.

In the non-linear feedback oscillation type digital oscillating circuit configured as described above, when the amplification μ is to be constant, the MPU 10 switches to select the terminal A of the data selector 33, and the constant amplification μ Data Dμ1
Is set in the latch circuit 34. As a result, the circuit operates as an oscillation circuit with a constant loop gain, digital data oscillation data is obtained from the digital oscillation output terminal 61, and an analog voltage oscillation signal is obtained from the analog oscillation output terminal 62.

When dynamically changing the amplification degree data μ with the lapse of time using the oscillation waveform evaluation circuit 40, the MPU 10 switches the data selector 33 to select the terminal B, and sets an externally set parameter. Is set in the latch circuit 35 from the MPU 10. At this time, when the data Ds and the data Dcc do not match, the data Dab increases and the amplification μ in the oscillation circuit is set to be larger than the threshold amplification μth, and the oscillation signal The waveform changes. On the other hand, when the data Ds and the data Dcc are close to each other, the data Dab decreases and decreases, and at that time, the amplification μ decreases and the oscillation waveform changes gradually.
Further, when the data Ds and the data Dcc match,
The data Dab becomes 0, and stable oscillation is achieved with the initial value amplification degree μ0. That is, by operating as described above, the oscillation waveform can be automatically changed in accordance with the data Ds of the reference amplification degree which is a parameter set externally.

Further, the result of an experiment in which each data line in the oscillation circuit of this embodiment is constituted by a 16-bit line and a seventh harmonic is oscillated will be described below.

Generally, in the region of the stable oscillation mode, many oscillation modes can be oscillated even with the same amplification value, and the multi-stable mode is set. At this time, oscillation is selectively performed in one oscillation mode. For example, for the seventh harmonic,
(7,1) oscillation, (7,2) oscillation, (7,3) oscillation,
(7, 4) Oscillation is stable without oscillation in oscillation modes such as. In an experiment using the circuit of the present embodiment by the inventor, among these oscillation modes, (7, 1)
Oscillation, (7, 2) oscillation, and (7, 3) oscillation were confirmed to be stable. FIG. 5 shows that μ = 0.0 generated by the nonlinear delay feedback type digital oscillation circuit of this embodiment.
The oscillation waveform of (7, 3) oscillation at 763 is shown.

Next, although the oscillation of the seventh harmonic itself is stable, it may change between various oscillation modes, and as a result, the oscillation waveform may fluctuate. And described as (7, c) oscillation. FIG. 6 shows an oscillation waveform of the (7, c) oscillation when μ = 0.804, generated by the nonlinear delay-feedback digital oscillation circuit of the present embodiment. As is clear from FIG. 6, in the (7, c) oscillation, the oscillation waveform fluctuates, and various waveforms having characteristics of the (7, 2) oscillation and the (7, 3) oscillation are successively generated. You can see that it appears.

Further, a harmonic having a messy oscillation waveform in which the order of the oscillating harmonic is unclear is simply referred to as chaos oscillation. FIG. 7 shows an oscillation waveform of chaotic oscillation when μ = 0.916 generated by the nonlinear delay feedback type digital oscillation circuit of this embodiment.

As described above, since the nonlinear feedback digital oscillation circuit is constituted by using the SRAM 11, the digital multiplier 12, the digital filter 13 and the dual port RAM 14, the data of the amplification μ, which is an oscillation parameter, respectively. Dμ, the data Dm of the non-linear characteristic stored in the SRAM 11, the coefficient value data Dc of the digital filter 13, and the number of delay stages nr in the delay circuit of the dual port RAM 14 are set with higher accuracy as compared with the conventional analog oscillation circuit. You can change the settings,
It has a unique advantage that it is possible to stably oscillate in various oscillation modes and reproduce oscillations of the same oscillation orbit. Therefore, it is possible to reproduce an oscillation waveform that draws a complex vibration trajectory such as chaotic oscillation.

In the above embodiment, the SRAM 11, the digital multiplier 12, the digital filter 13, and the dual port RAM 14 are replaced by the SRAM 11, the digital multiplier 1
2, digital filter 13, and dual port RAM 14
Are electrically connected in this order, but the present invention is not limited to this, and the order of electrical connection is not limited to this.

In the above embodiments, the digital filter 13 is used. However, the present invention is not limited to this. DSP).

In the above embodiment, the table ROM 53 for storing the data Dμ2 of the amplification degree μ is used.
The present invention is not limited to this. For example, an SRAM may be used instead of the table ROM 53, and the data to be written into the SRAM may be configured to be changeable similarly to the SRAM 11.

In the above embodiment, an example in which the data Dμ of the amplification μ is dynamically changed has been described. However, the present invention is not limited to this. , The nonlinear characteristic data Dm stored in the SRAM 11, the coefficient value data Dc of the digital filter 13, and the number of delay stages nr in the delay circuit of the dual port RAM 14 may be dynamically changed.

[0056]

As described above in detail, according to the nonlinear delay feedback type digital oscillation circuit according to the first aspect of the present invention,
First addressing means for storing data of a predetermined nonlinear characteristic at each address and outputting the stored data based on the input address, and multiplying the input data by multiplier data of a predetermined amplification degree Digital multiplying means for outputting product data, digital filtering means for performing impulse response processing on input data based on predetermined filtering coefficient data and outputting filtered and filtered data, and a write port And a read port for storing the input data through the write port and outputting the stored data through the read port.
And the timing at which the data stored in the second storage means is output via the read port by a predetermined delay time from the timing at which the data is input and stored via the write port of the second storage means. Control means for controlling the second storage means so as to write and read data with a delay, wherein the first storage means, the digital multiplication means, the digital filtering means, 2 is electrically connected in cascade so as to form a feedback path of an oscillation loop, and the nonlinear delay feedback digital oscillation circuit further includes an oscillation signal oscillated in the nonlinear delay feedback digital oscillation circuit. Parameter detecting means for detecting a predetermined parameter of the oscillation signal based on the data of Storing the characteristic data of the multiplied data of the amplification degree with respect to each parameter difference between the parameter detected by the means and the parameter difference between the input external setting parameter and the parameter detected by the parameter detecting means. And a third storage means for outputting the multiplication data of the amplification degree to the digital multiplication means based on Therefore, since the circuit of the present invention is composed of a digital circuit, it can oscillate with higher accuracy and stability than the conventional example, and can reproduce the same oscillation trajectory. In addition, the oscillation waveform can be automatically changed according to parameters set externally.

In the nonlinear delay feedback type digital oscillation circuit according to the second aspect, at least one of the data of the nonlinear characteristic, the multiplication data of the amplification degree, the filtering coefficient data, and the delay time. Is provided. Therefore, various parameters of the nonlinear delay feedback type oscillation circuit can be changed, and oscillation can be performed in various oscillation modes.

[0058]

[Brief description of the drawings]

FIG. 1 is a block diagram of a nonlinear delay feedback type digital oscillation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a digital filter 13 of FIG.

FIG. 3 is a graph showing an example of nonlinear characteristic data stored in an SRAM 11 of FIG. 1;

4 is a graph showing an example of an impulse response characteristic of the digital filter 13 of FIG. 2, which is a characteristic of an impulse response signal h (n) with respect to a time variable n.

FIG. 5 (7, 3) generated by the nonlinear delay-feedback digital oscillation circuit of FIG. 1 when μ = 0.766.
6 is a graph showing an oscillation waveform of oscillation.

FIG. 6 (7, c) when μ = 0.804 generated by the nonlinear delay feedback type digital oscillation circuit of FIG. 1;
6 is a graph showing an oscillation waveform of oscillation.

FIG. 7 is a graph showing an oscillation waveform of chaotic oscillation when μ = 0.916, generated by the nonlinear delayed feedback digital oscillation circuit of FIG. 1;

FIG. 8 is a graph showing an example of amplification degree data Dμ2 stored in the table ROM 53 of FIG. 1;

9 is a diagram illustrating a voltage signal Va of a first example of a third harmonic oscillation signal output from the D / A converter 16 and a threshold value for explaining the operation of the oscillation waveform evaluation circuit 40 of FIG. The voltage signal S1 output from the processor 41 and the pulse width expander 4
2 is a graph showing a voltage signal S2 output from the second embodiment.

10 is a diagram illustrating a voltage signal Va of a second example of a third harmonic oscillation signal output from the D / A converter 16 and a threshold for explaining the operation of the oscillation waveform evaluation circuit 40 of FIG. 5 is a graph showing a voltage signal S1 output from a processor 41 and a voltage signal S2 output from a pulse width expander 42.

FIG. 11 is a block diagram showing a basic configuration of a conventional nonlinear delay feedback oscillation circuit.

FIG. 12 is a block diagram of a conventional nonlinear delay feedback type opto-electric hybrid oscillation circuit using an optical fiber cable as a delay feedback path.

FIG. 13 is a circuit diagram of the coincidence detection circuit 22 of FIG. 1;

[Description of Signs] 10 ... MPU, 11 ... SRAM, 12 ... Digital Multiplier, 13 ... Digital Filter, 14 ... Dual Port RAM, 15 ... Keyboard, 16 ... Digital / Analog Converter (D / A Converter), 20 ... Memory control circuit, 21,23 ... Up counter, 22 ... Match detection circuit, 31,32,33 ... Data selector, 34,35 ... Latch circuit, 40 ... Oscillation waveform evaluation circuit, 41 ... Threshold processor, 42 ... Pulse width expander, 43 ... Counter, 44 ... Clear pulse generator, 51 ... Digital adder, 52 ... Absolute value calculator, 53 ... Table ROM, 61,63,66,67 ... Digital multiplier, 62,64 ... Digital adder, 65 ... 1 clock delay circuit, 71,72,73,74 ... Latch circuit.

Continuation of the front page (56) References JP-A-63-77203 (JP, A) JP-A-63-82021 (JP, A) JP-A-4-205796 (JP, A) JP-A-4-142519 (JP) , A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03B 28/00 H03B 29/00 H03H 17/08

Claims (2)

(57) [Claims] A first storage unit for storing data of a predetermined nonlinear characteristic at each address and outputting the stored data based on an input address; a multiplier for multiplying the input data by a predetermined amplification factor Digital multiplying means for multiplying data and outputting product data; digital filtering for performing impulse response processing on input data based on predetermined filtering coefficient data and outputting filtered and filtered data Means, having a write port and a read port, after storing the input data via the write port,
A second storage unit for outputting the stored data via the read port; and a timing for outputting the data stored in the second storage unit via the read port, the write port of the second storage unit. Control means for controlling the second storage means so as to write and read data with a delay of a predetermined delay time from the timing of inputting and storing the data via the first storage means, The digital multiplying means, the digital filtering means, and the second storage means are electrically connected in cascade so as to form a feedback path of an oscillation loop. A parameter for detecting a predetermined parameter of the oscillation signal based on data of the oscillation signal oscillated in the nonlinear delay feedback type digital oscillation circuit. Data of the characteristic of the multiplication data of the amplification degree for each difference of the parameter between the input external setting parameter and the parameter detected by the parameter detecting means, and the input external setting parameter A third storage means for outputting multiplication data of the amplification degree to the digital multiplication means based on a difference between the parameters detected by the parameter detection means and the parameters. Digital oscillation circuit. 2. The non-linear delay feedback type digital oscillation circuit further comprises: data for changing at least one of the non-linear characteristic data, the amplification multiplication data, the filtering coefficient data, and the delay time. 2. The nonlinear delay feedback type digital oscillation circuit according to claim 1, further comprising a change unit.