JPH0895937A - Chaos neuron circuit - Google Patents

Abstract

PURPOSE: To easily prepare a neuron element utilizing chaos characteristics by integrating a chaos circuit for generating a high-order chaos in place of a conventional amplifier on the output stage in a digital/analog neuron circuit. CONSTITUTION: This circuit is composed of field effect transistors(FET) 21 and 22, current mirror circuit 27 provided between the FET 21 and 22, differential amplifier circuit 28 and chaos circuit 30. Namely, this circuit is constituted as a chaos neuron circuit equipped with the chaos circuit for generating a high-order chaos in place of the conventional amplifier on the output stage. This chaos circuit 30 is composed of an adder/subtracter, multiplier, comparator, amplifier, further, reference vibration generating circuit and delay circuit. Namely, the circuit is provided with the reference vibration generating circuit, amplifier equipped with a delay feedback circuit and delay circuit for realizing a high-order chaos phenomenon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a neuron circuit that models the function of nerve cells in order to construct a neural network, and in particular, a chaotic neuron circuit that applies the chaos phenomenon to enable connection with digital equipment. Regarding

[0002]

2. Description of the Related Art An example of a conventional digital / analog neuron circuit is shown in "Neuron element circuit" described in JP-A-2-311972. As shown in FIG. 4 (corresponding to FIG. 1 of JP-A-2-311972), the above-mentioned digital / analog neuron circuit is a field effect transistor which operates in a saturation region when a weighting voltage V1 is applied to its gate. FET) 21, an FET 22 to which the output voltage V2 of the preceding neuron element is input to the drain, a current mirror circuit 27 provided between the FET 21 and the FET 22 for controlling the gate voltage of the FET 22, and an output of the FET 22. An operational amplifier 23 for addition, a differential amplifier circuit 28 composed of a bipolar transistor for generating a sigmoid function from the output of the operational amplifier 23, and an operational amplifier 24 at an output stage for outputting the difference between the voltage Vcc and the output from the differential amplifier circuit 28. It is composed of and. It should be noted that the reference numerals used here do not follow the reference numerals in the above publications, but are given unique reference numerals.

Incidentally, a sigmoid function f in a circuit for generating a sigmoid function (sigmoid function generating circuit)
(U) means “chaos in neural systems” edited by Kazuyuki Aihara, published by Tokyo Denki University Press, p185. As shown in p185, f (u) = 1 / {1 + exp (-u /
ε)}. Here, u represents a unit step function, and ε represents a constant representing the steepness of the slope of the above function (see the above-mentioned reference "Chaos in Neural System" p161).

In the low integration type digital / analog neuron circuit using the above-mentioned conventional operational amplifier and current mirror circuit, the gain is adjusted by the circuit of the analog part, and the connection with the existing electronic device is the digital part. A field effect transistor (FET) was used.

[0005]

However, in the above-mentioned conventional digital / analog neuron circuit described in Japanese Patent Application Laid-Open No. 2-311972, since information is a digital value, chaos generated in a transistor or an amplifier in the circuit. Since the chaotic vibration must be treated as noise, the chaotic characteristics cannot be positively used, and therefore the precision required for the components that make up the circuit is severe, and it is easy to make neuron elements. There was a problem that it could not be done.

The present invention has been made in view of the above circumstances. It is possible to easily perform chaos by incorporating a chaos circuit that generates high-order chaos in place of the conventional output stage amplifier in a digital / analog neuron circuit. It is an object of the present invention to provide a chaotic neuron circuit which can make a neuron element utilizing the characteristics.

[0007]

According to a first aspect of the present invention for solving the above-mentioned problems of the prior art, in a chaotic neuron circuit, an integrating circuit including a field effect transistor and a current mirror circuit and an operational amplifier are provided. A summing circuit, a sigmoid function generating circuit formed of bipolar transistors, and a chaotic circuit, the chaotic circuit adding and subtracting a difference between two inputs, and an amplifier including a delay feedback circuit, A reference vibration generating circuit for generating a reference vibration signal; and a delay circuit for delaying the signal, the reference vibration signal output from the reference vibration generating circuit being connected to the input of the amplifier, The output from the amplifier is connected to one input of the adder / subtractor, and the output from the adder / subtractor is input to the delay circuit. And the output from the delay circuit is connected to the other input of the adder / subtractor, and the output from the sigmoid function generating circuit is input to the other input of the adder / subtractor. The circuit is connected so that the output of the adder / subtractor is the output of the circuit.

A second aspect of the present invention for solving the above-mentioned problems of the conventional example is the chaotic neuron circuit according to the first aspect, in which the reference from the reference oscillation generating circuit is synchronized with the output from the sigmoid function generating circuit. It is characterized in that a frequency adjusting circuit for outputting a vibration signal to the amplifier is provided.

[0009]

According to the first aspect of the present invention, a chaos circuit is provided which has an integrating circuit, a summing circuit, and a sigmoid function generating circuit, and which generates high-order chaos instead of the conventional output stage amplifier. Since it is a chaotic neuron circuit, high-order chaotic characteristics can be easily used in the neuron circuit.

According to a second aspect of the present invention, the chaotic neuron circuit according to the first aspect, wherein the frequency adjusting circuit causes the reference oscillation signal in the chaotic circuit to be generated by the frequency adjusting circuit in synchronization with the output from the sigmoid function generating circuit. Because,
Since the output from the sigmoid function generating circuit and the reference signal in the chaotic circuit are synchronized, and the output from the sigmoid function generating circuit can be captured in the pure chaotic state,
The chaotic characteristic can be more positively utilized in the chaotic neuron circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. The chaotic neuron circuit according to the embodiment of the present invention is a neuron circuit in which a chaotic circuit for generating a higher order shown in FIG. 2 or 3 is incorporated instead of the operational amplifier 24 in the output stage of FIG. 4 and the resistor 26 attached thereto. It is possible to take advantage of the chaotic characteristics.

FIG. 1 is a configuration block diagram of a chaotic neuron circuit according to an embodiment of the present invention. The same components as those in FIG. 4 are designated by the same reference numerals. As shown in FIG. 1, the chaotic neuron circuit of this embodiment has a field effect transistor (FET) 21 which operates in a saturation region when a weighted voltage V1 is applied to its gate, and an output voltage V2 of a neuron element in the preceding stage to its drain. FET22 input,
A current mirror circuit 27 provided between the FET 21 and the FET 22 for controlling the gate voltage of the FET 22.
And a differential amplifier circuit 2 including an operational amplifier 23 that adds the outputs of the FET 22 and a bipolar transistor that generates a sigmoid function from the output of the operational amplifier 23.
8 and a chaos circuit 30, which is a characteristic part of this embodiment, to which the voltage Vcc and the output from the differential amplifier circuit 28 are input.

Next, the chaotic circuit 30, which is a characteristic part of this embodiment, will be specifically described with reference to FIGS.
2 is a circuit configuration diagram of a chaotic circuit incorporated in the chaotic neuron circuit of the present embodiment, and FIG. 3 is a circuit configuration diagram of another chaotic circuit incorporated in the chaotic neuron circuit of the present embodiment.

First, the chaos circuit of FIG. 2 will be described. The chaos circuit of FIG. 2 includes an adder / subtractor 3, a multiplier 4, and
It comprises a comparator 5, amplifiers 6a, 6b and 6c, a reference vibration generating circuit 7 and a delay circuit 8. Here, an amplifier 6b having a reference vibration generating circuit 7 and a delay feedback circuit and a delay circuit 8 are provided to realize a higher-order chaotic phenomenon. still,
The basic operations of the adder / subtractor 3, the multiplier 4, the comparator 5, and the amplifier 6 are as widely known in general, and therefore a detailed description thereof will be omitted here.

The connection relationship of the chaotic circuit shown in FIG.
The output of c is input to the delay circuit 8, the output of the delay circuit 8 and the voltage (reference potential) of + Vcc supplied from the power supply are input to the amplifier 6a, and the output of the amplifier 6a is input to the multiplier 4 for multiplication. The output of the differential amplifier circuit 28 is added to the output of the amplifier 4 and is input to one terminal of the adder / subtractor 3, and the output of the reference vibration generating circuit 7 is input to the amplifier 6b, and the output of the amplifier 6b is added / subtracted. 3 is input to the other terminal, the output of the adder / subtractor 3 is branched, one is input to the amplifier 6c, the other is input to the comparator 5, and the comparator 5
Therefore, the output of the chaotic circuit of this embodiment can be obtained.

The input part of the amplifier 6b is grounded via a resistor r, and the input part of the amplifier 6c is grounded via a capacitance C. A resistor R is used as a delay feedback circuit for the amplifiers 6b and 6c.

Here, the reference vibration generating circuit 7 of the present embodiment.
Is a reference vibration generating circuit using a crystal oscillator, for example. Further, the reference vibration generating circuit 7 may be a reference vibration generating circuit that generates a periodic clock using an electric relay circuit.

Further, in the chaos circuit of FIG. 2, in order to generate higher-order chaos, the delay circuit 8 composed of the variable resistor VR and the variable capacitor VC is provided for feedback of the feedback circuit from the amplifier 6c to the amplifier 6a. ing.

The delay circuit 8 has a configuration in which a variable resistor VR and a variable capacitor VC are connected in parallel.
And the value of the variable capacitor VC are adjusted to change the delay time and generate a periodic signal (periodic attractor) or a quasi-periodic signal (quasi-periodic attractor) or a chaotic signal (aperiodic attractor). It is what makes me.

Further, even if the delay circuit 8 is constituted by connecting the variable resistor VR and the variable capacitor VC in series, the delay time can be changed and an attractor similar to the above can be generated.

Next, the operation of the chaotic circuit shown in FIG. 2 will be described. As shown in FIG. 2, the output from the amplifier 6c is input to the delay circuit 8, the output is delayed by the delay circuit 8, and the signal to which the voltage of + Vcc supplied from the power supply is added to the output is input to the amplifier 6a. The output from the amplifier 6a is multiplied by a constant k (electrically constant level signal) in the multiplier 4, and the output from the differential amplifier circuit 28 as an external input is added to the output from the multiplier 4, Further, the output from the reference vibration generating circuit 7 is input to the amplifier 6b, and the difference between the output from the amplifier 6b and the signal obtained by adding the external input to the output from the multiplier 4 is taken by the adder / subtractor 3 to obtain the amplifier. 6c is input. Here, the output from the adder / subtractor 3 is branched and input to the comparator 5, and the output from this comparator 5 becomes the output of the chaos circuit of this embodiment.

The constant k represents a refractory time decay constant, and its value is determined within the range of 0≤k <1 ("Chaos [Basics and Applications of Chaos Theory]" Kazuyuki Aihara. Edited by Science Publishing, p300-p301).

Since the resistor R is provided as the delay feedback circuit in the amplifier 6b, the amplitude of the signal input from the reference vibration generating circuit 7 to the amplifier 6b is affected by the delay time depending on the value of the resistor R. It may be shaking. This swaying state is caused by the chaos phenomenon, and this state can be realized by adjusting the gain (actually, the resistance ratio by the resistor R) of the input stage or the output stage of the amplifier 6b.

The feedback signal amplified by the amplifier 6a is multiplied by a constant k in the multiplier 4 by using the signal in a swaying state output from the amplifier 6b, and further externally input (output of the differential amplifier circuit 28). The difference between the signal and
Then, the comparator 5 generates a chaotic signal.

The delay feedback circuit of the amplifier 6b in FIG. 2 is realized by using a resistor R, but a CCD (Charge Coupled D) that sequentially shifts and outputs the accumulated charges is output.
It is also possible to use a capacitor C, a variable resistor VR, a variable capacitor VC, or a resistor R.
An element in which the capacitor C and the capacitor C are connected in parallel may be used, or an element in which the variable resistor VR and the variable capacitor VC are connected in parallel may be used. The variable capacitor VC can also be realized by changing the parallel capacitance of the capacitors using a relay, for example.

Next, the chaos circuit of FIG. 3 will be described. The chaos circuit of FIG. 3 is provided with a frequency adjusting circuit 9 for synchronizing the external input with the reference frequency, based on the chaos circuit of FIG. ing. This chaotic circuit can change the allowable range of high-order chaos generated by the chaotic circuit with respect to the input signal.

The frequency adjusting circuit 9 in the chaos circuit of FIG. 3 is specifically a frequency divider 9 for dividing the frequency of the input signal.
a and an AND gate multiplier 9b, the product (AND) of the signal divided by the frequency divider 9a and the reference frequency output from the reference vibration generating circuit 7 is taken by the multiplier 9b and is then amplified. It is output to 6b. That is, by synchronizing the external input signal with the reference frequency, the external input signal can be taken into a pure chaotic state. Here, the external input signal is a signal output from the differential amplifier circuit 28.

According to the chaos circuits of FIGS. 2 and 3, the reference vibration signal generated from the reference vibration generating circuit 7 is used as the signal whose amplitude is fluctuated by the amplifier 6b having the delay feedback circuit, and this fluctuation is caused. The differential amplifier 28 receives the status signal and the delayed feedback signal from the delay circuit 8 provided in the feedback section from the amplifier 6c to the amplifier 6a.
Since the difference from the signal added with the output from is added and subtracted by the adder / subtractor 3 and the signal in the chaotic state is output from the comparator 5, for example, JP-A-1-147657.
As compared with the conventional chaos circuit described in Japanese Patent Publication, it is not necessary to set the order parameter of the timing φ at which the switch for generating chaos is turned on / off.
There is an effect that it is possible to prevent the history of the previous data from being dragged due to the interaction of other circuits due to improper order parameter setting, and to easily realize a high-order chaotic neuron circuit that generates a good chaotic state.

Further, according to the chaos circuit of FIG. 3, since the frequency adjusting circuit 9 can obtain the reference vibration signal synchronized with the external input signal, the external input signal is synchronized with the reference frequency. By taking the effect, there is an effect that the external input signal can be taken into the pure chaotic state.

According to the chaotic neuron circuit of this embodiment, the FET 21 that operates in the saturation region corresponding to the number of neuron elements in the preceding stage, the current mirror circuit 27, the operational amplifier 23 that performs current addition, and the sigmoid function generating circuit are provided. A differential amplifier circuit 28 formed of bipolar transistors and a reference potential (power supply voltage) of the output voltage
Vcc and the chaos circuit 30 of FIG. 2 or 3 for adjusting the amplitude
Therefore, the accuracy of the integrating circuit is improved by the configuration of the FET 21, the current mirror circuit 27, and the operational amplifier 23, and the power consumption is reduced by the sigmoid function generating circuit by the differential amplifier circuit 28 using bipolar transistors. In addition, since the chaotic circuit of FIG. 2 or 3 is incorporated, the neuron circuit can easily use high-order chaotic characteristics.

In particular, according to the chaotic neuron circuit incorporating the chaotic circuit of FIG. 2 or 3, even if the information is a digital value in the digital / analog neuron circuit, the chaotic circuit of FIG. 2 or 3 is output to the output stage. Since the circuit is provided, chaotic vibrations generated by transistors and amplifiers in the circuit are not treated as noise, and the chaotic characteristics can be positively used.
Therefore, there is an effect that it is not necessary to make the precision required for the components constituting the circuit strict, and a neuron element utilizing the chaotic characteristics can be easily manufactured.

Further, according to the chaotic neuron circuit incorporating the chaotic circuit of FIG. 3, the frequency adjusting circuit 9 generates the reference signal in the chaotic circuit in synchronization with the signal output from the differential amplifier circuit 28. Therefore, the signal from the differential amplifier circuit 28 and the reference signal in the chaotic circuit are synchronized, and the signal from the differential amplifier circuit 28 can be taken into a pure chaotic state. Further, there is an effect that the chaotic characteristic can be positively utilized.

[0033]

According to the first aspect of the present invention, a chaotic circuit having an integrating circuit, a summing circuit, and a sigmoid function generating circuit for generating high-order chaos instead of the conventional output stage amplifier. Since the chaotic neuron circuit is provided with, there is an effect that the high-order chaotic characteristic can be easily used in the neuron circuit.

According to the second aspect of the present invention, the chaotic neuron circuit according to the first aspect, wherein the frequency adjusting circuit causes the reference oscillation generating circuit to generate the reference signal in the chaos circuit in synchronization with the output from the sigmoid function generating circuit. Because,
Since the output from the sigmoid function generating circuit and the reference signal in the chaotic circuit are synchronized, and the output from the sigmoid function generating circuit can be captured in the pure chaotic state,
There is an effect that the chaotic characteristic can be more positively utilized in the chaotic neuron circuit.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a chaotic neuron circuit according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a chaotic circuit incorporated in the chaotic neuron circuit of this embodiment.

FIG. 3 is a circuit configuration diagram of another chaotic circuit incorporated in the chaotic neuron circuit of the present embodiment.

FIG. 4 is a circuit diagram of a conventional digital / analog neuron circuit.

[Explanation of symbols]

3 ... Adder / subtractor, 4 ... Multiplier, 5 ... Comparator,
6 ... Amplifier, 7 ... Reference vibration generating circuit, 8 ... Delay circuit, 9 ... Frequency adjusting circuit, 21, 22 ... FET,
23 ... Operational amplifier, 27 ... Current mirror circuit, 2
8 ... Differential amplifier circuit, 30 ... Chaotic circuit

Claims (2)

[Claims] 1. A chaotic circuit comprising: an integrating circuit including a field effect transistor and a current mirror circuit; a summing circuit including an operational amplifier; a sigmoid function generating circuit formed of bipolar transistors; and a chaotic circuit. Is provided with an adder / subtractor that takes the difference between two inputs, an amplifier that includes a delay feedback circuit, a reference vibration generation circuit that generates a reference vibration signal, and a delay circuit that delays the signal. The reference oscillation signal output from the circuit is connected to the input of the amplifier, the output from the amplifier is connected to one input of the adder / subtractor, and the output from the adder / subtractor is The input from the delay circuit is connected to the input, and the output from the delay circuit is connected to the other input of the adder / subtractor, Further, the chaotic neuron circuit is characterized in that the output from the sigmoid function generating circuit is connected so as to be inputted to the other input of the adder / subtractor, and the output of the adder / subtractor is used as the output of the circuit. 2. A chaotic neuron circuit according to claim 1, further comprising a frequency adjusting circuit for outputting a reference vibration signal from the reference vibration generating circuit to the amplifier in synchronization with an output from the sigmoid function generating circuit. .